Lecture Digital logic design - Lecture 20: Sequential circuits: Latches

The following will be discussed in this chapter: Circuits require memory to store intermediate data; sequential circuits use a periodic signal to determine when to store values; single bit storage element is a flip flop; a basic type of flip flop is a latch; latches are made from logic gates.

Lecture 20

Sequential Circuits: Latches

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° Circuits require memory to store intermediate data

° Sequential circuits use a periodic signal to determine when to store values.

• A clock signal can determine storage times

• Clock signals are periodic

° Single bit storage element is a flip flop

° A basic type of flip flop is a latch

° Latches are made from logic gates

• NAND, NOR, AND, OR, Inverter

Combination Vs Sequential

° Combinational Circuits

• Combinational circuits have only input and output

Output depends on input.

• Example: AND,OR,NAND,NOR,XOR etc

° Sequential Circuits

• Sequential circuits have input, present state, next state

and output Next state depends upon present state and input Output depends upon present state and input

• Example: Flip-Flops etc

° A Sequential Circuit can be defined as circuit having

sequential logic Sequential logic is a type of a logic circuit whose output depends not only on current inputs but also

What exactly is memory?

° A memory should have at least three properties

1 It should be able to hold a value.

2 You should be able to read the value that was saved

3 You should be able to change the value that’s saved

A one-bit bi-stable memory

1 It should be able to hold a single bit, 0 or 1 (two possible stable states)

2 You should be able to read the bit that was saved

3 You should be able to change the value Since there’s only a single bit,

there are only two choices:

Bi-stable Binary Storage Elements

° Simple Circuits with Feedback

• Primitive memory elements created from cascaded gates

• Simplest gate component: inverter

• Basis for commercial static RAM designs

• Cross-coupled NOR gates and NAND gates also possible

Static Memory Cell

The story so far

° Logical operations which respond to combinations

of inputs to produce an output

• Call these combinational logic circuits.

° For example, can add two numbers But:

• No way of adding two numbers, then adding a third (a sequential

operation);

• No way of remembering or storing information after inputs

have been removed.

° To handle this, we need sequential logic capable of

storing intermediate (and final) results.

Basic structure

° The basic structure of a synchronous sequential

circuit is shown here.

° Synchronous – One input is a clock and on the

clock the next state becomes the present state of

the system.

° Sequential – The circuit transitions between states

in a regular manner.

° Inputs – All the outside logic signal inputs to the circuit

Typically, the clock is not consider part of the signal inputs

of the circuit.

° Outputs – The logic signal outputs.

° Present State – the logic value of all the state variables of

the system These are stored in the state memory.

state

Timing signal (clock)

Clock

Clock

a periodic external event (input)

Clock

a periodic external event (input)

synchronizes when current state changes happen

keeps system well-behaved

synchronizes when current state changes happen

keeps system well-behaved makes it easier to design and build large systems

° To figure out how Q and Q’ change, we have to look at not only the

inputs S and R, but also the current current values of Q and Q’:

Q next = (R + Q’ current )‘

Q’ next = (S + Q current )‘

° Let’s see how different input values for S and R affect this thing

Q: 1-bit state variable

Storing a value: SR = 00

° What if S = 0 and R = 0?

° The equations on the right reduce to:

Q next = (0 + Q’ current )’ = Q current Q’ next = (0 + Q current )’ = Q’ current

° So when SR = 00, then Q next = Q current

Whatever value Q has, it keeps

° This is exactly what we need to store

values in the latch.

Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

Setting the latch: SR = 10

So when SR = 10, then Q’ next = 0 and Q next = 1

° This is how you set the latch to 1 The S input stands for “set”

° Notice that it can take up to two steps (two gate delays) from the time S becomes

1 to the time Q next becomes 1

° But once Q next becomes 1, the outputs will stop

changing This is a stable state

Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

Resetting the latch: SR = 01

° What if S = 0 and R = 1?

° Since R = 1, Q next is 0, regardless of Qcurrent :

Q next = (1 + Q’ current )’ = 0

° Then, this new value of Q goes into the bottom

NOR gate, where S = 0

Q’ next = (0 + 0)’ = 1

° So when SR = 01, then Q next = 0 and Q’ next = 1

° This is how you reset , or clear , the latch to 0 The R

input stands for “reset”

Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

SR latches are memories!

° This little table shows that our

latch provides everything we

need in a memory: we can set

it, reset it, and remember the

current value.

° The output Q represents the

data stored in the latch, which

is called as the state of the

latch.

° We can expand the table

above into a state table , which

explicitly shows that the next

values of Q and Q’ depend on

their current values, as well as

on the inputs S and R.

SR latches are sequential!

° Notice that for inputs SR = 00 ,

the next value of Q could be

either 0 or 1, depending on the

current value of Q

° So the same inputs can yield

different outputs, depending

on whether the latch was

previously set or reset

° This is very different from the

combinational circuits that

we’ve seen so far, where the

same inputs always yield the

What about SR = 11?

° Both Qnext and Q’ next will become 0

° This contradicts the assumption that Q

and Q’ are always complements

° Another problem is what happens if we

take S = 0 and R = 0 together.

Q next = (0 + 0)’ = 1 Q’ next = (0 + 0)’ = 1

° But these new values go back into the

NOR gates, and in the next step we get:

Q next = (0 + 1)’ = 0 Q’ next = (0 + 1)’ = 0

° The circuit enters an infinite loop, where

Q and Q’ cycle between 0 and 1 forever

Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

S-R Latch with NORs

SR Latch Symbols

Characteristic Table

° In order to remember previous inputs, sequential circuits

must have some sort of storage element This storage

element is called “flip-flop”.

° Flip-flop depends on previous inputs to the circuit.

° The basic memory unit is called an SR flip-flop.

° We can describe flip-flops using characteristic table.

SR Flip-Flop operation (BUILT WITH NOR GATES)

Characteristic table Excitation table

°1 °0

Review: Steering Gates

° The flow of logic can be controlled with a logic

An SR latch with a control input

° Here is an SR latch with a control input C

° Notice the hierarchical design!

• The dotted blue box is the S’R’ latch from the previous slide

• The additional NAND gates are simply used to generate the correct

S-R Latch with NANDs

° Latch made from cross-coupled NANDs

° Sometimes called S’-R’ latch

° Usually S=1 and R=1

° S=0 and R=0 generates unpredictable results

S-R Latches

S-R Latch with control

input

° Occasionally, desirable to avoid latch changes

° C = 0 disables all latch state changes

° Control signal enables data change when C = 1

° Right side of circuit same as ordinary S-R latch

Outputs change when C is low:

Outputs change when C is low:

Latch is level-sensitive, in regards to C

Latch is

Latch is level-sensitive level-sensitive , in regards to C

Only stores data if C’ = 0

Problems with SR Latch

° The problem with the SR Latch is that it requires

two inputs to store one value.

° A latch is needed where one input is applied to

store one value.

° A control input is also required to place the device

in a hold state.

° Moreover there is a race condition (undefined)

° Input value D is passed to output Q when C is high

° Input value D is ignored when C is low

D Latch

    E 

x

Latches on following edge of clock

E 

D  Q  C

x

z

z

° Z only changes when E is high

° If E is high, Z will follow X

D Latch

    E 

x

Latches on following edge of clock

E 

D  Q  C

Symbols for

Latches

° SR latch is based on NOR gates

° S’R’ latch based on NAND gates

° D latch can be based on either.

° S-R latches operate like cross-coupled inverters with

control inputs (S = set, R = reset)

° With additional gates, an S-R latch can be converted to

a D latch ( D stands for data )

° D latch is simple to understand conceptually