Development and characterization of high k dielectric germanium gate stack

List of Symbols χ Electron affinity of a semiconductor ε0 Permittivity of free space ϕ Electron barrier height μe Mobility of electron μeff Effective mobility μh Mobility of hole

DEVELOPMENT AND CHARACTERIZATION OF HIGH-K DIELECTRIC/GERMANIUM GATE STACK

XIE RUILONG

(B.Eng (Hons.), NUS)

A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE

DECEMBER 2009

To Guo Qian

ACKNOWLEDGMENTS

First and foremost, I would like to express my deepest gratitude to my principle advisor, Professor Zhu Chun Xiang for his knowledge, constant guidance and encouragement throughout the course of my research He was always there to listen and

to give advice He showed me different ways to approach a research problem and the need to be persistent to accomplish any goal

I would like to gratefully thank my co-supervisors Dr Yu Ming Bin for his kindly support and all the opportunities provided in collaboration with Institute of Microelectronics, and Professor Li Ming Fu for his valuable suggestions and the fruitful discussions I am also very grateful to Chartered Semiconductor Manufacturing, Ltd for the financial support and to Dr Chan Lap and Dr Ng Chee Mang not only for their teaching and training but also for their valuable advice on my future career

I would like to express my warmest thanks to Dr Wu Nan and Dr Zhang Qing Chun for many stimulating and joyful discussions Special thanks to Sun Zhi Qiang, He Wei, and Shen Chen for their important helps in experiments and device characterizations

I would like to thank my colleagues in Prof Zhu’s group, such as Yu Xiong Fei, Huang Ji Dong, Zhang Chunfu, Song Yan, Fu Jia, Yang Jian Jun and Phung Thanh Hoa, for their discussions and supports Many thanks to my peers in SNDL: Ren Chi, Wang Xin Peng, Gao Fei, Chen JingDe, Rinus Lee, Zang Hui, Jiang Yu, Pu Jing, Zhang Lu, Yang Wei Feng, Wang Jian, Peng Jian Wei, Chin Hock Chun and Liu Bin I have benefited the

enjoyable I also would like to extend my appreciation to all other SNDL teaching staff, fellow graduate students, and technical staff

I also would like to express my appreciation to Ma Yu Wei and Du Guo An from Chartered SP group for their valuable discussions

Last but not least, my deepest thanks to my wife, Guo Qian, whose tremendous understanding and support throughout those four years have made this work possible Special recognition also belongs to my parents, who through my childhood and study career had always encouraged me to follow my heart and inquisitive mind in any direction

TABLE OF CONTENTS

ACKNOWLEDGEMENTS III

1 Introduction

1.1 Challenges of MOSFETs scaling and possible solutions … …… …… … 1

1.2 High-k gate dielectrics……… ……… 3

1.2.1 Limits of SiO2 scaling……….……… ……….… 3

1.2.2 Alternative gate dielectrics……….……….… 5

1.3 Ge MOSFETs……… ……… … …….……… 8

1.4 Current status of Ge channel MOS devices with high-k dielectric…… … ……11

1.5 Thesis outline and original contributions ……… ………23

References……… ……… …… 25

2 Effects of Sulfur Passivation on High-k/Ge Gate Stack

2.1 Experiments……… ………32

2.2 Results and discussions……… 32

2.3 Conclusions…….………… ……….………44

References……… ……… ……….45

3 Effects of Silicon Nitride Passivation on High-k/Ge Gate Stack 3.1 Experiments……… … ……… …….…….………… …… 48

3.2 Physical effects of silicon nitride passivation……… ……… …… … 48

3.3 Electrical effects of silicon nitride passivation……….……….………54

3.4 Conclusions……… ……….……….59

References……… ……… ……….61

4 High-k Gate Stack on Germanium Substrate with Fluorine Incorporation 4.1 Principle and criteria of post gate treatment ……… ……… 64

4.2 Effects of F incorporation without pre-gate surface passivation…… …… 67

4.2.1 Experiments…….… ……….…….………….………… … ….67

4.2.2 Results and discussions…… ……….……… ………… … ….68

4.2.3 Summary…… ……… ……….73

4.3 Effects of fluorine incorporation with Si pre-gate surface passivation…… ……74

4.3.1 Experiments……… ……… ……… ……… … ….74

4.3.2 Results and discussions…… ……….…… ……… ………… … ….75

4.4 Conclusions……… ……… ……….……… 80

References……….……….82

5 Interface Engineered High Mobility High-k/Ge pMOSFETs with 1 nm Equivalent Oxide Thickness 5.1 Effects of F incorporation and FGA on TaN/HfO2/GeO2/Ge MOS capacitors….86 5.1.1 Experiments…….……….……….…….……… … ….86

5.1.2 Results and discussions…… ……… ….… ……… … ….87

5.1.3 Summary…….……… ……….94

5.2 Ge pMOSFEs with 1 nm EOT……… ……… …… 94

5.2.1 Device performance of Ge pMOSFETs……… ……… ….94

5.2.2 Interface characterization…… …… … ……… ………… ….….100

5.2.3 Discussions…… ……….……… ……….108

5.3 Conclusions……… ……… ….109

References……… ………110

6 Energy Distribution of Interface Traps in Germanium

Metal-Oxide-Semiconductor Field Effect Transistors with HfO 2 Gate Dielectrics and Its

Impact on Mobility

6.1 Experiments……….… ……….………115

6.2 Results and discussions……… ……… …… 116

6.3 Conclusions…….……… ……… …….………121

References……… ……… ………122

7 Conclusions and Recommendations 7.1 Conclusions……… ……… …….…….……… … …….124

7.2 Recommendations for future work… ……… …… ……… … 128

References……… ……… … ……….131

Appendix – Computer Programs 132

List of Publications

ABSTRACT

Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of the past 40 years However, as the metal-oxide-semiconductor field-effect transistors (MOSFET) continues to scale down to tens of nanometers, Si/SiO2 based device is approaching its fundamental limits, the motivation for alternative gate stacks has increased considerably High-k/Ge gate stack is very promising for future nanoscale devices because it improves the device performance in terms of both drive current and power consumption The most important technical issue for high-k/Ge MOSFET technology is the passivation of the Ge surface

In this study, two approaches to improve the high-k/Ge interface qualities were investigated The first approach was using pre-gate surface passivation for high-k/Ge gate stack Two pre-gate surface passivation techniques were investigated The first one was the sulfur passivation We found that the Ge diffusion was suppressed by introducing sulfur atoms at high-k/Ge interface, due to less GeOx (x < 2) formation, and consequently,

the interface trap density (Dit) was significantly reduced However, device with sulfur passivation presented a large amount of hysteresis The second one was silicon nitride passivation by SiH4-NH3 treatment This was an improved version of Si passivation We found that ultrathin silicon nitride layer was more effective to suppress the Ge diffusion

than ultrathin Si layer Moreover, the unexpected positive threshold voltage shift was also eliminated by using silicon nitride passivation, which was attributed to the suppressing of interfacial dipole formation

The second approach to improve the high-k/Ge interface quality is to adopt proper post-gate treatment processes For the first time, we proposed and demonstrated a post-gate CF4 plasma treatment process to incorporate fluorine (F) into high-k/Ge gate stacks

We found that F tends to segregate at high-k/Ge interface upon thermal annealing and both the interface quality and high-k bulk quality were significantly improved by F incorporation This was attributed to the Ge-F and Hf-F bonds formation at interface and

in the bulk high-k, respectively The post-gate treatment was found to be compatible with pre-gate surface passivation By applying both techniques on high-k/Ge gate stack, the optimum interface quality was able to be achieved

Variable rise/fall time charge pumping method was also used to characterize the interface properties of Ge MOSFETs We found that F passivation was capable to reduce interface traps that located in the both bottom half and upper half of the Ge bandgap It

was also observed that Dit distribution in Si passivated Ge MOSFETs was asymmetric with much higher density in the upper half of the Ge bandgap Those traps can act as Coulomb scattering centers when the MOSFETs operate under inversion, which can be possible cause of severe electron mobility degradation for Ge nMOSFETs

List of Figures

Fig 1.1 Tradeoff factors among short-channel effects, on current (Ion) and power

consumption under simple device scaling and possible solutions to mitigate the relationship Critical device or physical parameters to provide the

tradeoff, such as power-supply voltage Vdd and threshold voltage Vth , are shown between the two indexes, and also, the physical mechanisms causing the tradeoffs are shown inside the boxes

2

Fig 1.2 (Left) Schematic energy band diagram of an n-Si/SiO2/metal gate structure,

illustrating direct tunneling of electrons from the Si substrate to the gate ϕ is

the energy barrier height at the Si/SiO 2 interface, V ox , the potential drop in the SiO2 layer and VG, the applied gate voltage (Right) Simulated tunneling current through a MOS as a function of the potential drop in the gate oxide,

Vox, for different SiO2 gate layer thickness Shaded areas represent the maximum leakage current specified by the ITRS for high performance and low operating power application, respectively

Fig 2.4 Fig 2.4 XPS data in Ge 2p region from Ge(100) substrates after only HF

clean or after HF + (NH 4 ) 2 S treatment The dot lines are deconvoluted peaks for sample with (NH4)2S treatment

34

Fig 2.5 SIMS profiles for HfON/Ge gate stack after 500 o C PDA in N 2 ambient for

30s

36

Fig 2.6 Capacitance-Voltage characteristics of TaN/HfON/Ge capacitors (a) with

(NH 4 ) 2 S treatment, (b) without (NH 4 ) 2 S treatment, after a 550°C PMA, in N 2

ambient for 30s

37

Fig 2.7 Capacitance–voltage curves measured at 100 kHz, 500 kHz, and 1 MHz for 39

Fig 2.8 High-frequency C-V measurement of MOS capacitor at 50 kHz (square),

100 kHz (cross), and 1 MHz (circle) C-V characteristics depend on

frequency in the parallel circuit model As-deposited Sm2O3 on TaN is shown

to be likely poly-crystalline

39

Fig 2.9 Frequency dispersion characteristics of TaN/HfON/Si capacitors The

dispersion at accumulation region is attributed to the parasitic resistance

40

Fig 2.10 EOT values with different surface treatment and post metal annealing

temperatures Sulfur passivated samples show about 0.7nm thinner EOT

41

Fig 2.11 Gate leakage current density as a function of EOT with different surface

treatment and PMA temperatures together with published data

42

Fig 2.12 Typical Ig-Vg curves of Ge MOS Capacitors with different surface treatment

and PMA temperatures

43

Fig 2.13 Cumulative probability of leakage current densities of Ge MOS capacitors

with different surface treatments and PMA temperatures

43

Fig 3.1 (a) High resolution XPS data in (a) Ge 2p and (b) N 1s for Ge wafers after

SiH 4 or SiH 4 -NH 3 treatment Ultrathin (~6Å) Si passivation layer by SiH 4

treatment can not adequately prevent GeOx formation at Ge surface when sample is exposed to oxidized ambient (e.g air)

49

Fig 3.2 SIMS profiles for HfO2 gated Ge MOS capacitors with Si passivation (dash)

and silicon nitride (SN) passivation (solid) Red: N Blue: Si Green: Ge Ta: Black

50

Fig 3.3 Schematic illustration of better passivation effects by silicon nitride layer

After thermal treatments, ultrathin Si layer can be oxidized, especially when HfO 2 thickness is large and subsequently, volatile GeO could be formed and results serious Ge out-diffusion Introduction of N can suppress volatile GeO formation at high-k/Ge interface

50

Fig 3.4 Summary of the dipole moment formed at high-k/SiO2 interface predicted

by our model, for various high-k candidates including GeO 2 The dipole

direction to increase VFB is represented as a positive direction

53

(b)HfO 2 /MO x /Ge gate stack (M = Y, La or Sr)

Fig 3.6 C-V characteristics of HfO2 gated Ge MIS capacitors with (a) Si passivation

and (b) SN passivation measured at 1MHz, 800kHz, 500kHz, 300kHz, 200kHz, 100kHz, 80kHz, 50kHz, 30kHz, 20kHz and 10kHz

54

Fig 3.7 Gate leakage current densiy for samples with Si passivation and SN

passivation Smaller Jg is observed for devices with SN passivation

55

Fig 3.8 Well-behaved Id-Vg characteristics for Ge pMOSFETs (L = 5 μm) with (a) Si

passvation and (b) SN passivation

55

Fig 3.9 Rise and fall time dependence of charge pumping (CP) currents (t r = t f =

100, 200, 300, 400, 500, 600, 700, 800, and 900 ns) for samples with (a) Si passivation and (b) SN passivation The area is 14400μm 2 , amplitude is 1V and frequency is 200 kHz

57

Fig 3.10 Qcp(= Icp/f) as a function of In(t r ×t f) 1/2 that provides the mean Dit for samples

with Si or SN passivation

57

Fig 3.11 Hole mobility as a function of vertical effective vertical field for Ge

pMOSFETs (L = 5μm) with Si or SN passivation

58

Fig 3.12 Id-Vd for Ge pMOSFETs (L = 5 μm) About 52% enhanced drive current is

obtained for SN passivated device at Vg-Vt = -1.2V and Vd= -2V

58

Fig 4.1 Concept of interface engineering processes: Pre-gate passivation and

Post-gate dielectric treatment

65

Fig 4.2 (a) F incorporation to high-k dielectric during CF4-plasma treatment (b)

Various mechanisms that can take place during the subsequent PDA or S/D activation annealing process for devices with CF 4 -plasma treatment

67

Fig 4.3 SIMS depth profile for samples with and without CF 4 -plasma treatment F

was incorporated in the bulk high-k dielectric and high-k/Ge interface

69

Fig 4.4 F 1s XPS spectrum for samples with and without CF 4 -plasma treatment on

HfO2/Ge gate stack

69

Fig 4.5 Fig 4.5 C-V frequency dispersion characteristics for samples (a): with 70

Fig 4.6 Ig-Vg characteristics for samples with and without CF4-plasma treatment 72

Fig 4.7 Cumulative probability of breakdown voltages for samples with and without

CF4-plasma treatment

72

Fig 4.8 Samples with both Si passivation and CF4-plasma treatment show excellent

high frequency C-V characteristics

75

Fig 4.9 C-V frequency dispersion characteristics for SP samples (a) without

CF 4 -plasma treatment and (b) with CF 4 -plasma treatment for 3 min Both

frequency-dependent ΔVfb and stretch-out disappear for CF4 treated samples

76

Fig 4.10 Comparison of frequency dependent flat band voltage shift for samples with

different pre-gate or post-gate treatment conditions

76

Fig 4.11 Frequency dependent conductance G p/ω for a series of gate voltages for SP

samples w/o F treatment, with F treatment for 1 min, and with F treatment for min, respectively

78

Fig 4.12 Plot of Dit vs energy relative to the valence band edge for samples w/o CF 4

treatment, with CF4 treatment for 1- and 3- min, respectively Interface quality is greatly improved after CF 4 -plasma treatment

78

Fig 4.13 Output characteristics for Ge pMOSFETs with Si passivation and

CF 4 -plasma treatment for different duration Enhanced drive currents were achieved after CF4 plasma-treatment

79

Fig 4.14 Left: effective hole mobility in Ge pMOSFETs versus effective field for

silicon passivated devices with different CF4 treatment conditions without

correction Right: peak μeff after correction together with other reported data

80

Fig 5.1 Splits for post gate treatments scheme for TaN/HfO2/GeO2/Ge MOS

capacitors

87

Fig 5.2 Angle resolved XPS Ge 3d spectra for germanium samples after the thermal

oxidation at 400oC The thickness of GeO 2 is about 2 nm

88

Fig 5.3 SIMS profiles for TaN/HfO2/GeOx/Ge gate stack after PDA and FGA The 88

treatment process Other curves are taken from CF 4 treated samples

Fig 5.4 Capacitance-voltage characteristics of TaN/HfO 2 /GeO x /Ge gate stacks (~ 2

nm GeO2 and 4.5 nm HfO2 ) measured at 1Mhz, 900kHz, 800kHz,…, 200kHz, 100kHz, 90kHz, 80kHz,…, 20kHz and 10kHz (a) with neither CF4plasma treatment nor FGA; (b) with CF 4 plasma treatment for 3 min but without FGA; (c) without CF4 plasma treatment but with FGA; (d) with both

CF 4 plasma treatment and FGA

89

Fig 5.5 Frequency dependent flat band voltage shifts (ΔV) and Equivalent oxide

thickness (EOT) for samples both with and without FGA of different CF 4

treatment conditions

90

Fig 5.6 I g -V g characteristics for forming gas annealed samples with different CF4

plasma treatment conditions

92

Fig 5.7 Typical frequency dependent conductance Gp/ω for a series of gate voltage

for forming gas annealed samples without CF 4 plasma treatment and samples with CF4 plasma treatment for 3 min

92

Fig 5.8 Extracted midgap Dit for FGA annealed samples with different F treatment

conditions

93

Fig 5.9 Split C-V obtained for a 200μm × 10μm pMOSFET 95

Fig 5.10 Gate-leakage-current density as a function of EOT together with published

data

96

Fig 5.11 Linear I d -V g and G m -V g obtained for 200μm × 10μm pMOSFETs Device

with F incorporation shows higher I d and G m

97

Fig 5.12 Hole mobility as a function of vertical effective field for 200μm × 10μm

pMOSFETs, with and without F incorporation The mobility enhancement is maintained for large field Right figure shows the comparison of peak hole mobility with previous reported record values

97

Fig 5.13 Well behaved I d -V g characteristics for the 200μm × 10μm pMOSFETs with

and without F incorporation Devices with GeO 2 passivation and Forming gas annealing (FGA) show SS about 98mV/dec, while devices with GeO2passivation and both post-gate treatments including CF4 plasma treatment

98

quality

Fig 5.14 I d -V d for 200μm × 10μm pMOSFETs About 18% Enhanced drive current is

obtained after F incorporation Drive current is 37.8 μA/μm at

This is the highest record drive current published for unstrained Ge devices to date

1.2

g t d

V  V V   V

99

Fig 5.15 Fig 5.15 Left: Series resistance Rs for the Al contacted Source/Drain

extracted from the total resistance vs gate length at V g = -2V, -1.5V and -1V for 200μm width devices Right: Junction leakage characteristics

100

Fig 5.16 Basic experimental set-up for charge pumping measurement on HfO 2 /Ge

gate stack

101

Fig 5.17 Illustration of charge pumping effects by varying the Vg on a MOSFET 101

Fig 5.18 Waveform applied at the gate when performing charge pumping 102

Fig 5.19 Different processes occurring during one cycle of the gate pulse (T p = 100

us), using the energy-band diagrams (the Fermi level is used as the zero reference level):

1) steady-state emission of holes to valence band (towards the substrate)

2) nonsteady-state emission of holes to valence band (towards the substrate) 3) trapping of electrons (from source and drain);

4) steady-state emission of electrons to conduction band (towards source and drain)

5) nonsteady-state emission of electrons to conduction band (towards source and drain)

6) trapping of holes (from substrate)

103

Fig 5.20 Rise/fall time dependence of CP current (t r = t f = 50, 100, 200, 500, 900 ns)

for Ge pMOSFETs with or without F incorporation

104

Fig 5.21

Q cp (= I cp /f) as a function of provides the mean Dit for samples without F incorporation is about 3.07 × 10 12 cm -2 eV -1 and for samples with F incorporation is about 9.55×1011 cm-2eV-1, respectively

1/ 2

ln(t t r f) 105

Fig 5.22 (a) Fall time dependence of CP current curves for fixed rise time of 100 ns 106

time dependence of CP current curves for fixed fall time of 100 ns to

measure the Dit distribution in the lower half of the Ge bandgap for samples without F incorporation

Fig 5.23 (a) Fall time dependence of CP current curves for fixed rise time of 100 ns

to measure the Dit distribution in the upper half of the Ge bandgap (b) Rise time dependence of CP current curves for fixed fall time of 100 ns to

measure the Dit distribution in the lower half of the Ge bandgap for samples with F incorporation

107

Fig 5.24 Energy distribution of Dit as determined by rise/fall time dependence of Icp 107

Fig 5.25 F incorporation into high-k/Ge gate stack and various possible passivation

mechanism during subsequent annealing steps: (a) passivation of interface traps at GeO2/Ge interface by forming Ge-F; (b) passivation of interface traps at HfO 2 /GeO 2 interface; (c) passivation of HfO 2 bulk traps by forming Hf-F

108

Fig 6.1 Schematic illustration of n-channel electron mobility degradation by

Coulomb Scattering

114

Fig 6.2 (a) Strong fall-time dependence of charge pumping currents from 50 ns to

450 ns for fixed rise time of 50 ns; (b) Relatively week rise-time dependence

of charge pumping currents from 50 ns to 450 ns for fixed fall-time of 50 ns

116

Fig 6.3 Energy distribution of interface traps in HfO 2 gated Ge MOSFETs as

determined by rise/fall time dependence of charge pumping currents under room temperature

117

Fig 6.4 Energy band diagrams of MOS system with asymmetrical distribution of

interface trap density along the bandgap (a) p-MOS under flat-band; (b) p-MOS near weak inversion; (c) n-MOS under flat-band; (d) n-MOS near strong inversion

117

Fig 6.5 (a) High Frequency Capacitance-Voltage (HFCV) characteristics of

TaN/HfO 2 /Ge p-MOS capacitors with surface nitridation (SN) or silicon passivation (SP); (b) HFCV characteristics of TaN/HfO2/Ge n-MOS capacitors with SN or SP

119

Fig 6.6 Effective carrier mobility of HfO2 Ge MOSFETs with SP together with 120

List of Tables

Table 1.1 Key characteristics of a wide variety of gate dielectrics on Si 8

Table 1.2 Material properties of alternative channel materials 9

Table 4.1 Comparison of Dit , EOT, hysteresis and gate leakage current for Ge

capacitors with different pre-gate or post-gate treatment conditions

79

Table 5.1 Equations used for analyzing CP data with trapezoidal pulse waveform 104

List of Symbols

χ Electron affinity of a semiconductor

ε0 Permittivity of free space

ϕ Electron barrier height

μe Mobility of electron

μeff Effective mobility

μh Mobility of hole

ϭn Capture cross section area of electron

ϭp Capture cross section area of hole

C gb Gate to substrate capacitance per unit area

C gc Gate to channel capacitance per unit area

Cinv Gate to channel capacitance under inversion per unit area

Cmin Minimum capacitance of a MOS capacitor

Dit Density of interface states

Ec Conduction band edge

Eeff Vertical effective electric field in a MOSFET channel

Eem.e Electron emission energy level

Eem.h Hole emission energy level

EF Fermi level of a semiconductor

Eg Energy bandgap of a semiconductor

Ev Valence band edge

f Frequency

Gm Transconductance of a MOSFET

Gp Equivalent parallel conductance of an MOS capacitor

Icp Charge pumping current

Id Current through the drain

Ig Leakage current through the gate electrode

Ioff Drain leakage when the MOSFET is off

I on Channel saturation current when the MOSFET is on

J Current density

Jg Gate leakage current density

k Dielectric constant (relative permittivity)

kGe Dielectric constant of Ge (relative permittivity)

k high-k Dielectric constant of high permittivity dielectric (relative permittivity) Dielectric constant of SiO 2 (relative permittivity)

2

SiO

k

L Gate length of a MOSFET

Nc Effective density of states in the conduction band

ni Intrinsic carrier concentration in a semiconductor

N scatter Interface scattering density

N sub Substrate doping concentration

Nv Effective density of states in the valence band

q Electronic charge

Qb Depletion charge in the bulk per unit area

Qcp Recombined charge per cycle in the charge pumping measurement

Qi Inversion charge in the channel per unit area

R Resistance

Rs Series resistance

t high-k Physical thickness of high permittivity dielectric

tinv Capacitance equivalent oxide thickness in inversion

Tm Melting point

T p Period of the gate pulse

t f Fall time of the gate pulse signal

tox Equivalent oxide thickness

tpoly Equivalent oxide thickness due to poly depletion effect

tqm Equivalent oxide thickness due to quantum mechanical effect of channel

t r Rise time of the gate pulse signal

Va Amplitude of gate pulse

List of Abbreviations

ALD Atomic layer deposition

C-V Capacitance — voltage characteristic

CET Capacitance equivalent oxide thickness

CMOS Complementary metal-oxide-semiconductor device

CP Charge pumping

CVD Chemical vapor depostition

DI Deionized

EOT Equivalent oxide thickness

FGA Forming gas annealing

FUSI Full silicidation

Gm-Vg Transconductance-gate voltage characteristic

GOI Germanium on insulator

HFCV High frequency capacitance-voltage characteristic

Id-Vd Drain current — drain voltage characteristic

Id-Vg Drain current — gate voltage characteristic

IC Integrated circuit

ICP Inductively coupled plasma

IL Interfacial layer

ITRS International Technology Roadmap for Semiconductors

J-V Leakage current-voltage characteristic

Jg-Vg Gate leakage current-gate voltage characteristic

LCR Inductance (L), Capacitance (C), and Resistance (R)

MOCVD Metalorganic chemical vapor deposition

MOS Metal-oxide-semiconductor device, usually the MOS capacitor

nMOS n-type MOS device

nMOSFET n-type channel MOSFET

PDA Post deposition annealing

PMA Post metal annealing

pMOS p-type MOS device

pMOSFET p-type channel MOSFET

PVD Physical vapor deposition

QMCV Quantum mechanical capacitance voltage

UHV Ultra high vacuum

UTB Ultrathin body

UV Ultraviolet

XPS X-ray photoelectron spectroscopy

XTEM Cross-section transmission electron microscopy

Chapter 1 Introduction

1.1 Challenges of MOSFETs scaling and possible solutions

The success of the semiconductor industry relies on the continuous improvement

of integrated circuit (IC) performance by reducing the dimensions of the key component

of these circuits: the metal-oxide-semiconductor field effect transistor (MOSFET) Indeed, the reduction of device dimensions, or scaling, allows the integration of a higher density

of transistors on a chip, enabling higher switching speed and reduced costs The scaling

of MOSFET device was originally predicted by Intel co-founder Gordon E Moore, in

1965 [1] Moore’s law describes a long term trend in the history of computing hardware,

in which the number of transistors that can be placed inexpensively on an integrated circuit has doubled approximately every two years* The key concept of the MOSFET

scaling proposed by Dennard et al in 1974 [2] is that various structure and electrical

parameters of MOSFET (such as gate length, gate width, gate thickness and power supply voltage) should be scaled in concert, which guarantees the reduction in device dimensions without compromising the current-voltage characteristics However, as the MOSFET continues to scale down to tens of nanometers, this conventional device scaling

* Although originally calculated as a doubling every year [1], Moore later refined the period to two years It

is often incorrectly quoted as a doubling of transistors every 18 months, as David House, an Intel Executive,

scheme has confronted the difficulty that the three main indexes associated with MOSFET performance: short-channel effects, on current (Ion) and power consumption have the tradeoff relationships between each other, owing to several physical and essential limitations directly related to the device miniaturization (e.g to maintain the Ion

scaling, SiOxNy with equivalent oxide thickness (EOT) ~ 1 nm has to be used for 45 nm node technology, but this will cause greater power consumption in terms of high gate leakage current) The schematic diagram of this tradeoff relationship is shown in Fig 1.1 [3]

Fig 1.1 Tradeoff factors among short-channel effects, on current (Ion) and power consumption under simple device scaling and possible solutions to mitigate the relationship Critical device or physical parameters to provide the tradeoff, such as

power-supply voltage Vdd and threshold voltage Vth, are shown between the two indexes, and also, the physical mechanisms causing the tradeoffs are shown inside the boxes [3]

Consequently, to continue the MOSFET scaling in the future, novel device

power consumption under healthy device characteristics against these physical limitations are strongly desired to overcome these challenges or to mitigate these stringent constraints in the tradeoff relations A group of these novel device technologies or new materials have been proposed to solve the ultimate scaling issues for future MOSFET, including high-k/metal-gate, high carrier mobility or high carrier velocity channels, ultrathin-body (UTB) structures, multigate structures, and metal source/drain, which are called the technology boosters in the International Technology Roadmap for Semiconductors (ITRS) [4] The basic principle of these technology boosters is to boost

or improve a specific device parameter like the gate leakage current, mobility, channel effects, and so on

short-In this thesis, we focus on the gate stack engineering, because gate stack technology is the key driver for MOSFET scaling The advanced gate stacks must fulfill both requirements of low power consumption and high performance Therefore, the introduction of high-k materials for gate dielectrics and high carrier mobility material for channels is of paramount importance

1.2 High-k gate dielectrics

1.2.1 Limits of SiO 2 scaling

The excellent material and electrical properties of thermal SiO2 allowed the successful scaling of Si-based MOSFETs in the twentieth century Properly working MOSFETs with SiO2 gate layer as thin as 1.5 nm has been reported [5, 6] However, further scaling of SiO2 gate layer thickness is problematic The first problem is the

concern of high leakage current flowing through the metal-oxide-semiconductor (MOS) structure For the ultrathin SiO2 gate layer (< 3 nm), charge carriers can flow through the gate dielectric by the direct tunneling mechanism [7] as illustrated in Fig 1.2 [8] It has been shown that the tunneling probability increases exponentially as the thickness of the SiO2 layer decreases [7, 9] As shown in the Fig 1.2, the leakage current density exceeds

100 A/cm2 at Vox = 1V in a 1 nm thick SiO2 layer (Vox is the potential drop across the dielectric layer) It also can be seen from this figure that the SiO2 layer thickness scaling

is limited by the leakage current specifications from ITRS SiO2 gate dielectric is not suitable for 80 nm technology and below because the EOT requirement of 80 nm node and below is less than 1.4 nm for high performance logic and 1.7 nm for low operating power and the leakage current densities of the SiO2 layers with those thickness will exceed the maximum leakage current specifications

Fig 1.2 (Left) Schematic energy band diagram of an n-Si/SiO2/metal gate structure,

illustrating direct tunneling of electrons from the Si substrate to the gate ϕ is the energy

barrier height at the Si/SiO2 interface, Vox, the potential drop in the SiO2 layer and VG, the applied gate voltage (Right) Simulated tunneling current through a MOS as a function of the potential drop in the gate oxide, Vox, for different SiO2 gate layer thickness Shaded areas represent the maximum leakage current specified by the ITRS for

Another issue arising from SiO2 scaling is boron penetration through the gate dielectric Upon thermal annealing, the boron from heavily doped poly-silicon gate can easily diffuse through the thin SiO2 layer into substrate This will cause unexpected threshold voltage shift and reliability issues [10] Actually, to tackle the gate leakage and boron penetration issues, in most aggressive high performance technologies, SiOxNy is used as gate dielectric SiOxNy has a dielectric constant ~7, which is higher than SiO2, thus a larger physical thickness is allowed to achieve the same EOT In addition, introduction of nitrogen into SiO2 greatly reduces the boron diffusion benefited from the Si-O-N networking bonds formed in SiOxNy [11] In this case, SiOxNy dielectric layer with EOT as thin as 1.1 nm still exhibits acceptable leakage current and amount of boron penetration, extending the scaling limit to 45 nm technology node However, for sub-45

nm technologies, SiOxNy will not be used as gate dielectric since sub-1 nm EOT is necessarily required and SiOxNy can no longer fulfill the gate leakage requirement

1.2.2 Alternative gate dielectrics

The MOS structure actually behaves like parallel plate capacitors The

capacitance density at strong inversion C inv is given by

free space (8.85 × 10-12 Fm-1) and t is the capacitance equivalent oxide thickness (CET) inv

of the gate oxide Higher C inv value enables the MOS structure to have more inversion carriers in the channel at the given gate voltage, and thus increases the drive current of

MOSFETs According to equation (1.1), to increase C inv, we should decrease the t The inv

Si gate with metal gate, which is not the focus of this study is an intrinsic mechanism and cannot be eliminated The most effective way to reduce the is to decease (EOT) For the past several decades, the gate oxide thickness has been scaled down from hundred nm to now about ~ 1 nm As pointed out in section 1.2.1, SiO2 or SiOxNy

has reached to its scaling limits To further decrease the EOT while maintaining the gate leakage current of MOS structure, an insulator with a higher dielectric constant than SiO2

(high-k material) with larger physical thickness should be used The increased physical thickness can also solve the boron penetration problem and improve the gate dielectric reliability As an example, using ZrO2 as gate dielectric (

A lot of research efforts have been made on high-k gate dielectrics for the potential replacement of SiO2 in advance CMOS technologies The material that could be

* The EOT ( ox) of a material is defined as the thickness of the SiO 2 layer that would be required to achieve the same capacitance density as the high-k material in consideration EOT is given by

ox high k SiO high k , where t high k

t

t t k k  and k high k are the physical thickness and relative dielectric

the good candidate needs to satisfy a long list of requirements [12], e.g.:

 The relative dielectric constant of the material should be somewhere between 10 and 30 Dielectrics with higher k value will give rise to fringe fields from the gate to the drain

or source and these fields can degrade short channel performances

 The dielectric material must be an insulator with a band gap greater than 5 eV and the band offsets with silicon must be sufficient Generally, increasing dielectric constant leads to lower conduction and valence band offset for materials in contact with silicon, and there is an inverse relationship between dielectric constant and the band gap To prevent conduction by Schottky emission of electrons or holes into their respective bands, i.e reduce leakage currents, the barrier at each band must be greater than 1 eV

 Low density of intrinsic defects at the Si/dielectric interface and in the bulk of the material, providing high mobility of charge carriers in the channel and sufficient gate dielectric life time

 Good thermal stability in contact with Si, preventing the formation of a thick SiOx

interfacial layer or silicide layers

Table 1.1 lists the key characteristics of a wide variety of potential high-k gate dielectrics together with SiO2 and Si3N4 for comparison It can be seen that HfO2 and LaAlO3 meet most of the criteria listed above, such as k value, band offsets and good thermal stability Indeed, the materials that received by far the most attention as alternative gate dielectrics are Hf-based, either HfO2 or (nitrided) HfSiOx over a broad compositional range The Intel’s 45 nm technology microprocessor has already adopted Hf-based high-k dielectrics as gate insulator Since Hf-based gate dielectrics have already

been demonstrated to be a very important high-k material for Si-based MOS devices In this thesis, we will still focus on Hf-based high-k gate dielectrics for advanced gate stack application with alternative channel material

Table 1.1 Key characteristics of a wide variety of gate dielectrics on Si [13-16]

Dielectric k value Bandgap

(eV)

Conduction band offset (eV)

Valence band offset (eV)

becomes small enough (gate length < 20 nm), ballistic transport will become the dominant carrier transport mechanism The transistor speed is no longer determined by the saturation velocity but the injection velocity at the source region, which is proportional to the mobility Therefore, a MOSFET with high-k gate dielectrics and high mobility channel materials is a good option for future nanoelectronic devices

Table 1.2 Material properties of alternative channel materials [18, 19]

Bandgap, Eg(eV) 0.66 1.12 1.42 0.17 1.35 Breakdown field (MV/cm) 0.1 0.3 0.06 0.001 0.5

Electron affinity, (eV) 4.05 4.0 4.07 4.59 4.38 Hole mobility, μh (cm2/V·s) 1900 450 400 1250 150 Electron mobility, μe (cm2/V·s) 3900 1500 8500 80000 4600 Effective density of states in

unstrained Ge pMOSFETs can provide 3 times hole mobility against the Si universal hole mobility Furthermore, Ge based MOS devices have shown to be compatible with strain technology for both nMOSFET [20] and pMOSFET [3] It is found that the hole mobility enhancement of as high as ten is obtained by combing both Ge channel (GOI with 93%

Ge content) and compressive strain [3] Thus, Ge-channel MOSFETs have been regarded

as one of the most promising channel materials for high speed application

However, the current performance of Ge nMOSFETs is too poor to reach the level for the 22 nm node in the ITRS Therefore, it maybe useful to investigate the feasibility

of III-V MOSFETs because the enhancement factor of the bulk electron mobility against

Si can amount to 3-50 for III-V semiconductors However, it is easier to fabricate MOSFETs in Ge than in III-V materials since the surface passivation of III-V semiconductor is more challenging Ge also has a larger density of states in the conduction band than III-V materials, which is another advantage for achieving a large drive current It is suspected that the low mobility of Ge nMOSFETs is mainly attributed

to the high density of interface traps of the gate stacks [21] So Ge is also a potential nMOSFETs candidate if significant improvement of the interface quality can be achieved

To realize the Ge-based CMOS technologies, there are a few issues to be solved, which are listed below [3]:

(1) High-k gate insulator formation with high quality interface and small EOT

(2) High-quality Ge or GOI channel layer formation

(3) Formation of low resistivity source/drain junctions

(4) Improvement of poor performance of Ge nMOSFETs

(5) Reduction in large off state leakage current (Ioff ) due to smaller bandgap

(6) Appropriate CMOS structures and integration technologies

In this thesis, we will focus on the issue (1) This is because in order to realize the desired high mobility Ge CMOS for sub-22 nm nodes, a viable high-k gate stack on Ge must at least have a low density of interface traps and small EOT

1.4 Current status of Ge channel MOS devices with high-k dielectrics

Due to the water soluble nature of amorphous GeO2, the early works mainly used germanium oxynitride as gate dielectrics Rosenberg and Martin reported this kind of Ge pMOSFETs in 1988 [22] Some subsequent result was reported from the same research group with improved hole mobility of 1050 cm2/V·s [23] Further progress was made by

Ransom et al with both n-channel and p-channel MOSFETs together in 1991 [24] A

gate-self-aligned process flow was used in this paper, which is very close to contemporary device fabrication flow already Both n- and p-channel mobilties obtained from long channel device characteristics were greater than 1000 cm2/V·s, which are much higher than the mobility obtained from Si devices In 2002, effective hole mobility

measured by split C-V method was reported by Shang et al with GeON dielectrics that

was less than 10 nm thick [25] Over 40% hole mobility enhancement is obtained over the Si control and a subthreshold slope less than 100 mV/dec was demonstrated Although these results are encouraging, the equivalent oxide thicknesses are all too large

to meet the ITRS requirement Chui et al studied the scalability of Ge oxynitride

dielectrics for MOS applications [26] They found that GeON was not suitable for highly scaled MOSFET application (EOT < 2 nm) due to the high leakage current density

In order to meet the gate leakage requirement, high-k dielectrics must be

implemented on Ge substrate In 2002, Chui et al demonstrated Ge MOS capacitors with

ZrO2 gate dielectrics for the first time [27] The gate dielectric was formed by UHV

sputtering of ~ 20-30 Å Zr films on the Ge surface followed by in-situ UV ozone oxidation at room temperature EOT as low as 5~8 Å and C-V hysteresis as small as 16

mV were achieved The group further reported the Ge pMOSFETs with such high-k dielectrics with peak hole mobility as high as 313 cm2/V·s [28] However, the gate leakage currents for their samples were quite high and prevented the extraction of other

device characteristics like interface states density Kim et al further investigated the

ZrO2/Ge gate stack, which was formed by atomic layer deposition (ALD) [29] Large

frequency dispersion and hysteresis were presented in the C-V characteristics, which was

ascribed to poor interface quality

Although introduction of high-k gate dielectrics enabled the scaling of EOT, the interface quality is poor when high-k dielectrics directly deposited on the Ge substrate For ZrO2/Ge gate stack, the poor interface quality was believed to originated from either the large areal density of interfacial dislocations due to the relatively large lattice mismatch or because of a very high density of interface states due to intrinsic differences

in bonding coordination across the chemically-abrupt ZrO2/Ge interface [29] For the HfO2/Ge gate stack, it was reported that a significant amount of germanium was found

inside HfO2 film deposited by metalorganic chemical vapor deposition (MOCVD) [30] Similar Ge incorporation was also observed in physical vapor deposition (PVD) HfO2 on

Ge substrate after high-temperature annealing [31] There are several possible mechanisms causing the Ge diffusion into HfO2 Zhang et al believed that the fast

germanium diffusion in dielectrics is probably due to its higher self-diffusivity coefficient

compared to Si [31] Kita et al suggested that the diffusion might be attributed to the

desorption of Ge-riched volatile Hf-Ge-O [32] Whereas some other studies speculated that the formation of volatile GeO at HfO2/Ge interface caused the diffusion [33] The Ge diffusion into high-k dielectrics can cause significant degradation of interface quality and device performance The high-k/Ge MOS characteristics tend to deteriorate when high-k/Ge is treated with thermal processes above 500 °C [34] Such deterioration can be attributed to the fact that Ge-O bonds inevitably exist at the interface between Ge and high-k dielectrics

The poor interface quality of high-k/Ge gate stack becomes the most challenging issue for the Ge MOSFETs Many efforts have been made to improve the interface

quality between high-k and Ge In 2003, Bai et al used an RTP NH3 annealing before HfO2 gate dielectric deposition for Ge MOS capacitors [35] XTEM picture revealed that

an ultra-thin interfacial layer (~8Å) was formed between the HfO2 and Ge, which was believed to be the Ge oxynitride By using the NH3 passivation, electrical characteristics

such as EOT, gate leakage current, hysteresis and Dit were significantly improved The

Ge pMOSFETs with such NH3 treatment and HfO2 gate dielectrics were further made by

Ritenour et al [36] These devices exhibited sub-90 mV/decade substreshold swing and

low gate leakage current An 1.8 X enhancement of hole mobility was achieved

compared to Si control wafers Van Elshocht et al [30] and Lu et al [33] investigated the

Ge diffusion for MOS capacitors with NH3 treatment It was found that there was much less Ge diffusion for samples with NH3 treatment compared to samples without NH3

treatment

The physical characteristics of NH3 annealing was investigated by Wu et al

[37] High resolution XPS study showed that GeOxNy is formed during NH3 annealing The concentrations of oxygen and nitrogen were quantified to be about 0.83:0.17 Although high purity NH3 gas (99.999%) was used in the experiment, the concentration

of oxygen in Ge oxynitride was very high They author suspected that the oxygen was introduced by the NH3 gas source since the main impurity was O2, H2O and H2 The

results also implied that Ge was much easier to be oxidized than nitrified Gusev et al

further studied the microstructure of HfO2 gate dielectric deposited on Ge [38] It was found that the lack of an interlayer enables quisiepitaxial growth of HfO2 on the Ge surface after wet chemical treatment whereas a nitrided interface (grown by thermal oxynitridation in NH3) resulted in an amorphous HfO2 Nitrided interfaces produced much better quality stacks

Besides thermal NH3 annealing, other techniques have also been reported to form

the Ge oxynitride interlayer Chen et al reported an alternative surface nitridation

technique by exposing the Ge substrate to an atomic N beam from a remote RF source at

350oC to 600oC [39] Nuclear reaction analysis of nitride Ge substrate showed a nitrogen

surface density of 2.3 × 1015 cm-2, translating to a substrate coverage of 3 to 4 monolayers

The surface nitridation was found to be effective to reduce EOT and C-V hysteresis for

HfO2 gated MOS capacitors On the other hand, the nitridation also introduced a negative flatband voltage shift ~ 0.7 V, indicating of positive charge introduction or the incorporation of a charge dipole Although improved electrical characteristics were

obtained by surface nitridation, the Dit was still found to be high (~ 6×1012 eV-1cm-2) near the mid-gap using high-frequency/low-frequency method The author also reported Al2O3

gated Ge MOS capacitor with surface nitridation Interestingly, much lower Dit was found compared to HfO2 gated samples, at the expense of increase in EOT and gate leakage current To further minimize the GeOx (x<2) component and increase N

incorporation in the Ge oxynitride interlayer, a wet-NO oxidation was proposed by Xu et

al [40] The mechanisms involved probably lie in the hydrolysable property of GeOx in water-containing atmosphere

Some groups of researchers also tried to fabricate Ge MOS structures with pure germanium nitride (Ge3N4) Because it is believed that the unstable GeOx component can degrade the interface quality and high oxygen concentration may also lead to partially crystallization of Ge oxynitride films [37] However, most of the films obtained through thermal nitridation were Ge oxynitride Oxygen incorporation in these films was unavoidable, attributed to native oxide or residual oxygen in the reactor or oxygen

impurities in the gas sources Maeda et al presented a demonstration of pure nitridation

of clean Ge substrate using a plasma process at low temperatures [41] The surface cleaning of Ge substrate and subsequent nitridation were performed in the same chamber

In situ physical characteristics showed that oxygen was not present in these germanium

nitride films They also managed to fabricated the Ge MOS capacitors with EOT as low

as 1.23 nm These devices exhibited good high-frequency C-V characteristics but the gate

leakage current is substantially high due to the fact that Ge3N4 was not a high-k material The same group of researchers further optimized the process conditions and they found the smoothest interface and surface can be achieved in the Ge3N4 films grown at 100oC [42] It was also pointed out that the top surface of Ge3N4 films was oxidized easily once the Ge3N4 films were exposed to air The similar phenomenon was also reported by

Kutsuki et al [43] They found that humidity in the air accelerated the degradation of

Ge3N4 layers and that under 80% humidity condition, most of the Ge-N bonds converted

to Ge-O bonds Therefore it is essential to take the best care of moisture in the fabrication

of Ge MOS devices with Ge3N4 insulator or passivation layer Maeda et al further

demonstrated HfO2 gated Ge MOS capacitors with pure Ge3N4 interfacial layers [44]

The gate stack exhibited excellent interface quality with minimum Dit ~ 1.8×1011cm-2eV-1

It was noteworthy that Dit increased exponentially as the energy approached to the midgap The thermal stability of the high-k gate stack was also improved with Ge3N4

interfacial layer However, there is no report on transistor performance in that paper

As mentioned earlier, pure Ge3N4 is hard to form on Ge surface due to two reasons The first is that it is difficult to avoid residual oxygen content inside the process chamber or at Ge surface The second is that Ge is much easier to be oxidized than nitrided [37] Thus, some other groups of researchers tried to use metal nitride or metal oxynitride passivation layer to minimize the GeOx (x<2) content at high-k/Ge surface

Gao et al demonstrated a surface passivation using AlNx film for HfO2 gated Ge MOS capacitors [45] The AlNx layer was deposited by reactive sputtering of Al target in N2/Ar ambient For comparison, they also fabricated Ge MOS capacitors with thermal NH3

treatment Interestingly, the author found that the intensity of GeO2 peak increased significantly after HfO2 deposition for sample with surface nitridation, indicating that most of the GeOx component was formed at interface during the HfO2 deposition process Whereas for devices with AlNx passivation, the GeOx component was reduced because AlNx acted as a better oxygen diffusion barrier The electrical characteristics and thermal stability was also improved for device with AlNx passivation Kim et al further made

both n and p channel Ge MOSFETs with AlNx or Hf3N4 passivation layer deposited by

ALD [46] Good C-V characteristics were achieved with EOT as low as 0.8 nm However,

the devices exhibited quite high interface states The mobility for pMOSFETs was only slightly higher than Si hole universal and mobility for nMOSFETs was much lower than

Si electron universal It can be seen that although metal nitride passivation layer acts as a

better oxygen barrier, but the high Dit seems to an intrinsic problem that limits its implementation for MOSFETs fabrication Some recent works presented another TaOxNy

passivation layer, formed either by plasma enhanced ALD [47] or reactive sputtering (with PDA) [48] TaOxNy interlayer was demonstrated to be a good diffusion barrier

between high-k and Ge Electrical characteristics like EOT, hysteresis and Dit were

improved Dit value was lower than MOS capacitors with AlNx or Hf3N4 interlayer reported earlier A peak hole mobility of 225 cm2/V·s was demonstrated for Ge pMOSFETs with TaOxNy interlayer, which was about ~1.7 X enhancement over Si hole universal