Modeling and characterization of high dielectric constant tunnel barriers for nanoelectronic applications

...101 Figure 3-12: Comparison of the simulated lines gate current density with the experimental measurements symbols for a MOS structure area = 10 x 10 μm2 with SiO2 as the gate dielec

MODELING AND CHARACTERIZATION OF HIGH DIELECTRIC CONSTANT TUNNEL BARRIERS FOR FUTURE NONVOLATILE

MEMORY APPLICATIONS

KOH BIH HIAN

(B.Eng (Hons), NUS)

A THESIS SUBMITTED FOR

THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2005

Acknowledgements

Eight years of undergraduate and postgraduate studies in the NUS campus

have left both wonderful memories and as well as those stressful days that I will

remember forever The vibrant campus life and ever-changing landscape that has

captivated me all these years will keep me coming back to my alma mater, no matter

how far I shall venture in the future

Throughout my graduate studies, many individuals and organizations have

contributed generously to my work First of all, I would like to express my heartfelt

thanks and gratitude to my thesis advisor, Assoc Prof Chim Wai Kin No matter how

occupied he was, he always found time to hear my problems and offer his guidance I

would like to thank Assoc Prof Choi Wee Kiong, for giving me unrestricted access

to the equipment in Microelectronics laboratory (MicroE Lab) The work in this thesis

would be impossible without his kind gesture I also wish to acknowledge the research

scholarship and President’s Graduate Fellowship from NUS, and the scholarship from

Chartered Semiconductor Manufacturing Limited

I am grateful to the people who made my stay in the Center for Integrated

Circuit Failure Analysis and Reliability (CICFAR) and MicroE Lab enjoyable

Thanks to staff and ex-staff of CICFAR and MicroE Lab, Mrs Ho, Mr Goh, Mr

Walter Lim, Yong Yu, Xiao Yun and Kar Sin, for the assistance they have given me

To the graduate students from both labs, Yeow Hoe, Merrvyn, Yan Jian, Måns, Kok

Kiong, Kin Mun, Jianxin, Soon Leng, Tsu Huat, Heng Wah, Alfred, Kuan Song, Ric,

Eric, Lee Wee, Li Juan, Vincent, Chen Zhong, David, Chin Heng, Guo Feng, Chen

others for the wonderful company and friendship they had provided Many thanks to

the honours students, Edmund, Kah Meng, Vincent, Gene, Jieyi, Karen, Sing Yang,

Anthony, Kah Cheong, Chi Liang and others that I have worked together before, and

hope that the friendship would last beyond this candidature

I am appreciative of the constant encouragement and advice from all my good

friends, especially, Kaisheng, Jinpiau, Gerald and Jinghui I would like to also thank

my parents, who despite being unhappy with my decision to undertake graduate

studies initially, nonetheless supported me morally and slowly accepted me decision

Hopefully, they would feel proud when seeing the figures and equations in the thesis

Not forgetting my brother, Damien, my sister-in-law, Deedee, and my sister, Kleo,

who constantly asked me when I would be graduating I am also thankful to my

in-laws, Mum, Jason and Dad for giving me their support and encouragement I really

enjoyed all the gourmet treats they had treated me! Thanks to those who I have left

out unintentionally but have helped in any way or contributed to my work

Finally, my deepest gratitude to my wife, Grace, for the patience, care and the

love she has given unconditionally throughout the candidature

2005

“Only those who risk going too far can possibly find out how far one can go.”

-Thomas Stearns Eliot (1888-1965)

CONTENTS

Acknowledgements……… i

Contents……… iii

List of Figures……… vii

List of Tables……… xv

Summary……… xvi

Chapter 1 Introduction 1.1 Background 1

1.2 Motivation 5

1.3 Objectives of Project 9

1.4 Organization of Thesis 10

References 11

Chapter 2 Literature Review 2.1 Review on Quantization and Tunneling Models 14

2.1.1 Carrier Quantization Models 14

2.1.2 Carrier Tunneling Models 19

2.2 Issues in Modeling of Quantization Effects and Tunneling 24

2.2.1 Effective Mass 24

2.2.2 Dispersion Relationship 25

2.2.3 Wave Function Penetration Effects 26

2.2.4 Polysilicon Depletion Effects 27

2.2.5 Image Force 28

2.3 Review on the Modeling of Nanocrystal Based Memory 29

2.4 Charge Retention Issues in Nanocrystal Based Memory 32

2.5 Review on High Dielectric Constant Materials 37

2.5.1 High Dielectric Constant Materials and Crystalline Oxides on silicon 37

2.5.2 Yittrium Oxide – A Potential Candidate for the Implementation of Crystalline Oxide on Silicon 40

2.6 Crested Barrier Structure 46

2.7 Conclusion 49

References 50

Chapter 3 Quantum Mechanical Quantization and Tunneling Model for Metal-Insulator-Semiconductor Devices 3.1 Introduction 63

3.2 Description of the Carrier Quantization Model 63

3.3 Modeling of the Gate Tunneling Current 72

3.3.1 Derivation of Recursive Equations for Gate Tunneling Current Calculation 74

3.3.2 Calculation of the Gate Tunneling Current 82

3.4 Modeling Issues and Assumptions 84

3.4.1 Conservation of Momentum 84

3.4.2 Image Force Effect in the Tunnel Barrier 85

3.4.3 Wave Function Penetration 86

3.4.4 Hole Dispersion Relationship and Effective Masses 91

3.4.5 Polysilicon depletion 96

3.5 Capacitance-Voltage Modeling 97

3.6 Current-Voltage Modeling 100

3.7 Analysis of High-κ MIS Structures Using the Developed Simulation Model .102

3.7.1 Fabrication Details of High-κ MIS Structures 103

3.7.2 Electrical Characterization of High-κ MIS Structures 105

3.7.3 Conduction Mechanism in the Non-ohmic Region of High-κ MIS Structures 108

3.7.4 Fitting of Simulated Capacitance-Voltage and Current-Voltage Characteristics of High-κ MIS Structures 113

3.8 Conclusion 117

References 118

Chapter 4 High-κ Tunnel Barriers – Single Layer and Crested Barrier Stacked

Structure

4.1 Introduction 124

4.2 Review of Tunnel Barriers 125

4.3 Comparison between Single High-κ Layer and Crested Barrier Structure 132

4.4 Selection of Suitable Materials and Devising a Design Rule for Crested Barrier Structures 139

4.5 Experimental Results on Si3N4/Al2O3/Si3N4 Crested Barrier Structure 151

4.6 Epitaxial Y2O3 on Si Substrate for Y2O3/Al2O3/Y2O3 or Y2O3/SiO2/Y2O3 Crested Barrier Structure 161

4.6.1 C-V Hysteresis and Trapped Charge Analysis of Y2O3 163

4.6.2 Flatband Voltage and Oxide Fixed Charge Density Analysis of Y2O3 .168

4.6.3 Amorphous Yttrium Silicate Formation 171

4.6.4 Summary 174

4.7 Conclusion 175

References 176

Chapter 5 Modeling of Charging and Discharge Mechanisms in Germanium Nanocrystal Memory Structures 5.1 Introduction 179

5.2 Modeling of Nanocrystal Memory 180

5.2.1 Modeling of Write Operation 182

5.2.2 Modeling of Erase Operation and Charge Retention 187

5.2.3 Comparison between Present and Existing Model 194

5.3 Conclusion 195

References 196

Chapter 6 Characterization of Discharge Mechanism in Germanium Nanocrystal

Memory Structures

6.1 Introduction 199

6.2 Fabrication of Ge Nanocrystal Memory Structures 201

6.3 Characterization of Ge Nanocrystal Memory Structures 203

6.4 Retention Measurements and Trap Energy Extraction 206

6.4.1 Trap Energy Extraction by Experiment 207

6.4.2 Trap Energy Extraction by Simulation Fitting with Experimental Data .210

6.5 Discussion on the Trap Energy Level 212

6.6 Trap Level Engineering 213

References 217

Chapter 7 Conclusion 7.1 Summary 220

7.2 Recommendations for Further Work 222

Appendix A:

Calculation of D it using Terman’s method A-1

Appendix B:

Derivation of the Physical Thickness of the Stacked Dielectric B-1

Appendix C:

Analyzing Transmission Coefficient of High-κ Materials using Simplified

Wentkel-Kramers-Brillouin (WKB) Approximation C-1

Appendix D:

Relevant Binding Energy for X-ray Photoelectron Spectroscopy D-1

Appendix E:

List of Publications E-1

List of Figures

Figure 2-1: Pictorial illustrations of (a) Fowler-Nordheim (F-N) and (b) direct

tunneling in a nMOS structure V ox is the oxide voltage drop and Φ B is the conduction

band offset at the Si/SiO2 interface 16

Figure 2-2: Electron density in different quantization models z is the vertical

distance from the Si/SiO2 interface and n is the carrier density of the selected

quantized state After Schenk et al [11] 17

Figure 2-3: C–t characteristics at a bias of -10 V after injecting electrons at 20 V for 8

s The inset shows the retention time variation as a function of bias voltage After Kim

Figure 2-6: Inversed discharging time constants divided by squared temperature (T)

Etrap in the plot is equivalent to E t in this work After Baik et al [109] 37

Figure 2-7: (a) Basic building blocks and (b) unit cell of Yttrium Oxide .41

Figure 2-8: Conduction band edge diagrams of various tunnel barriers: (a) a typical

uniform barrier; (b) idealized crested symmetric barrier; (c) idealized asymmetric

barrier; (d) crested, symmetric layered barrier; and (e) asymmetric layered barrier

Dashed lines in panels (a) and (b) show the barrier tilting caused by the applied

voltage V After Likharev [140] 48

Figure 3-1: Schematic diagram showing the propagatory nature of wave functions in

the gate electrode and the quasi-bound wave function when the n-type silicon (Si)

MIS structure is biased into accumulation ……… 64

Figure 3-2: Flow diagram showing the implementation of quantum-mechanical

modeling of a MIS device incorporating the capacitance-voltage calculation

procedure 71

Figure 3-3: Diagram showing the conduction band profile represented by step

potentials of a MIS structure κ j is the wave number at j z j indicates the distance of the

node j from the input electrode κ in and κ out are the wave numbers at the input and

output electrodes, respectively 76

Figure 3-4: Calculated room temperature (T = 300 K) low-frequency C-V curves with

(open circles) and without (solid circles) wave function penetration The substrate

doping concentration is 1x1018 cm-3, oxide thickness is 1 nm and polysilicon doping

concentration is 5x1020 cm-3 88

Figure 3-5: (a) The eigenenergies of the first three subbands, E 10 , E 11 and E 20, with

(open symbols) and without (solid symbols) wave function penetration, as a function

of the surface electric field (b) The average distance of electrons in the subbands, z 10

and z 20 , and the average distance of total electrons, z av, from the surface with (open

symbols) and without (solid symbols) wave function penetration, as a function of the

surface electric field The simulated results were obtained at a temperature T = 300 K.

89

Figure 3-6: Potential profile of a MOS device under (a) low and (b) high negative

gate voltage bias The energy difference of the quantized tunneling hole, E, with

respect to the valence band edge is indicated as ΔE x and ΔE y in (a) and (b)

respectively .92

Figure 3-7: The hole direct tunneling currents in p-MOSFETs, as given by the

source/drain currents in a carrier separation measurement The open circles are the

measured values The solid and dashed lines denote the calculated values by assuming

the hole dispersion in the SiO2 band gap obeys Franz type (m ox = 0.55m o) and

parabolic (m ox = 0.4m o) relationships, respectively mox is the hole effective mass in

conduction defined in Ref [42] After Hou et al [42] .93

Figure 3-8: Plots showing the experimental source/drain (hole) current density (in

open symbol, obtained from Hou et al.[42] ) and the simulated hole current density (in

lines) of pMOS devices with SiO2 as the tunnel barrier The hole current is obtained

from the source/drain current in a carrier separation measurement The doted and bold

lines indicate the simulations performed using one-band and two-band dispersion

relationships, respectively The EOTs used for the simulation are indicated in the plot

and they are the same as the EOTs obtained from C-V fittings in Hou et al [42] 95

Figure 3-9: Plots showing the experimental gate current density (in open symbol,

obtained from Hou et al.[42]) and the simulated electron current density (in lines) of

nMOS devices using SiO2 as insulator The simulations are performed using a

two-band dispersion relationship The EOTs used for the simulation are indicated in

the plot and they are the same as the EOTs obtained from C-V fitting in Hou et al

[42] 96

Figure 3-10: Quantum-mechanical C-V modeling of gate capacitance using the gate

capacitance (solid line) compared to experimental measurements (open circles) on a

(a) pMOSFET: Oxide thickness, T ox = 1.35 nm, Substrate doping (N sub) = 5 x 1017

cm-3 and polysilicon doping (N poly) = 5 x 1019 cm-3 (b) nMOSFET: Oxide thickness,

T ox = 1.35 nm, Substrate doping (N sub) = 8x 1017 cm-3 and polysilicon doping (N poly) =

9 x 1019 cm-3 .100

Figure 3-11: Schematic diagram showing the band structure and band offset values

used for a p+ polySi/SiO2/n-Si MOS structure at flatband .101

Figure 3-12: Comparison of the simulated (lines) gate current density with the

experimental measurements (symbols) for a MOS structure (area = 10 x 10 μm2) with

SiO2 as the gate dielectric for two different oxide thickness (T ox) of 1.57 nm and 2.05

nm The simulated results are performed using the recursive relationship method of

Casperson et al [18] The simulations were performed using an electron effective

mass in the oxide of 0.42m o , N sub = 1 x 1018 cm-3 and N poly = 1 x 1020 cm-3 102

Figure 3-13: TEM micrograph of the (a) Al/ZrO2/ZrSixOy/n-Si MIS device, (b)

Al/SiO2/HfO2/SiO2/n-Si MIS device .105

Figure 3-14: Jg-Vg plots of typical low and high leakage devices from the

Al/ZrO2/ZrSixOy/n-Si MIS structure 106

Figure 3-15: C-V plots of typical low and high leakage devices from the

Al/ZrO2/ZrSixOy/n-Si MIS structure 106

Figure 3-16: D it versus surface band bending (ψs) in a typical (a) high and (b) low

leakage device from the Al/ZrO2/ZrSixOy/n-Si MIS structure .107

Figure 3-17: Diagram showing the three different conduction regions in Ig as a

function of Vg of a typical low leakage sample from the Al/ZrO2/ZrSixOy/n-Si MIS

structure 108

Figure 3-18: Measured Jg-F characteristics for the (a) interfacial layer and (b) bulk

ZrO2 of a typical low leakage Al/ZrO2/n-Si MIS device (area = 1.26 x 10-2 cm2) in the

low gate bias region compared with that calculated based on the Schottky emission

and Frenkel-Poole emission mechanisms The calculated Jg-Vg characteristics were

obtained with T = 295 K, ε = 15 (interfacial layer) or 25 (bulk ZrO2), Φt = 1 eV

(interfacial layer) or 0.9 eV (bulk ZrO2), ΦB = 1.4 eV, A = 120 A cm-2 K-2 (the

free-electron Richardson constant was assumed for both the interfacial layer and bulk

ZrO2), and B = 25.95 A cm-1 V-1 (interfacial layer) or 667 A cm-1 V-1 (bulk ZrO2)

Figure 3-23(a) shows the calculated electric fields in the interfacial layer (dashed line)

and bulk ZrO2 (solid line) corresponding to each gate voltage .112

Figure 3-19: (a) Two-frequency (f = 100 kHz and 400 kHz) corrected

(experimentally measured) C-V curve (in open circles) and Q-M simulated C-V

curves (dashed and solid lines) for the Al/ZrO2/ZrSixOy/n-Si MIS device (gate area =

1.26 x 10-2 cm2) Relative dielectric constant values of 15 and 25 have been used for

the interfacial ZrSixOy (thickness of 1.73 nm from TEM) and bulk ZrO2 (thickness of

13.08 nm from TEM) layers, respectively, in obtaining the simulated C-V curves The

plot with dashed line is the simulated C-V curve for zero oxide fixed charge density

(N f = 0) and zero interface trap density (D it = 0) The plot with solid line is the

simulated C-V curve for D it = 0 and N f = 5.2 x 1012 cm-2, and (b) Conduction band

profile of the Al/ZrO2/ZrSixOy/n-Si MIS device .114

Figure 3-20: (a) Measured and QM simulated C-V curves of the

Al/SiO2/HfO2/SiO2/n-Si MIS device (gate area = 1.26 x 10-2 cm2) Relative dielectric

constant values of 3.9 and 7.117 have been used for the SiO2 (thickness of 1 nm and

2.3 nm from TEM) and bulk HfO2 (thickness of 2.9 nm from TEM) layers,

respectively, in obtaining the simulated C-V curve, and (b) Conduction band profile

of the Al/SiO2/HfO2/SiO2/n-Si MIS device .115

Figure 3-21: Comparison of the simulated (lines) gate current density with the

experimental measurements (symbols) for a MOS structure with 4.3 nm thick SiO2

gate dielectric and MIS devices using multi-layered dielectric stacks as indicated in

the legend This simulation is performed using the recursive method .117

Figure 4-1: Conduction band profile of nanocrystal (nc)/tunnel barrier/Si substrate

using (a) single-layered tunnel barrier at flatband condition, (b) single-layered tunnel

barrier during charging, (c) single-layered tunnel barrier during discharging, (d)

dual-layered tunnel barrier at flatband condition, (e) dual-dual-layered tunnel barrier during

charging, (f) dual-layered tunnel barrier during discharging, (g) crested tunnel barrier

at flatband, (h) crested tunnel barrier during charging and (i) crested tunnel barrier

during discharging The bold arrow shows the effective tunneling distance of the

electron and the dashed line depicts the quantized energy level of the electron The

flatband conduction band is shown in dotted lines……… 128

Figure 4-2: Curves showing gate current density as a function of gate voltage for

SiO2/ZrO2 stacks of 5.6 nm EOT, for different interfacial oxide thicknesses as

indicated After Govoreanu et al [9] .130

Figure 4-3: Tunneling current characteristics versus applied electric field for single

and crested barriers After Baik et al.[8] 131

Figure 4-4: Conduction band profiles of (a) Al/Y2O3/Al2O3/Y2O3/Si, (b)

Al/Y2O3/SiO2/Y2O3/Si and (c) Al/HfO2/Al2O3/HfO2/Si crested barrier structures

Band offsets and permittivities are taken from Ref [1] 133

Figure 4-5: Comparison of the simulated gate current density across the

Y2O3/SiO2/Y2O3 dielectric stack using EOT of 3 nm (square symbol), 4 nm (circle

symbol) and 5 nm (triangle symbol) for the entire Y2O3/SiO2/Y2O3 stack .135

Figure 4-6: Comparison of the simulated gate current density across the

Y2O3/Al2O3/Y2O3 dielectric stack using EOT of 3 nm (square symbol), 4 nm (circle

symbol) and 5 nm (triangle symbol) for the entire Y2O3/Al2O3/Y2O3 stack .135

Figure 4-7: Comparison of the simulated gate current density across the

HfO2/Al2O3/HfO2 dielectric stack using EOT of 3 nm (square symbol), 4 nm (circle

symbol) and 5 nm (triangle symbol) for the entire HfO2/Al2O3/HfO2 stack .136

Figure 4-8: Comparison of the simulated gate current density across single-layered

Al2O3 and SiO2 tunnel barriers using EOT of 3 nm (square symbol) and 5 nm (triangle

symbol) Current density of SiO2 and Al2O3 are represented by closed and opened

T is the WKB transmission coefficient across a

Figure 4-10: Potential profile of Si/Si3N4/Al2O3/Si3N4/Si structure 146

Figure 4-11: Jg versus Vg plots of n-Si/(1-x)(1-y)Si3N4/yAl2O3/x(1-y)Si3N4 structure

using different values of x and y 147

Si/(1-x)(1-y)Si3N4/yAl2O3/x(1-y)Si3N4, (b) Si/(1-x)(1-y)Y2O3/yAl2O3/x(1-y)Y2O3 and

(c) Si/(1-x)(1-y)Gd2O3/yAl2O3/x(1-y)Gd2O3 149

Figure 4-13: Plot showing the hysteresis in the C-V of (a) 5.5 nm Si3N4 and (b) 7 nm

Al2O3 after different annealing durations at 950 oC in pure nitrogen .153

Figure 4-14: Forward and reverse sweep C-V curves of the MIS device using a

crested barrier structure of 2.7 nm Si3N4/7 nm Al2O3/2.7 nm Si3N4 as the tunnel

2/ SiO

hk φφ

barrier layer The bold and the dotted lines indicate the forward and backward voltage

sweeps, respectively 154

Figure 4-15: Plots showing the gate current density of 5.5 nm Si3N4/7 nm

Al2O3/5.5 nm Si3N4 (square symbol), 2.7 nm Si3N4/7 nm Al2O3/2.7 nm Si3N4 (circle

symbol) and 7 nm Al2O3 (triangle symbol) structures, as a function of the Vg-Vfb

during (a) accumulation and (b) inversion 156

Figure 4-16: TEM micrograph showing the 5.5 nm Si3N4/7 nm Al2O3/5.5 nm Si3N4

structure after annealing at 950 oC for 30 min in a nitrogen ambience .158

Figure 4-17: (a) TEM micrograph showing the 5.5 nm Si3N4/7 nm Al2O3/5.5 nm

Si3N4 structure after annealing at 950 oC for 30 min and (b) Nitrogen mapping of the

same 5.5 nm Si3N4/7 nm Al2O3/5.5 nm Si3N4 structure shown in (a) The nitrogen-rich

areas are the brighter regions .160

Figure 4-18: C-V hysteresis versus anneal duration at 600 ºC for 10 nm Y2O3 film on

p-type Si wafer 164

Figure 4-19: C-V hysteresis versus anneal temperature for 10 nm Y2O3 film on

p-type Si wafer 164

Figure 4-20: C-V hysteresis for different wafer surface treatments at anneal

temperature of 400 ºC for different batches of wafers……… 165

Figure 4-21: Schematic of hole injection for unetched and etched wafers for low

temperature anneal 165

Figure 4-22: C-V hysteresis versus anneal temperature for 5 nm Y2O3 films on p-type

Si wafer 166

Figure 4-23: Schematic band diagram representing slow states phenomenon during

(a) negative and (b) positive gate bias……… 167

Figure 4-24: C-V hysteresis at 40-100 kHz for (a) Unetched and (b) H-ter samples

168

Figure 4-25: Flatband voltage versus anneal duration at 600 ºC anneal for 10 nm

thick Y2O3 samples on p-type Si wafer 169

Figure 4-26: Oxide fixed charge density versus anneal temperature for 10 nm thick

Y2O3 samples on p-type Si wafer 170

Figure 4-27: XPS of Si2p for unetched surface samples (5 nm) Y2O3 films at

different anneal temperatures of 400 oC, 600 oC and 800 oC for an anneal duration of

30min 171

Figure 4-28: XPS of Si2p for H-ter surface (5 nm) Y2O3 films at different anneal

temperature for a duration of 30 min .172

Figure 4-29: Transmission electron microscopy micrographs showing 5 nm (as-deposited) (a) Y2O3 on hydrogen-terminated Si substrate that underwent 400 oC anneal for 30 min and (b) Y2O3 on hydrogen-terminated Si substrate that underwent 800 oC for 30 min 173

Figure 5-1: (a) Schematic of nanocrystalline-Ge (nc-Ge) memory device structure (b) Electron tunneling and capture by a trap in nc-Ge during the write process (c) Thermal detrapping of electron and subsequent electron tunneling into the silicon (Si) substrate during the erase process 181

Figure 5-2: Circuit diagram of the nanocrystal memory device .184

Figure 5-3: Conduction band profile of the nanocrystal memory device at thermal equilibrium 185

Figure 5-4: Flow chart for modeling of the charging process .187

Figure 5-5: Plots showing the effects of varying E t and β on the retention time 190

Figure 5-6: Flow chart for the discharge modeling .194

Figure 5-7: Plot showing the experimental retention times measured at different temperatures (Ref [12]) and the fitted simulation results from the present and Min She’s model [12] .195

Figure 6-1: (a) Plan view optical micrograph of the nc-Ge memory transistor Gate length is 10 μm (b) Schematic cross-sectional structure of fabricated device and HRTEM image of the SiO2/nc-Ge/SiO2 transistor memory structure .201

Figure 6-2: Planar TEM image of self assembled nc-Ge embedded in SiO2 The histogram plot shows the size distribution of the nc-Ge 203

Figure 6-3: (a) Typical drain current (IDS) versus gate voltage (VGS) characteristics during forward (1 V - 10 V write) and reverse (10 V – 1 V erase) sweeps in VGS, showing hysteresis, of n-channel nc-Ge memory transistors fabricated in pure N2 No hysteresis was observed in control devices without Ge nanocrystals (b) Hysteresis IDS-VGS characteristics of a similar nc-Ge memory transistor fabricated in forming gas The various hold time in seconds indicate how long the device was held at a particular bias (as shown) at the beginning of the forward and reverse sweeps 205

Figure 6-4: Plot of retention time (t50) versus temperature Solid squares represent the

experimental measurements (taken from the plot in the inset) while the bold line

represents the simulated result using E t = 0.16 eV and β = 13.65 The inset shows the

variation of threshold voltage (Vth) 206

Figure 6-5: (a) Drain current (IDS) transient at a read voltage of 5 V after a write

operation at 15 V for 20 s Symbols represent measured data and the lines are fitted

data from simulation (b) Inverse of the discharging time constant (1/τD) divided by

the square of the temperature (T) plotted against 1/T .210

Figure 6-6: (a) Capacitance versus time (C-t) discharging curves for capacitor

memory structures with nc-Ge and SiO2 tunnel barrier at various temperatures (b)

Temperature dependence of retention time for nc-Ge capacitors with SiO2 or Al2O3

tunnel barrier The error bars represent the spread of the measurements from 5 devices

for each temperature .214

Figure 6-7: Inverse of the discharging time constant (1/τD) divided by the square of

the temperature (T) plotted against 1/T 215

Figure 6-8: Trap energy level required for 10-year charge retention performance

versus the nanocrystal diameter The Ge bandgap widening due to the quantum size

effect is also indicated The conduction and valence band edges at the boundaries of

the widened Ge bandgap are given by E c and E v (E c - E i ) = (E i - E v) = 0.33 eV in bulk

Ge, E i is the midgap energy of Ge .216

Figure A-1: Flow Diagram for the implementation of Terman’s method……… A-3

List of Tables

Table 4-1: Comparison of the |Vprog/Vret| ratio of MIS structures with Al gate and Si

substrate using (a) crested tunnel barriers and (b) single-layered tunnel barriers of

different materials for the insulator layer 137

Table 4-2: Physical thicknesses of the MIS structures with Al gate and Si substrate

using (a) crested tunnel barriers and (b) single-layered tunnel barriers of different

materials for the insulator layer .137

Table 4-3: Conduction band offset and relative permittivity of selected high-κ

dielectric materials The numbers within square barckets indicate the source or

reference Relative transmission coefficient is obtained from Figure 4-9 .140

Table 4-4: Fractional values used for calculating the physical thickness of the LBG

and SBG layers in the crested barrier structure .147

Table 4-5: |Vprog/Vret| ratio obtained from Jg-Vg plots of the different structures in (a)

Figure 4-15(a) assuming J prog /J ret = 10-1 Acm-2/10-7 Acm-2 and (b) Figure 4-15(b)

assuming J prog /J ret = 10-3 Acm-2/10-7 Acm-2 157

Table 5-1: Initial parameters used in the simulation 183

Table 6-1: Parameters and their respective values used in the simulation m o is the

free electron mass .211

Table 7-1: Comparison of the electron affinity of Ge with work functions of selected

metals……… 224

Nonvolatile nanocrystal memory has attracted attention since the availability

of nanofabrication technology However, charge retention times of nanocrystal

memories reported in the literature are still relatively poor This work explores the

possibility of improving the charge retention performance of nanocrystal memory

through the use of high dielectric constant tunnel barriers and trap engineering By

using a crested barrier structure as the tunnel barrier, a high electric field sensitivity

can be achieved which would enable both fast charging and long charge retention

Possible crested barrier structures have been proposed and the design of such

structures is investigated through quantum mechanical modeling Based on the

experimentally observed temperature-dependence in the charge retention times, the

discharging mechanism of our germanium (Ge) nanocrystal memory devices have

been attributed to a trap-related emission process Investigation of trap energy levels

in Ge nanocrystal memory structures and their effect on the device charging and

discharging kinetics are carried out through theoretical modeling and experimental

measurements The trap energy level requirement for achieving a specified long-term

charge retention performance (i.e., 10-year retention time) is obtained from simulation

as a function of the nanocrystal size

Semiconductor memories can be generally classified into two categories The first category consists of volatile memories like static random access memories (SRAM) and dynamic random access memories (DRAM) These volatile memory devices have demonstrated fast speeds during write and read operations of the device and are capable of achieving a high memory density However, data is only stored while the electrical power is sustained The other category consists of non-volatile memories (NVM) like electrically programmable read only memories (EPROM), electrically erasable and programmable read only memories (EEPROM) and Flash

memories The NVM devices are capable of retaining data even without the power supply Amongst the three different NVM devices, Flash memories show the largest growth in recent years, driven by the explosive growth of cellular phones and other types of portable equipment, such as palm tops, mobile personal computers, MP3 players and digital cameras

The history of NVM can be dated back to 1967 when the idea of the “floating gate” structure was introduced by Kahng and Sze [2] The initial design went through

a series of modifications and improvements over the decades Due to its poor charge retention capability, the initial design has been modified by either introducing a charge trapping dielectric layer or a thicker tunnel barrier The device that uses the former and latter methods is known as “charge trapping” and “floating gate” devices, respectively The floating gate (FG) device later evolved to become the mainstream product in the non-volatile memory market because of the following reasons Firstly, its fabrication process is compatible with conventional complementary metal-oxide-semiconductor (CMOS) processing Secondly, the use of a thicker oxide

as the tunnel barrier gives good charge retention performance and read-disturb tolerance On the other hand, the “charge trapping” device or the SONOS (polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon) structure found limited applications, primarily in space and strategic areas, due to the difficulty of fabricating thin layers of silicon oxide and silicon nitride in the 1970’s However, with progress in fabrication technologies, the SONOS structure is a potential candidate to overcome the scaling limitations (especially, the requirement of a thick tunnel barrier) of the FG structure

In addition, the use of a thicker tunnel barrier in a FG device would require a large charging voltage to obtain high charging efficiency A way to avoid a large

charging voltage, and still achieve a high charging efficiency, was the implementation

of avalanche injection [3] of carriers in the drain region, namely Floating gate Avalance injection Metal-Oxide-Semiconductor (FAMOS) and Stacked-gate Avalanche injection MOS (SAMOS) structures Most of the earlier research was mainly on p-channel metal-oxide-semiconductor (p-MOS) and later, n-channel MOS (n-MOS) began to attract more attention due to the higher carrier mobility of electrons compared to holes in the channel Higher carrier mobility would result in faster access time However, avalanche injection in n-MOS can give rise to substantial substrate hole current, which may cause latch-up Therefore channel hot carrier injection and Fowler-Nordheim tunneling are required to achieve high injection efficiency The major improvement for n-MOS came from researchers in Intel in 1980 [4] They proposed the “FLOating gate Tunnel OXide (FLOTOX)” structure which uses electrical signals to perform byte-by-byte erase without having to erase the entire chip during reprogramming Today, the most widespread memory array organization is the Flash memory, in which a byte-selectable write operation is combined with a sector

“flash” erase The Flash memory was first introduced by Fujio Masuoka in 1984 [5]

while working at Toshiba The name Flash was given to represent the fact that the whole memory array could be erased at the same time

The implementation of NVM, in either standalone or embedded memories and

in both code and data storage applications, is mostly by the FG structure Despite the huge commercial success, conventional FG devices do have their limitations The most prominent one is the limited potential for continued scaling of the device structure The term “scaling” refers to the reduction in the device’s dimensions for achieving higher integration density and performance Scaling of devices leads to rapid progress in the development of the metal-oxide-semiconductor field-effect

transistor (MOSFET) technology This enables the silicon (Si) based microelectronics industry to simultaneously meet several technological requirements to fuel market expansion These requirements include performance (speed), low static (off-state) power and a wide range of power supply and output voltages for different applications The guiding principle that governs the scaling trend is Moore’s Law [6] This principle is named after Gordon Moore, co-founder of Intel, who proposed that the number of transistors on a semiconductor chip can be doubled every two years, a prediction that has turned out to be true for the last three decades Even though the scaling trend can be predicted, it will take a strenuous engineering effort to meet the demands of Moore's Law for future developments of the FG structure

The limitation for scaling stems from the extreme requirements place on the

FG tunnel oxide layer During charging and discharging of the memory device, the tunnel oxide has to allow quick and efficient charge transfer to and from the FG The tunnel oxide should preferably be under low electric field condition in order to enable low power operation and to minimize disturbance to neighbouring transistors On the other hand, during the read operation, the tunnel oxide needs to provide good isolation for the FG, so that stored charges in the FG layer are not leaked out, and thus ensuring the integrity of the stored information for at least ten years (typical industry standard,

[7]) In addition, the read voltage must not cause disturbance to the device and its neighbouring devices as well Other factors that have to be taken into consideration are the accumulated effects of repeatedly stressing the tunnel oxide during the write/erase operation, which can lead to bulk and interface oxide trap generation and stress-induced leakage current (SILC) increment

Flash manufacturers have settled on a compromise for tunnel-oxide thickness with values in the range of 9 to 11 nm This thickness has been barely reduced over a

few technology nodes As a consequence, the FG NVM performance, in terms of access time, operating speed and voltages, has only improved marginally with device scaling Area reductions have been achieved mainly through a combined scaling of isolation and interconnect schemes (reducing the metal half-pitch) The area of the storage transistors itself has only been scaled marginally At present, the FG structure

is believed to have problems beyond the 65 nm technology node [7] and this has prompted many incumbent Flash manufacturers to explore alternative storage requirements The major problem lies in the thickness of the tunnel barrier According

to the most authoritative industrial forecast, the International Technology Roadmap for Semiconductors (ITRS), tunnel oxide thickness of 6 to 7 nm (for NAND flash requirements) is required for technology nodes of 65 nm and beyond [7] At this thickness, it is difficult to achieve a 10-year charge retention time specification for nonvolatile memory application

1.2 Motivation

The scaling limitation may seem to signal the end of the road for the Flash memory However, the demand and profit from NVM products are too huge and attractive to be given up Manufacturers like Intel, Motorola, Samsung and others are looking into alternative technologies to circumvent the problem Similarly, research in CMOS devices is facing a similar problem in the scaling of the gate oxide thickness Theoretical and experimental results have predicted that silicon dioxide (SiO2) would fail as an insulator when the thickness is below 7Å (about 2 atomic layers) [8]-[10] For CMOS devices, using high permittivity (high-κ) dielectric materials may solve the problem However, for NVM devices, a single high-κ layer as the tunnel barrier

material with much higher permittivity than SiO2, so that a thicker physical layer can

be used and at the same time, keeping the electrical equivalent oxide thickness (EOT) small and the gate capacitance large The EOT is the equivalent SiO2 thickness when

a high-κ layer is used as a replacement The EOT of a high-κ dielectric layer is the ratio of the permittivity of SiO2 to that of the high-κ layer, multiplied by the physical thickness of the high-κ layer

There are a few major reasons why using a single high-κ dielectric layer for the tunnel barrier in a NVM device does not solve the problem Firstly, when a physically thicker layer is used, the operation voltage increases The increase in power consumption goes against the principle of scaling The basic objectives that scaling of devices aims to achieve, are to have higher integration density, lower power consumption and lower gate delay Secondly, hot carrier injection at the storage node degrades the oxide quality after multiple program/erase operations Even though increasing the physical thickness does improve its resistance to catastrophic degradation, a better solution is to have a layer that has a high immunity to hot carrier and stress-induced leakage current (SILC) degradation In addition, another obstacle

to achieving high integration density is the increase in the parasitic coupling with the reduction in device dimensions [11]

Currently, researchers are looking at the potential of charge trapping devices

to replace the floating gate device From the literature search, two strong candidates have emerged They are the nitride-type memory, based on the SONOS structure as discussed earlier in the section 1.1, and the nanocrystal memory In brief, nanocrystal memory structures uses a charge storage layer consisting of nano-islands of crystalline material (semiconductor or metal), sometimes called “nano-dots” Each nano-dot will typically store a number of carriers and collectively, the charges stored

in the nano-dots control the channel-conductivity of the memory structure Nanocrystal memory offers several advantages over the nitride-type memory device Firstly, due to the distributed nature of nanocrystals where each nanocrystal is isolated from the neighbouring nanocrystals by the surrounding oxide matrix, one weak spot

in the tunnel barrier does not necessarily cause the device to fail For the case of nitride-type memory device, such a weak spot will possibly cause the device to fail as the stored charges are connected to this weak spot through lateral leakage or conduction paths in the nitride layer Due to this reason, the nanocrystal memory can allow further scaling of the tunnel barrier dimension The scaling of the tunnel barrier thickness will in turn lead to a reduction in supply voltage to maintain the electric field magnitude at the injection electrode Secondly, since the charges are localized in each individual nanocrystal, and there is no interacting path in-between the crystals, the nanocrystal memory does not suffer from lateral hoping or percolative leakage as much as in the nitride-type memory device Another attractive feature in nanocrystal memory is the possible use of quantum confinement effects in charge storage Quantum confinement effects in nanocrystals (bandgap widening and energy quantization) can be exploited in small nanocrystal (< 5 nm) devices Another characteristic is the weak dependency on the drain-to-nanocrystal coupling ratio in nanocrystal memory, which means a smaller drain-induced barrier lowering (DIBL) Other attractive advantages include the potential of achieving multibit storage using Coulomb blockade in nanocrystals [12] and the larger carrier capture cross section in nanocrystals, which would give a higher trapping efficiency

Likharev’s group [13]-[15] has been studying the feasibility of using nanocrystal memory structures for future technology nodes They have proposed that,

in order to prevent read disturbance effects on the stored charges during operation, the

ratio of the write/erase voltage to the read voltage should be kept at a value of 2 or below A single silicon dioxide or high-κ tunnel barrier layer may not be capable of fulfilling such a requirement One solution that they proposed is to use a “crested barrier” potential profile The crested barrier structure uses a large bandgap material sandwiched in-between two smaller bandgap materials During the read operation, the charge leakage mechanism is direct tunneling through all the layers of the gate stack structure, which means that the full blocking potential of the entire stack structure is utilized On the other hand, during the write/erase operation, the energy bands are tilted severely and this would greatly reduce the maximum barrier potential seen by the tunneling carriers The conduction mechanism would likely be Fowler-Nordheim tunneling and the effective barrier thickness that the carrier needs to tunnel through is reduced The overall effect is achieving low leakage during the read operation and fast charging at low electric field during write/erase programming

Likharev has demonstrated the performance of crested barrier structures by semiclassical analytical simulation Recently, the Samsung group [16],[17] have presented preliminary experimental results of a silicon nitride/silicon dioxide/silicon nitride (NON) crested barrier structure The ITRS 2003 [7] has also highlighted the possible application of crested barrier structure in future “nano-floating gate memory structures”

In other aspects of nanocrystal memory research, the issue of charge storage is widely debated The initial proposal of charge storage in nanocrystals is by Coulomb blockade in the quantized energy levels within the conduction band of the charge storage layer [18] A possible alternative mechanism was suggested by Tiwari et al.,

who highlighted the possibility of an electron injected to the nanocrystal falling into a trap energy level in the nanocrystal matrix layer [12] Shi et al have demonstrated the

effects of traps on the long term charge retention characteristics of nanocrystal memories [19] By annealing nanocrystal memory structures in a hydrogen ambience,

Shi et al have shown that the memory effect can be reduced and thus concluded that

that hydrogen has possibly passivated the traps responsible for charge trapping

The charge retention time issue is one of the most crucial for nanocrystal memory devices Most reported works [4], [20], [21], [22], [23], [24], [25], [26] have, however, shown relatively short retention times for nanocrystal memory devices It is therefore imperative to investigate methods to achieve a long retention time in order

to realize the goal of replacing the FG structure by nanocrystal memory for NVM devices

1.3 Objectives of Project

The first goal of this project is to study the feasibility of using the crested barrier structure for nanocrystal memory device Since the work for the crested barrier structure is still relatively minimal, suitable materials have not been identified and a study on the requirements on the physical dimensions and properties of the crested barrier gate stack has not been reported This project aims to study these issues primarily through modeling and simulation, which would provide a guide for future experimental work Some preliminary experimental results on the implementation of crested barrier structures are also reported in this work

The first task for the theoretical study on crested barrier structures is to select and implement a suitable energy quantization and carrier tunneling model for the metal-oxide-semiconductor (MOS) structure In order to achieve high accuracy, numerical methods are preferred compared to analytical equations The simulation

high-κ and crested barrier insulator layers Simulations are then performed using the simulation model to devise the design rule for crested barrier structures The materials for crested barriers are identified using the bandgap and band offsets as selection parameters

The second part of the project focuses on the investigation of the charge trapping and discharge mechanisms in nanocrystal memory devices The main objectives are to identify the trapping (charge storage) mechanism in germanium (Ge) nanocrystal memory, investigating the trap energy levels and proposing a suitable trap energy level for a specified long-term retention duration using the developed simulation model The work involves the implementation of a discharge model which incorporates the developed quantum mechanical tunneling model in the first part of the project Experimental measurements are used to calibrate the developed simulation model and the calibrated simulation model is used to predict the required trap energy level needed for long-term retention requirement Trap energy levels are also extracted experimentally from the fabricated Ge nanocrystal memory devices and compared to best fitted (to experimental data) results from the developed simulation model

1.4 Organization of Thesis

This thesis consists of seven chapters Chapter 1 introduces the background of the issues and the motivation that leads to the formation of this project Chapter 2 is a literature review on various topics that are related to this work Chapter 3 covers the description of the self-consistent quantum mechanical model developed for the simulation in this thesis In addition, experimental data from fabricated metal-oxide-semiconductor (MOS) or metal-insulator-semiconductor (MIS) devices

are used to verify the simulated results from the model Chapter 4 presents a short introduction on the retention issue in nanocrystal based memory and also introduces various proposed tunnel barriers that are able to fulfill the long term charge retention requirement for nonvolatile memory devices A single high-κ layer structure is compared with the crested barrier structures to show the superior electric field sensitivity of the latter structure Possible crested barrier structures are proposed and a new design rule to determine the required dimensions of individual layers in the crested barrier structure is devised Lastly, in this chapter, single layer Y2O3 and

Si3N4/Al2O3/Si3N4 crested tunnel barrier are fabricated to investigate the feasibility of both structures as future tunnel barriers in nanocrystal based memory Chapter 5 describes the modeling of the charging and discharging mechanisms in nanocrystal based memory Chapter 6 describes the investigation on the trap energy level that is responsible for charge storage in germanium nanocrystals and discusses the requirement on the trap energy levels for long term charge retention Finally, chapter

7 gives the concluding remarks for the work and proposes some possible follow-up for the project

[4] W.S Johnson, G Perlegos, A Renninger, G Kühn and T Ranganath, “A 16k bit electrically erasable non-volatile memory”, Technical Digest of IEEE International Solid-State Circuits Conference, pp 152, 1980

[5] F Masuoka, M Asano, H Iwahashi, T Komuro and S Tanaka, “A new Flash EEPROM cell using triple polysilicon technology”, International Electron Device Meeting Technical Digest, pp 464, 1984

[6] G.E Moore, “Cramming more components onto integrated circuits”, Electronics, vol 38, no 8, pp 114-117, 1965

[7] The International Technology Roadmap for Semiconductors, San Jose, CA: Semiconductor Industry Association, 2003

[8] S Tang, R.M Wallace, A Seabaugh and D King-Smith, “Evaluating the minimum thickness of gate oxide on silicon using first-principles method”, Applied Surface Science, vol 135, no 1-4, pp 137-142, 1998

[9] J.B Neaton, D.A Muller and N.W Ashcroft, “Electronic properties of the Si/SiO2 interface from first principles”, Physical Review Letters, vol 85, no 6,

pp 1298-1301, 2000

[10] D.A Muller, T Sorsch, A Moccio, F.H Baumann, K Evans-Lutterodt and G Timp, “The electronic structure at the atomic scale of ultrathin gate oxides”, Nature, vol 399, no 6738, pp 758-761, 1999

[11] J.D Lee, S-H Hur and J-D Choi, “Effects of floating-gate interference on NAND flash memory cell operation”, Electron Device Letters, vol 23, no 5, pp 264-266, 2002

[12] S Tiwari, F Rana, H Hanafi, A Hartstein, E.F Crabbe and K Chan, “A silicon nanocrystals based memory”, Applied Physics Letters, vol 68, no 10, pp 1377-

[17] S.J Baik, S Choi, U-In Chung and J.T Moon, “Engineering on tunnel barrier

and dot surface in Si nanocrystal memories ”, Solid-State Electronics, vol 48,

[22] A Fernandes, B De Salvo, T Baron, J.F Damlencourt, A.M Papon, D Lafond,

D Mariolle, B Guillaumot, P Besson, P Masson, G Ghibaudo, G Pananakakis, F Martin and S Haukka, “Memory characteristics of Si quantum dot devices with SiO2/ALD Al2O3 tunneling dielectrics”, International Electron Device Meeting Technical Digest, pp 155-158, 2001

[23] J.A Wahl, H Silva, A Gokirmak, A Kumar, J.J Welser and S Tiwari, “Write, erase and storage times in nanocrystal memories and the role of interface states”, International Electron Device Meeting Technical Digest, pp 375-378, 1999 [24] M Saitoh, E Nagata, and T Hiramoto, “Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates, International Electron Device Meeting Technical Digest, pp 181-184, 2002 [25] Y.C King, “Thin dielectric technology and memory devices”, Ph.D Thesis, University of California, Berkeley, 1999

[26] D.H Chae, D.H Kim, Y Lee, C.H Kwak, J.D Lee and B.G Park,

“Nanocrystal memory cell using high-density Si0.73Ge0.27 quantum dot array”,

Chapter 2

Literature Review

This chapter presents the review on several topics related to this work Firstly,

existing works on the carrier quantization effect and quantum mechanical tunneling

calculations are presented The various issues regarding the quantum mechanical

models would be also addressed Next, the modeling of nanocrystal memory is

discussed and this is followed by a review on the charge retention issue in nanocrystal

memory A review on high dielectric constant materials and crystalline oxides on

silicon, that could be used to implement the crested tunnel dielectric layer in

nanocrystal memory, is also given Lastly, this chapter would describe various novel

tunnel barriers structures that have been proposed to improve the charge retention in

nonvolatile memory

2.1 Review on Quantization and Tunneling Models

2.1.1 Carrier Quantization Models

The interest in the modeling of the quantization and tunneling of carriers at the

silicon (Si) / silicon dioxide (SiO2) interface was spurred by the rapid down-scaling of

device dimensions [1] The demand for higher device packing density has caused a

reduction in device dimensions As dictated by transistor design rules, the gate or

channel length L gate = 45 x T ox [2] in order to avoid short channel effects, where T ox is

the gate oxide thickness This means that any reduction in L gate will be accompanied

by a decrease in T ox The reduction in T ox or the SiO2 barrier thickness has a two-fold

effect Firstly, a decrease in T ox, coupled with the increased doping density in the

substrate, which is also a result of device scaling, will cause larger bending of the

energy bands at the Si/SiO2 interface The consequence of this large band bending is

the creation of a deep potential well that would lead to significant quantization effects

of the carriers at the SiO2/Si interface [3]-[6] Secondly, the thinner SiO2 barrier layer

would be less effective in insulating the substrate from the gate The dominant

leakage mechanism changes from Fowler-Nordheim (F-N) tunneling to direct

tunneling as the SiO2 barrier layer thickness reduces In F-N tunneling, electrons

tunnel through a barrier of triangular shape into the conduction band of the oxide

layer under high oxide fields as shown in Figure 2-1(a), while in direct tunneling,

electrons tunnel through a trapezoidal shaped barrier under low oxide fields Unlike

F-N tunneling, the electron tunneling distance during direct tunneling does not vary

with the oxide field F-N tunneling is a high electric field process (qV ox > Φ B) while

direct tunneling exists in the low electric field regime (Φ B > qV ox ), where V ox is the

oxide voltage drop and Φ B is the conduction band offset at the Si/SiO2 interface

Large direct tunneling current can cause a serious current leakage problem in the

device even during off-state operation It is projected that the operating voltage will

be reduced to 1.0 V or less within this decade, and modern MOSFETs will thus

operate in the direct tunneling regime It has been shown [7],[8] that leakage from

direct tunneling can be significant for ultrathin SiO2 barrier thickness of 3 nm and

below Generally, the direct tunneling current density increases by a decade or 10

times when the SiO2 barrierthickness decreases by 0.25 nm, for oxide thicknesses of

4 nm and below[9]

Figure 2-1: Pictorial illustrations of (a) Fowler-Nordheim (F-N) and (b) direct tunneling in a nMOS

structure V ox is the oxide voltage drop and Φ B is the conduction band offset at the Si/SiO 2 interface

In view of this potential limitation in scaling of the gate oxide thickness,

researchers are interested in looking for solutions to overcome the problem and also

investigating the limits of SiO2 For the modeling of quantized carriers in Si, the

conventional modeling approach based on classical treatment of the carriers is no

longer valid [3]-[6],[10] In the strong inversion state, severe band bending produces a

narrow and deep potential well at the SiO2/Si interface, which quantized the carriers

in the direction normal to the interface The inversion carriers are thus confined within

a two-dimensional (2-D) charge sheet and behave like a two-dimensional electron gas

(2-DEG) Since the carrier quantization is significant, there is a need to provide a

quantum mechanical treatment of the problem Therefore, numerous publications

[3]-[10] in the last three decades have attempted to model the carriers at the Si/SiO2

interface Figure 2-2 shows that the quantum mechanical approaches result in a peak

in the carrier density in the substrate near the SiO2/Si interface while the carrier

density distribution calculated classically failed to predict a peak value at the SiO2/Si

interface

(b) (a)

Figure 2-2: Electron density in different quantization models z is the vertical distance from the Si/SiO2

interface and n is the carrier density of the selected quantized state After Schenk et al [11]

In order to model the quantization effects, there are two general approaches

One approach is to make use of a semiclassical approximation [12]-[14] for the

electron transport This is performed by introducing a “quantum potential” term, Λ, in

the classical formula of the electron density shown in Equation (2-1)

)]

exp[(

T k

E E Nc

where N C is the effective density of states for electrons in the conduction band, k B is

Boltzmann constant, T is temperature, E F is the Fermi level and E C is the bottom of

the conduction band The other approach is by quantum mechanical modeling

[3]-[6],[9],[10],[15]-[18] The more accurate way is to solve the Schrödinger equation

directly by the so-called quantum mechanical numerical approach The Schrödinger

equation is coupled with the Poisson equation and both equations are solved

self-consistently to obtain the eigenenergies and the respective wave functions The

electron density is subsequently calculated as

])(exp[

)()()

,

* 2 ,

E z E z m z T

v j

v v j

where ψj,v and E j,v are the j-th eigenfunction and eigenenergy for valley v obtained by

the self-consistent numerical calculation of Poisson-Schrödinger equations in the

z-direction, that is perpendicular to the SiO2/Si interface m* v is the effective mass at

valley v, E F (z) is the Fermi level at z and ħ is the modified Planck constant However,

the direct numerical method can be computationally intensive Hence, approximate

methods, such as the density gradient method [12]-[14] and van Dort approximation

[19], were proposed as alternatives In the van Dort model, the Λ term is modeled as a

function of the local electric field, F⊥, normal to the semiconductor-insulator interface,

as

3 / 2 3 / 1

)4)(

=

T k d h a

B

Si o fit

εε

(2-3)

where a fit is a fit factor, h(d) is a turn-off function which restricts the model to a

region near the SiO2/Si interface, εo is the permittivity of free space and εSi is the

relative permittivity of Si As can be seen, this model uses Λ to account for the

bandgap widening effect and it only considers the lowest eigenenergy level In the

density gradient method, the Λ term is given as follows:

n m

n n

2 2

* 2

6

])log(2

1log[12

∇

−

=

∇+

where γ is a fit factor, n is the electron density and m *

c is the effective mass of electron in the conduction band.However, these approximations are not as accurate as

the direct quantum mechanical method and therefore the usefulness of these

approximations would depend largely on the degree of accuracy required by the user

Figure 2-2 shows the electron density distribution calculated by the various

approximate quantum mechanical models, as compared to the full quantum

mechanical (Schrödinger) model

2.1.2 Carrier Tunneling Models

Similar to the quantization models discussed above, the direct tunneling

current model can be constructed by semiclassical or quantum mechanical approaches

In semiclassical approach, this is usually performed by weighting the electron

distribution function at the Si/SiO2 interface, deduced from the Boltzmann transport

equation, by the carrier transmission probability In this approach, the 2-D quantum

effects in the channel are neglected and the transmission probability represents the

fraction of free carriers, incident on the SiO2 layer, which crosses the oxide potential

barrier by tunneling The density gradient (DG) model, or the quantum drift-diffusion

(QDD) model, [13],[14] is one of such methods A quantum potential term is

introduced into the classical formulas of electron density and the calculations are

similar to the classical calculations

Generally, there are two different approaches for finding the gate tunneling

current by the quantum mechanical approach The most accurate way is by

considering the finite lifetime of the quasi-bound states in the potential well at the

Si/SiO2 interface It is known that if carriers leak out from the quantum well, the

density-of-states (DOS) broadens in energy and is no longer given by delta functions

at the eigenenergies The broadening due to carriers leaking from the potential well is

represented by the carrier lifetime, τ = /h Γ[20] Γ is the full width at half maximum

(FWHM) of the broadened Lorentzian distribution of the transmission probability or

the DOS Usually, the complex eigenenergy, Γ/2, is extracted by first finding the

transmission probability for a range of expected eigenenergy level(s) The typical

energy interval that is required for calculating the transmission probability is in the

range of 10-12 eV [18] This is a time-consuming and mathematically challenging

procedure which is computationally inefficient in giving fast output There are some

existing and established techniques [21],[22]for calculating the bound states, that can

also be used to determine the quasi-bound states in the leaky potential well However,

due to the difficulty in considering the position dependence of the quasi-bound state

and the inelastic scattering processes, it is not always possible to find the quasi-bound

state by these methods Recently, methods based on the transmission line concept

have been applied to find the lifetime of the quasi-bound states more efficiently

Khondker et al [23] have proposed a quantum mechanical model based on the wave

impedance concept The method was later refined by Haque et al.[24] and it is used in

a few publications [25]-[27] Another technique, known as the quantum transmitting

boundary method (QTBM) that was proposed by Lent and Kirker [28],[29],is largely

used by the University of Texas group [30],[31] Recently, the QTBM method was

also used by Iwata [32],[33]and a minor modification to the boundary condition was

introduced In Mudanai et al [31], it was shown that for a stacked dielectric structure,

the QTBM method tends to produce large oscillations in the gate current density The

authors attributed the large oscillation to the wave reflections which are due to the

large variation of the conduction band in the stacked dielectric [31],[34],[35]

However, it is noted that the oscillations in Ref [31] were much larger than those

reported in most other publications Thus this may not be a true phenomenon due to

the quantum oscillation Modeling of high dielectric constant material (high-κ) gate

stacks were not performed in Refs [32] and [33], and thus no other independent

results were available to verify the validity of the large “quantum oscillations”

Govoreanu et al [36] have derived an analytical method to extract the defining

parameters of the Lorentzian peaks associated with the relative probability of

localizing an electron in the confining potential region at the SiO2/Si interface They

have also proposed an algorithm that is able to estimate the energy levels and

lifetimes of the quasi-bound states, provided the solution of the approximate bound

state system is known

The other way to calculate the gate tunneling current is by finding the

transmission coefficient across the barrier layer where a small proportion of carriers

from the electrodes are able to tunnel through the barrier layer [17],[18] The lifetime

of the quasi-bound state is then approximated as

j

dz z V E m

E T E

0

* ,

)(/

2

)()

methods for calculation of the transmission coefficient The most direct way is to

calculate the ratio of the wave function at the input and output electrodes [37] In a

typical textbook problem, solving the Schrödinger equation for a step barrier is

relatively straight forward However the problem can be complicated for a varying

potential barrier Unfortunately, varying potential profiles do exist in most problems,

for example, in superlattice structures, stacked dielectrics, layers with graded

composition and most importantly, high-κ material that usually has an interfacial layer

when it is deposited on silicon substrate In most calculations for the transmission

coefficient, the varying potential profile is divided into small, and assumingly

constant potential steps, and the output wave function is found by matching the wave

functions at each potential step Throughout the process, a large number of unknown

variables are created and in order to solve these, many boundary conditions are

required, which may not be available In earlier works, most tunneling calculations

are based on Harrison’s independent electron approximation [38]-[40] Harrison

analyzed tunneling through a forbidden region with spatially varying band structure

from an independent-particle point of view He showed that the traditional

Wentzel-Kramers-Brillouin (WKB) approximation can be readily applied to the band

structures which vary slowly over a wavelength of the particle However, at the sharp

boundaries, the wave functions must be matched to conserve the electron flux An

alternative approach using the transmission coefficient across the barrier would give

the same result if wave function matching at the abrupt potential boundaries is

considered when deriving the transmission coefficient However, the earlier

transmission coefficient method used a simple exponential transmission coefficient

with a unity pre-exponential factor, thus neglecting the wave function matching

Recently, there is a rejuvenated interest [41],[42] in the method proposed by Bardeen

[43] in 1961 Bardeen considered tunneling in metal–oxide–metal (MOM) structures

as transferring of a quasi-particle across the oxide in a many-particle system He

showed that, by using the time-dependent perturbation approach, the transition

probability can be derived from the relationship involving the coupling matrix

element Cai et al [41] have combined Harrison’s and Bardeen’s approach to derive

the transmission coefficient with an electric-field dependent pre-exponential factor

Many mathematical methods were used to solve the Schrödinger equation for varying

potential profiles Some examples include the Runge-Kutta method, Numerov

Algorithm and Airy functions [44]-[46] However, these methods are complicated to

implement and in some cases, divergence may occur in the simulations and thus it

may not be suitable for all cases From the literature, the most popular technique used

for calculating the transmission coefficient is by the WKB method [47]-[49] The

method solves the differential (Schrödinger) equation by obtaining the wave functions

in the form of exponentials The method is largely based on the assumption that the

potential varies slowly as compared to the wavelength of the particle It has been

shown successfully [18],[47]-[49] that the WKB method is capable of modeling the

leakage through the SiO2 barrier layer For ultrathin (< 3 nm thick) oxides, Register et

al [47] have proposed a correction factor to the WKB method which successfully

models the direct tunneling in the ultrathin oxide regime However, Yang et al.[49]

have shown that the WKB method may not be suitable for multilayered stack

structures even though some publications have shown reasonably good results for

high-κ stacked dielectrics [50]-[52] Recently, Casperson et al [53] have proposed a

recursive procedure which is able to calculate the output wave function efficiently

However, the derivation of the mathematical relationships was not shown to prove

their validity and the initial parameters used