Application of high k dielectric to non volatile memory devices

In this work, we explored the scaling limit as well as possible materials for the interpoly dielectric IPD layer in future floating gate flash memory devices.. Modeling of Leakage Curren

A STUDY OF NOVEL HIGH-  MATERIALS IN FLASH MEMORY DEVICES AND INTEGRATED

A STUDY OF NOVEL HIGH-  MATERIALS IN FLASH MEMORY DEVICES AND INTEGRATED CIRCUIT METAL-INSULATOR-METAL CAPACITORS

ZHANG LU

(B.Eng., National University of Singapore)

A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINERRING

NATIONAL UNIVERSITY OF SINGAPORE

2010

ACKNOWLEDGMENTS

The four years of graduate study in National University of Singapore has been one of the most important periods and led me to firm direction in my life First and foremost, I would like to express my sincere gratitude to my supervisor advisors, Prof Chan Siu Hung, Daniel and Prof Cho Byung-Jin, for their invaluable guidance, encouragement, and kindness , during my postgraduate study at NUS, not only in terms of technical knowledge, but also personally I will definitely benefit from the experience and knowledge I have gained from them throughout my life

I am especially grateful of Prof Chan’s help, who provides me with the opportunity to join his research group in the first place Secondly for his patience and painstaking efforts devoting in my research as well as his kindness and understanding which accompanied me over the last four years I also greatly appreciate Prof Cho from the bottom of my heart for his knowledge, expertise and foresight in the field of semiconductor technology Without his guidance, it would be impossible for me to have completed this

I would like to extend my gratitude to other teaching staffs in Silicon Nano Device Lab (SNDL): Associate Professor Ganesh Samudar, Dr Lee Sunjoo, Dr Yeo Yee Chia, and Dr Zhu Chunxiang for sharing of their knowledge I also owe the opportunity to collaborate with so many talented graduate students in SNDL at NUS It

is my pleasure to have worked with Mr He Wei, Ms Pu Jing, Mr Hwang Wan Sik, Ms Tan Yan Ny and Mr Kim Sung-Jung, many thanks for their useful suggestions and kind assistance in my research

The technical staffs in SNDL are also gratefully acknowledged: Mr Yong Yu

Fu, Patrick Tang, Mr O Yan Wai Linn, Lau Boon Teck, Dr Han Geng Quan, Mr Sun Zhi Qiang, it was a joyful experience working with all of them

Many of my thanks also go to other students from SNDL, Andy Lim Eu-Jin, Eric Teo, Fu Jia,Gao Fei , Huang Jidong, Jiang Yu, Li Rui, Lin Jianqiang Ma Fa Jun,

Oh Hoon jung, Ren Chi, Rinus Lee, Shen Chen, Tan Kian Ming, Wang Xinpeng, Wang Yinqian, Wu Nan, Yang Jianjun, Yang Weifeng, Yu Xiongfei, Zhang Chunfu, , Zhang Qingchun, and Zhu Ming for their useful discussions and kind assistances during the course of my research, as well as the friendships that will be cherished always

Last but not least, my deepest love and gratitude will go to my family, for their love, patience and support throughout my postgraduate studies

Zhang Lu

January 2010

Rapid scaling of complementary-metal-oxide (CMOS) devices has led to performance challenges posed by the properties of conventional materials To meet this challenge, new high-κ materials have been widely studied for the applications ranging from memory devices to radio frequency (RF)/ mixed-signal (MS) technology for wireless communication In this work, we explored the scaling limit as well as possible materials for the interpoly dielectric (IPD) layer in future floating gate flash memory devices A systematic study of leakage current through the IPD layer was conducted using the MEDICI simulator Various high-κ dielectrics were studied for their feasibility of being used as IPD Simulation result shows that while conventional high- materials like Al2O3 and HfO2 can no longer meet the ITRS scaling requirement, new high-κ dielectrics like La doped Al2O3 and HfO2 show the potential

to be used in the 32 nm technology node Experimental result shows that multi-layer high-κ dielectric structures using Al2O3 and HfO2 based dielectric stack exhibit much improved dielectric thermal stability than that of single layer dielectric Moreover, simulation suggests that, contrary to the conventional high-low-high barrier structure like oxide-nitride-oxide (ONO) IPD, a low-high-low barrier structure like HfO2–Al2O3–HfO2 exhibits lower leakage current at high electrical fields due to the longer effective tunneling distance The advantage of low-high-low barrier structure over high-low-high barrier structure was then confirmed by experiments

gate (FG) was studied with simulation and experiment results reveal that a significant portion of the voltage will drop across the low- interfacial layer, decreasing the effective tunneling distance, and leading to an increased leakage current several orders higher It is suggested that the control of this interfacial layer plays an important role in reducing leakage current By using a low-high-low barrier structure IPD together and suppressing the interfacial layer between high-k and polysilicon floating gate, the leakage current through IPD layer can be significantly reduced Novel high-κ MIM capacitors were also developed for radio frequency and analog/mixed-signal (RF and AMS) IC application The feasibility of a La-doped HfO2 based MIM capacitor was investigated using the dielectric deposited by an atomic layer deposition (ALD) method It is found that for a single layer HfLaO thicker than 20 nm, the crystallization temperature can be as low as 420oC A high dielectric constant of 38 is achieved upon film crystallization, however with a trade off degraded voltage linearity By insertion of a LaAlO3 layer, grain boundary channels extending from the top to the bottom electrode are interrupted, and good interfacial quality near the bottom electrode can be achieved Consequently, HfLaO film crystallization is effectively suppressed and an improved voltage linearity results Both single layer 8% La doped HfO2 capacitors and HfLaO-LaAlO3-HfLaO multilayer stacked MIM capacitors exhibit excellent electrical characteristics such as low leakage current, quadratic linearity, high breakdown field and good device reliability, which make them promising candidates for RF circuit applications

TABLE OF CONTENTS

Acknowledgements i

Abstract iii

Table of Contents v

List of Tables x

List of Figures xi

List of Abbreviation xxi

Chapter 1 Introduction to Floating Gate Flash Memory Devices 1

1.1 Semiconductor Memory Devices 1

1.2 Flash Memory Devices 3

1.3 Operating Principles of Floating Gate Devices 4

1.3.1 Basic Programming Mechanisms 6

1.3.2 Basic Erasing Mechanisms 7

1.3.3 Basic Reading Operation 8

1.4 Challenges in Flash Memory Scaling 9

1.4.1 Scaling Limits for Conventional Interpoly Dielectric Layers 14

1.4.2 Scaling Limits for Conventional Interpoly Dielectric 17

1.4.3 Opportunities Arising from Interpoly Dielectric Scaling 19

1.5 Objectives of the Work 21

1.6 Thesis Outline 21

Reference 23

Chapter 2 MIM Capacitors for Radio Frequency and Analog/Mixed-Signal Technologies 26

2.1 RF and Mixed-Signal Technologies 26

2.2 Metal-Insulator-Metal Capacitor for RF/AMS Application 26

2.3 Parameters of RF/AMS Capacitors 28

2.3.1 Dielectric Constant and Capacitance Density 28

2.3.2 Temperature Coefficient of Capacitance (TCC) 29

2.3.3 Voltage Linearity 30

2.3.4 Leakage Current 31

2.3.5 Dissipation Factor and Loss Tangent 32

2.3.6 Compatibility with BEOL Integration 33

2.3.7 Technology Trends and Challenges 33

References 35

Chapter 3 Modeling of Leakage Current in Interpoly Dielectric Layers in Floating Gate Flash Memories 39

3.1 Introduction 39

3.2 Simulation Methodology 40

3.3 Results and Discussion 48

3.3.1 Single Layer IPD with Different Barrier Height 48

3.3.2 Multi Layer IPD Structure 51

3.3.3 Effect of an Interfacial Layer between the Polysilicon Gate and Dielectric 59

3.4 Summary 63

Reference 65

Chapter 4 High-κ Dielectrics for Interpoly-Dielectric Layers 67

4.1 Introduction 67

4.2 Device Fabrication 68

4.3 Evaluation of Single Layer High-κ Dielectric 69

4.3.1 Evaluation of Hafnium oxide (HfO2) 70

4.3.2 Evaluation of Tb-doped Hafnium oxide 71

4.3.3 Evaluation of Lanthanum-doped Hafnium Oxide Films 76

4.3.4 Evaluation of Yttrium Oxide (Y2O3) Dielectric Films 83

4.4 Multi-Layer High-κ Dielectric Evaluation 85

4 5 Suppression of Interfacial Layer 91

4.5.1 Surface Nitridation of Si 92

4.5.2 Poly-SiGe Floating Gate 93

4.4 Summary 96

Chapter 5 Atomic Layer Deposited HfLaO and LaAlO3 Multilayered

Dielectrics for High Performance MIM Capacitors 101

5.1 Introduction 101

5.2 Device Fabrication 103

5.3 Single Layer La-Doped HfO2 MIM Capacitors 105

5.3.1 Structural Analysis 105

5.3.2 Leakage Currents Characteristics 112

5.3.3 Capacitance Density and Voltage Linearity 115

5.4 HfLaO-LaAlO3-HfLaO Multi-layer MIM Capacitor 120

5.4.1 Motivation 120

5.4.2 Experiment 121

5.4.3 Results and Discussion 122

5.5 Summary 130

Reference 131

Chapter 6 Conclusions 134

6.1 Summary 134

6.1.1 Understanding the Interpoly Dielectric Layer 134

6.1.2 Lanthanum-doped Hafnium Oxide for RF/MS MIM Capacitors 136

6.2 Suggestions for Future Research 138

Reference 139

Appendix

List of Publications 140

LIST OF TABLES

Table 1.1 Volatile and non-volatile memory types and their main

features

2

Table 3.1 Electrical characteristics of different dielectric materials 48

Table 5.1 Comparison of various high capacitance density MIM

capacitors using high-κ dielectrics

120

List of Figures

Fig 1.1 Circuit schematics and top-down memory cell layouts for

conventional NOR and NAND flash memory (BL: bit-line; GL: ground select-line; SL: select-line: WL: word-line.)

4

Fig 1.2 A cross section of a floating gate type flash memory device 5

Fig 1.3(a) Schematic diagram of programming using the Fowler-Nordheim

tunneling mechanism

6

Fig 1.3(b) Energy band diagram of a floating gate memory during

programming by the Fowler-Nordheim tunneling mechanism

7

Fig 1.4(a) Schematic diagram of erasing using the Fowler-Nordheim

tunneling mechanism

8

Fig 1.4(b) Energy band diagram of a floating gate memory during erasing by

the Fowler-Nordheim tunneling mechanism

8

Fig 1.5 Current-Voltage transfer characteristic of a floating gate device

when there are no electrons stored (“1”) and when electrons are stored (“0”) in the floating gate

9

Fig 1.6 The aggressive scaling trend of NAND flash memory device

technology followed by major manufacturers [10]

11

Fig 1.7 The number of electrons stored in NAND type flash memory

devices under different design rules for a shift in Vth of 4V The loss of stored electron will result a drop in Vth value and subsequent failure in reading operation [7]

11

Fig 1.8 Floating gate interference with Si3N4 and SiO2 spacers under

different design rules [7]

14

Fig 1.9 Flash memory interpoly dielectric thickness scaling from 65 to 45

nm technology node (ITRS 2005) [13]

16

Fig 1.10 ITRS 2005 prediction on the required electrical thickness of IPD

and tunneling oxide for NAND-Flash memory [13]

17

Fig 1.11 Dependence of charge loss on top oxide thickness when the

bottom oxide thickness is 13~15 nm [15]

18

Fig 1.12 Current density at low electric field (3 MV/cm) as a function of

EOT for various IPDs [18]

20

Fig 2.1 Prediction on capacitance density requirements of MIM

capacitors to 2022 according to ITRS 2007

29

Fig 3.1 Device structure of a floating gate type flash memory device 41

Fig 3.2 Energy band diagram of three main types of carrier injection

mechanism through an insulator energy barrier

42

Fig 3.3 Band diagram for direct tunneling of electrons in the conduction

band (CBET) and valence band (VBET) from region 1 to region

as well as the tunneling of holes from the valence band (VBHT)

in regions 3 to region 1

43

Fig 3.4 Example of tunneling through an oxide-nitride-oxide dielectric

stack The potential barrier along the tunneling path is shown on the right

46

Fig 3.5 Calculated conduction band, valence band offsets and bandgap of

various oxides on Si [11]

47

Fig 3.6 Band diagram of IPD layer with TaN and poly electrode 47

Fig 3.7 Simulated IV grape for SiO2 , EOT=6.5nm TaN is used as gate

electrode

50

Fig 3.8 Minimum  value and barrier height required for meeting

specifications when electrons tunnel from the polysilicon Materials inside hatched areas show feasibility of meeting the specification for 45 nm

50

Fig 3.9 A schematic diagram of the device structure of multilayer MIM

capacitor used in the simulation study Total physical thickness is fixed at 19 nm while the physical thickness ratio between blocking oxide layer and middle layer is varied

52

Fig 3.10 Simulated tunneling current plotted against EOT for

SiO2-HfO2-SiO2 and Al2O3-HfO2-Al2O3 multilayer structures The total IPD physical thickness is fixed at 19 nm but the middle layer thickness is varied as in (x- (19-x) -x) A positive bias is applied on the TaN CG, and simulated leakage current is obtained from electrons injected from polysilicon FG

52

Fig 3.11 Band diagrams illustration of the VARIOT (variable oxide

thickness) and reverse-VARIOT effect At similar voltage drops over the two stacks, the tunneling barrier is much larger in the reverse-VARIOT case, as compare to the VARIOT case

54

Fig 3.12 Simulated tunneling current for HfO2-Al2O3-HfO2 when the IPD

total physical thickness is fixed at 19 nm, and the middle layer thickness ratio is varied A positive bias is applied on the TaN

CG, and tunneling electrons are injected from the polysilicon FG For such multilayer IPD structures, leakage current reaches a

55

minimum value at a certain thickness combination

Fig 3.13 Simulation results for the tunneling current in different multilayer

IPDs at a fixed EOT of 6.5nm The thickness of the middle layer EOT as a percentage of the total EOT is varied A positive bias is applied on TaN CG and tunneling electrons are injected from the polysilicon FG From the simulation results, it is observed that HfO2-Al2O3-HfO2 low-high-low barrier structure shows a minimum leakage current at a certain thickness combination

56

Fig 3.14 Simulated band diagram for (a) HfO2 – Al2O3 – HfO2 structure (b)

Al2O3 – HfO2 – Al2O3 structure, both under +10 bias The High-Low-High barrier structure has a shorter tunneling distance (4.425 nm) than the Low-High-Low barrier structure (7.025 nm), and this shorter tunneling distance results in greater leakage current

58

Fig 3.15 Tunneling current simulation results for HfO2-Al2O3-HfO2 and

HfLaO-Al2O3-HfLaO multilayer IPD at a fixed EOT of 6.5nm The middle layer EOT ratio is varied A positive bias is applied on TaN CG and tunneling electrons are injected from polysilicon FG

59

Fig 3.16 Simulation results show that adding a thin SiO2 interfacial layer

increases the tunneling current significantly at high voltage even though the total EOT is higher By comparing simulation results with experimental data, it is suggested that the interfacial layer between polysilicon and high-κ dielectric is greater than 0.5 nm

61

Fig 3.17(a) Band diagram of HfO2-Al2O3-HfO2 stack under 10 V bias on

poly-Si

61

Fig 3.17(b) Band diagram of HfO2-Al2O3-HfO2 stack with 1nm SiO2

interfacial layer under 10 V bias on poly-Si The electron effective tunneling distance (1.61 nm+1.4 nm) is reduced significantly

62

Fig 3.18 Band diagram of MOSCAP with 2 nm EOT HfO2 gate dielectric

(physical thickness 10 8 nm) under 2 V bias (left), MOSCAP

63

with 2nm EOT HfO2 gate dielectric and 1nm SiO2 interface under

2 V bias (right)

Fig 4.1 Process flowchart for IPD MIM capacitor fabrication. 69

Fig 4.2 Thermal stability of a single layer HfO2 at different PDA

temperatures were studied TaN was used for both FG and CG Leakage current increases dramatically after a high temperature process at 900oC The increase of leakage current is attributed to poly-crystallization of HfO2 as well as film stress build-up

71

Fig 4.3(a) Leakage current densities of MIM capacitors using HfO2 and

HfxTbyO with different Tb concentrations after 420oC forming gas anneal The lowest leakage current is found in 4% Tb-doped sample

73

Fig 4.3(b) Normalized Leakage current vs Bias/EOT for HfO2 and HfxTbyO

with different Tb concentrations after 420oC forming gas anneal

74

Fig 4.4 Thermal stability of a single layer 4% Tb doped HfO2 at different

PDA temperatures were studied TaN was used for both FG and

CG Leakage current starts to increase after 950oC (a) Leakage current vs applied voltage on gate; (b) Normalized leakage current vs Bias/EOT

75

Fig 4.5 Leakage current densities plotted against normalized bias, for

pure HfO2 and 4% Tb doped HfO2 after 900oC and 950oC annealing

76

Fig 4.6 XRD spectra of HfO2 and HfLaO films with 15% and 50% La

after 600oC and 900oC annealing for 30 s in N2 The La incorporated in HfO2 films can increase the crystallization temperature up to 900oC

79

Fig 4.7 XPS spectra for Si 2p core level taken from HfO2, HfLaO with 80

of the peak intensity for silicate-like interfacial layer and a shift toward high binding energy are observed after incorporating La into HfO2

Fig 4.8 TEM picture of (a) 15% La incorporated HfO2 after 900oC

annealing; (b) 50% La incorporated HfO2 after 900oC annealing

81

Fig 4.9 Leakage current comparison between single layer LaAlO3 and

HfLaO after 900C annealing.direction

Fig 4.12 HRTEM micrograph showing a 37 nm Y2O3 layer grown on Si A

rather thick (20 Ǻ) amorphous interfacial layer is observed Micrograph is reproduced from [15]

84

Fig 4.13 Leakage current comparison between single layer Al2O3, HfO2

and multilayer HfO2 - Al2O3 - HfO2 structure after 900C annealing HfO2 - Al2O3 - HfO2 multilayer structure has much more improved electrical thermal stability

86

Fig 4.14 Leakage current of a HfO2-Al2O3-HfO2 multilayer IPD at

different PDA temperatures It is shown that the leakage current of multi-layer high-κ stack with a similar total EOT does not increase much, even after 950°C annealing, confirming the improved electrical thermal stability

86

Fig 4.15 A comparison of experimental leakage currents in HfO2 – Al2O3 –

HfO2 and Al2O3 – HfO2– Al2O3 structure HfO2 – Al2O3 – HfO2

low-high-low barrier structure shows a lower leakage current than

88

Al2O3 – HfO2– Al2O3 high-low-high structure

Fig 4.16 Leakage current comparison of HfO2 – Al2O3 – HfO2 multilayer

stacks with different Al2O3 middle layer EOT percentage It is shown that samples with Al2O3 thickness closes to 80% shows lower leakage current than samples with Al2O3 thickness of 50% Inset is the simulation obtained from chapter 3 suggesting the leakage current is dependent on middle layer EOT percentage

89

Fig 4.17 Leakage current comparison for two different middle layers of

Al2O3 and HfLaO A positive bias is applied on TaN CG By the replacement of middle layer with HfLaO, IPD layer electrical thermal stability is improved, resulting in reduction of the leakage current

90

Fig 4.18 Leakage current comparison for different blocking layers of HfO2,

HfAlO and 4% Tb-doped HfO2 While HfAlO does not show improve leakage current, 4% Tb-doped HfO2 reduces leakage current effectively

91

Fig 4.19 Leakage current comparison for different polysilicon FG surface

treatment techniques Heavy nitridation of polysilicon helps to reduce the leakage current by reduction of IL growth HfO2 –

Al2O3 – HfO2 IPD stack was used

93

Fig 4.20 Use of SiGe floating gate is effective in suppressing interfacial

layer growth, leading to lower leakage current HfO2 – Al2O3 – HfO2 IPD stacks are used

95

Fig 4.21 A comparison of leakage current of HfO2 – Al2O3 – HfO2 IPD

stack structures on three different floating gate materials

95

Fig 5.1 The relationship between energy bandgap and the permittivity of

high-κ materials The c(Cubic)-HfO2 phase shows higher permittivity than that of m(monoclinic)-HfO2

103

Fig 5.2 Process flowchart for Hf x La y MIM capacitor fabrication. 104

Fig 5.3 TEM picture showing the 21.8nm and 44nm thick HfLaO films 105

Fig 5.4 XPS analysis of HfO2 incorporated with different La

concentration The La incorporation percentage increases, peak shifts to lower binding energy of La

107

Fig 5.5 Crystallization temperature for 10nm thick HfLaO films with

different concentrations of lanthanum (La) doping

107

Fig 5.6 Change in the dielectric constant of Hf1-xLaxO with different

compositions before and after crystallization Among various La doping concentrations, HfO2 films doped with 8% La shows the highest dielectric constant upon crystallization

108

Fig 5.7 Leakage current characteristic for amorphous and crystallized

Hf1-xLaxO 8% La doped HfO2 shows a lower leakage current than other doping concentrations

109

Fig 5.8 XRD analysis of 20 nm 8% La doped HfO2 with various

annealing conditions Peaks from the 500oC annealed sample correspond to a cubic crystalline phase

110

Fig 5.9 TEM image of 22 nm 8% La doped HfO2 It is a very clear that

the film has crystallized after annealing at 500oC

110

Fig 5.10 Dielectric constant change of single layer HfLaO films of

different thicknesses under different annealing conditions

111

Fig 5.11(a) Leakage current versus DC bias for HfLaO MIM capacitors with

different film thicknesses before crystallization

113

Fig 5.11(b) Leakage current versus DC bias for HfLaO MIM capacitors with

different film thicknesses after crystallization

113

Fig 5.12(a) Leakage current density (at -3.3 V) against capacitance density of

both amorphous and crystallized HfLaO capacitors

114

Fig 5.12(b) Leakage current density (at -5.6 V) plotted against capacitance

density of both amorphous and crystallized HfLaO capacitors

114

Fig 5.13 DC bias dependence of normalized capacitance (ΔC/C0) at 100

kHz and 1 MHz for MIM capacitors with different HfLaO thicknesses (amorphous)

116

Fig 5.14 Quadratic voltage linearity versus different capacitance densities

of single layer HfLaO capacitors

116

Fig 5.15 Lifetime projection 8% La-doped HfO2 MIM capacitors with

various thicknesses using 50% failure time as the criteria

118

Fig 5.16 Electric-field-strength (E) dependence of median time-to-failure

of HfLaO capacitors with different film thicknesses

119

Fig 5.17 Projection of operation voltage for 10-year life time for different

HfLaO capacitance densities

119

Fig 5.18 Schematic drawing of HfLaO single layer and

HfLaO/LaAlO3/HfLaO multi-layer MIM capacitor

122

Fig 5.19 Equivalent dielectric constant of HfLaO/LaAlO3/HfLaO (HLH)

multi-layer dielectrics under different annealing temperatures HfLaO thickness on the two sides is fixed at 10 nm while the middle LaAlO3 layer thickness is varied Inset is the XRD comparison between HfLaO single layer and HLH multi-layer

123

after 420ºC anneal for LaAlO3 thickness of 4 nm

Fig 5.20 Leakage current density (at -3.3 V) against capacitance density of

HfLaO and HfLaO/LaAlO3/HfLaO MIM capacitors Bench-marked results were plotted together for comparison purpose

125

Fig 5.21 Leakage current density (at -5.6 V) against capacitance density of

HfLaO and HfLaO/LaAlO3/HfLaO MIM capacitors

125

Fig 5.22 Quadratic voltage coefficient () of MIM capacitors versus

capacitance density of HfLaO and HfLaO/LaAlO3/HfLaO capacitors Bench-marked results from the literature were also plotted

127

Fig 5.23 Dependence of the Capacitance on Voltage Bias for HfLaO and

HLH MIM capacitors with similar capacitance density

127

Fig 5.24 Life time projection of HfLaO single layer (7.5 fF/µm2) and

HfLaO/LaAlO3/HfLaO multi-layer (7.4 fF/µm2) MIM capacitors measured at room temperature

129

Fig 5.25 Comparison of reliability performance of HfLaO single layer and

HfLaO/LaAlO3/HfLaO multi-layer MIM capacitors

129

LIST OF ABBREVIATIONS

AiryTMT Airy transmission matrix technique

ALD atomic-layer deposition

AMS analog /mixed signal

BEOL back-end of line

CHE channel hot-electron injection

CMOS complementary metal oxide semiconductor

C-V capacitance-voltage

CVD chemical vapor deposition

CVS constant voltage stress

DHF diluted hydrofluoric (acid)

DRAM dynamic random access memory

EEPROM electrically erasable programmable read-only memory

EOT equivalent oxide thickness

EPROM erasable programmable read-only memory

IPCVD low pressure chemical vapor deposition

IPD interpoly dielectric

ITRS international technology roadmap for semiconductors

MOSFET metal-oxide-semiconductor field-effect transistor

PDA post deposition annealing

SLC single level cell

SRAM static random access memory

TC tunneling coefficient

TCC thermal coefficient of capacitance

TEM transmission electron microscopy

VARIOT variable oxide thickness

VBET valence band electron tunnelling

VBHT valence band hole tunnelling

VCC voltage coefficient of capacitance

VLSI very large scale integration

WF work function

WKB Wentzel–Kramers–Brillouin

XPS x-ray photoelectron spectroscopy

XRD x-ray diffraction

Chapter 1

Introduction to Floating Gate Flash Memory Devices

1.1 Semiconductor Memory Devices

Semiconductor memories devices have been around for many decades Their areal density has increased almost four times every three years and they are now used

in many new applications, where both high data retrieval speed and lower power are demanded There are two main categories of complementary metal-oxide-semiconductor (CMOS) memories devices:

1) Volatile memories, including static random access memory (SRAM) or dynamic random access memory (DRAM) Although exhibiting fast writing and reading speed, these devices suffer the problem of losing stored information once the power supply is switched off [1]

2) Non-volatile memories, including erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memories These devices will keep stored information even when the power supply is switched off Table 1.1 lists some of the volatile and non-volatile memory types and their related features

Table 1.1 Volatile and non-volatile memory types and their main features

Electrically Erasable Programmable

Read-only Memory (EEPROM)

Electrically byte-erasable; lower reliability, higher cost, lowest density

Electrically Programmable Read-only

Memory (EPROM)

High-density memory; must be exposed

to ultraviolet light for erasure

Flash Memory Low-cost, high-density, high-speed

architecture; low power; high reliability

The ideal memory subsystem optimizes areal density, preserves critical material in a non-volatile condition, is easy to program and reprogram, can be read fast, and is cost-effective for the application Some memory technologies meet one or more of these requirements very well, but offsetting limitations can prevent the product from becoming a genuine solution, especially in newer applications Thanks

to the characteristics of non-volatile memory, it offers a wide range of applications

1.2 Flash Memory Devices

Among various non-volatile memory devices, floating gate (FG) type flash memory devices are the core of every modern non-volatile semiconductor memory device It has become the preferred device because its ease of erasing stored charge enables a memory device that is both non-volatile and reprogrammable Early floating gate devices had to be erased with a few minutes of ultraviolet radiation which imparts enough energy for stored electrons to surmount the insulating barrier In a modern floating gate memory, whole blocks of devices are erased electrically in less than a second, giving rise to the term flash memory [2, 3] This change greatly simplified memory packaging and simultaneously opened up vast new sets of applications [2, 4] Today, more than 90% of non-volatile memory production is based on the floating gate concept [5]

Meanwhile, specific applications have stimulated to the development of a wide variety of flash memory devices, and they all show different characteristics according to the structure of the selected cell and the complexity of the array organization There are two major kinds of flash memories, NOR and NAND, as depicted in Fig.1.1 [3] In NOR memory, each cell in a memory array is directly connected to the word-lines and bit-lines of the memory array, while NAND memory devices are arranged in series within small blocks Thus, while NAND flash can inherently be packed more densely than NOR flash, NOR flash offers significantly faster random access

Fig.1.1 Circuit schematics and top-down memory cell layouts for conventional NOR and NAND flash memory (BL: bit-line; GL: ground select-line; SL: select-line: WL: word-line.)

1.3 Operating Principles of Floating Gate Devices

A schematic cross section of a generic floating gate device is shown in Fig.1.2 The upper gate is the control gate (CG) and the lower gate, a conductive layer (doped polysilicon) completely isolated within the gate dielectric, is the floating gate (FG) The FG acts as a potential well, if a charge is forced into the well, it cannot move from there without an externally applied force; in other words, the FG stores charge The tunnel oxide between the floating gate and the substrate is an oxide with thickness in the range of 9-10 nm through which electrons can tunnel via the

dielectric layer that separates the FG from the CG is called interpoly dielectric (IPD) layer

Fig.1.2 A cross section of a floating gate type flash memory device

Basically, the floating gate memory device is an MOS transistor with a threshold voltage that is given by

VT=K - QFG/CCG Where K is a constant that depends on the gate and substrate material, doping, and gate oxide thickness, QFG is the charge in the floating gate, and CCG is the capacitance between CG and FG [6]

The threshold voltage can be altered by changing the amount of charge present in the floating gate Thus, by storing/removing charge in/from the floating gate, the threshold voltage can be changed repetitively from a high to a low state, in the other words, “programmed” and “erased” states, respectively

1.3.1 Basic Programming Mechanisms

While NOR flash memory is programmed using channel hot-electron injection (CHE), Fowler-Nordheim (FN) tunneling is used to program NAND flash memory through the channel area A schematic diagram of programming using the

FN mechanism is illustrated in Fig 1.3 For programming purposes, a large voltage

VCG is applied at the control gate (producing fields in the range of 8-10 MV/cm), forcing a large electron tunneling current through the tunnel oxide without destroying its dielectric properties Electrons are then stored in floating gate, this stage is defined

as “0” An energy band diagram during programing process is drawn in Fig 1.3(b)

Fig.1.3(a) Schematic diagram of programming using the Fowler-Nordheim tunneling mechanism

Fig.1.3(b) Energy band diagram of a floating gate memory during programming by

the Fowler-Nordheim tunneling mechanism

1.3.2 Basic Erasing Mechanisms

The electrons that are injected into the floating gate are trapped by the high gate-to-oxide energy barrier of 3.2 eV Since the potential energy barrier at the oxide-silicon interface is greater than 3.0 eV, the rate of spontaneous emission of electrons over this barrier is negligibly small The net negative charge which is stored

in floating gates shifts the Vth to a positive value For NAND flash memory, erasing is normally done by FN tunneling A large negative voltage is applied at the control gate and influences the energy band structure as shown in Fig 1 4 The applied VCG

creates the electric field which modifies the potential barrier for the stored electrons, allowing them a path to tunnel from the floating gate to the substrate through the thin gate oxide (Fig 1.4(b))

Fig.1.4(a) Schematic diagram of erasing using the Fowler-Nordheim tunneling mechanism

Fig.1.4(b) Energy band diagram of a floating gate memory during erasing by the Fowler-Nordheim tunneling mechanism

1.3.3 Basic Reading Operation

The “read” operation is performed by applying a gate voltage with magnitude that is between the values of the erased and programmed threshold voltages and sensing the current flowing through the device Once a proper charge amount and a

corresponding ΔVTis defined, it is possible to fix a reading voltage in such a way that the current of the “1” state is very high (in the range of tens of microamperes), while the current of the “0” state is zero, in the microampere scale In this way, it is possible

to define the logical state „1” from a microscopic point of view as no electron charge stored in the FG and from a macroscopic point of view as large reading current Vice versa, the logical sate “0” is defined, respectively, by electron charge stored in the FG and zero reading current In Fig 1.5, transfer characteristic of a FG device in

“programmed” and “erase” states are shown

Fig.1.5 Current-Voltage transfer characteristic of a floating gate device when there are no electrons stored (“1”) and when electrons are stored (“0”) in the floating gate

1.4 Challenges in Flash Memory Scaling

The increasingly fast growth in the non-volatile memory market is driven mainly by mobile applications which provide the market push for the rapid

development of non-volatile memory technology So far, conventional floating gate devices have served the flash industry well For the past decade, NAND flash memory has made remarkable progress to give ever smaller cell size and higher density, as shown in Fig.1.6 [10] There have been three technology innovations for this success (1) The cell area has been scaled-down by 50 % in each generation with a lithographic shrinkage by 70 % (2) The floating gate pattern has always been implemented to maximize the coupling ratio by new process schemes and architectures [8, 9] Coupling ratio is defined as γ=Cblocking oxide/Ctotal (Cblocking oxide is the control gate-to-floating gate capacitance and Ctotal is the total capacitance of the floating gate) (3) Multilevel cell (MLC) has been brought in order to purse much higher density while minimizing the price cost [9]

As shown in Fig.1.6, an extrapolation of the technology trend of NAND flash devices predicts that its minimum design rules will be beyond the 40 nm regime in few years time In this regime, various scaling obstacles such as extremely small tolerance of charge loss, greatly reduced coupling ratio, and severe floating gate interference effects become unacceptably pronounced due to the intrinsic properties of the current floating gate NAND flash

The number of electrons on the floating gate significantly decreases as the device dimension shrinks, as shown in Fig.1.7 Below the 40 nm design rule, less than 100 electrons are stored for Vth shift of 4V An single level cell (SLC) will fail when it loses about 20% of the charge stored on the floating gate In the case of a multilevel cell, the three states must be separated by the same magnitude of V shift,

the multilevel cell can only allow a loss of less than 5 electrons over 10 year period[7]

In order to meet the ten-year data retention requirement at elevated temperatures even after 105~106 endurance cycling without program/read disturb, it has been concluded that the tunnel oxide thickness must be greater than 7~8 nm[12] Scaling of the conventional tunnel oxide for flash memory technology is therefore close to its limits It is practically not possible to further scale down tunnel oxide for the reason of maintaining the retention leakage at acceptably low levels, although scaling of tunnel oxide is highly preferred

On the other hand, it is well known that considerable amount of interface states and oxide trapped charges are generated after repeated program/erase cycling stress Since the generation of interface traps and oxide defects is strongly dependent upon the robustness of tunnel oxide, the improvement of tunnel oxide quality becomes important, and techniques such as preferentially incorporating nitrogen at oxide interface are being explored [7]

To alleviate the lowering of charge loss tolerance, the capacitance between control gate and the floating gate has to be increased A good interpoly dielectric (IPD) layer must be electrically thin enough to ensure good electrical coupling to the control gate This allows for a significant part of the voltage applied over the entire stacked gate structure to be transferred to the tunnel dielectric However, too strong a coupling will actually decrease the VT shift for a given amount of the transferred charge, hence the optimal coupling ratio is obtained by balancing these two opposing constraints Typical CG to FG coupling ratios are currently in the range of 0.6-0.7[11] To allow for good information storage, IPD layer must provide excellent isolation at any

operating condition, involving extremely low leakage currents, under both retention and reading conditions On top of these requirements, a growing concern is the so-called erase saturation problem, in which the erase operation seems to slow down

or even stop During the erase process, electrons tunnel out from floating gate, thus reducing the potential difference across the IPD [12] If the IPD is too leaky, erase can effectively cease as electron removal across the tunnel oxide is counter-balanced by the electron tunneling through the IPD

Last but not least, as a word line space becomes narrower and below 50 nm, the threshold voltage Vth shifts are drastically increased to approximately 0.2 V due to the increased floating gate interference between adjacent cells[7, 9], which deteriorates the cell Vth distribution (Fig 1.8) The floating gate interference coupling ratio is a measure of how much a floating gate device is controlled by surrounding floating gate devices rather than its coutrol gate More detailed calculation of the floating gate interference coupling ratio can be found in [20] Even though the floating gate interference can be improved by using low-κ dielectric material and scaling down the floating gate height, it eventually limits scaling of the floating gate NAND flash technology

0.000.050.100.15

1.4.1 Scaling Limits for Conventional Interpoly Dielectric Layers

In current flash memory technologies, short program/erase times, fast response, and operation voltage reduction are the most important issues for realizing high speed/low power operation [11, 13] To meet such requirements, continuous down scaling has become a necessity for advanced flash memories However, the interpoly dielectric layer (IPD) in a floating gate flash memory device faces many challenges with down scaling The equivalent oxide thickness (EOT) of IPD layers

must be carefully selected to ensure high coupling ratio in the flash memory gate stack This is because in floating gate devices, the coupling ratio should be high enough to allow a significant part of voltage to drop across the tunnel dielectric for fast erase/write operation However, too high a coupling ratio will actually decrease the Vth shift Hence the optimal value of the coupling ratio is determined by this compromise (typical in the range of 0.6-0.7[11]) The coupling ratio is typically improved by increasing the floating/control gate coupling area or by reducing the interpoly dielectric thickness

The impact of the floating/control gate coupling area on the coupling factor becomes a critical issue starting from the 45-40 nm technology generation for both NOR and NAND flash devices, when the spacing between two adjacent floating gates (poly 1) becomes too small to allow the control gate (poly 2) to overlap the vertical poly 1 sidewalls, as is done in the present architecture The lack of electrical coupling between poly 1 and poly 2 along the vertical sidewalls of the poly 1 result in a strong degradation of the coupling ratio and hence requires a strong reduction of the interpoly dielectric thickness as a compensation (less than 15 nm)[13] This situation is illustrated in Fig 1.9 The scaling trend of IPD for both NAND and NOR type flash memory according to International Technology Roadmap for Semiconductors (ITRS) requirement is specified in Fig 1.10 It is observed that for NAND type flash memory below the 45 nm technology node, the required thickness for IPD will drop below 6~7 nm However, decreasing the thickness of the IPD to increase the floating gate capacitance may cause serious leakage and reliability