Digital Circuit Design-Lecture 1 pps

ECE 561 Digital Circuit Design Department of Electrical and Computer Engineering The Ohio State University... Course Philosophy and Objectivepractice as well as principles designing pra

ECE 561

Digital Circuit Design

Department of Electrical and

Computer Engineering

The Ohio State University

Today

Course Philosophy and Objective

practice as well as principles

designing practical digital circuits

Xilinx software and programmable chips

Modern Digital Design

by straight theoretical approach

 Requires use of subdivision of system into Logic Building Blocks Far above the gate level of AND/OR gates.

 Use of CAD

 Use of PLDs and FPGA – state of the art programmable chips.

Course Topics

logic

 Counters, shift registers, comparators

sequential design

Course Topics (2)

 Structured Sequential Design

 Based on Logical Building Blocks

 Complex System = Sum of smaller systems

 Organize functions, inputs, outputs from word description of problem

 Art – choose LBBs and organize

 Science – function and timing

 Design Technology

 Using modern CAD

 Use programmable chips – PLDs and FPGAs

 Use of HDLs – VHDL, Verilog, System C

Combination Logic Design

combinational and sequential, have

millions of gates and several hundred, if not thousands, of inputs and outputs

 Challenges the scope of human comprehension.

correct design” (from text)

complete and understandable

of the circuit or system

The Specificaiton

system is supposed to do

specified

specified

Other aspects of documention

 HDL description both documents and allows for simulation and synthesis of the design

Block Diagrams

modules

Gate Symbols

Active high and Active low

Circuit Timing

 In Comedy

 In Investing

 In digital design

the gate will respond to that change

The output will change (if it does) after

the internal circuitry of the gate settles to the new output state

Circuit Timing (2)

inputs do not arrive simultaneously

combinational logic circuit that is 100%

glitch free It can be design such that

the glitches that do occur are

insignificant

Timing Analysis Tools

Assignment