CHAPTER 4: STRUCTURAL MODELING Lecturer: Ho Ngoc Diem 1 NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING Agenda  Chapter 1: Introduction  Chapter 2: Modules and hierarchical structure  Chapter 3: Fundamental concepts  Chapter 4: Structural modeling (Gate & Switch-level modeling)  Chapter 5: Dataflow modeling (Expression)  Chapter 6: Behavioral modeling  Chapter 7: Tasks and Functions  Chapter 8: State machines  Chapter 9: Testbench and verification  Chapter 10: VHDL introduction 2 Content Chapter 4: A – Overview  What is structural modeling  Primitive gates  Switches  User-defined primitives B – Examples  Combinational Circuit  Sequential Circuit 3 A – Overview Primitive Gates, Switches, User-defined primitives 4 Verilog model for hardware design 5 Verilog design Gate/Switch level modeling Behavioral modeling Dataflow modeling - Primitive switch, gate - User defined primitive -Continuous assignment (assign) - Expression (operators)  There are different ways of modeling a hardware design. Choose an appropriate model to design Combinational or Sequential Circuit.  Some books do not classify Dataflow modeling as a separate modeling type. RTL Design - Procedural assignment - initial, always block - Conditional statement… Structural model  When Verilog was first developed (1984) most logic simulators operated on netlists  Netlist: a list of gates and show how they are connected together  A natural representation of a digital logic circuit  Not the most convenient approach to express the test benches 6 Structural model  Structural - Explicit structure of the circuit - How a module is composed as an interconnection of more primitive modules or components - E.g. Each logic gate initially instantiated and connected to others  In Verilog, a structural model consists of: - List of connected components - Like schematics, but using text: netlist - Boring when write, and hard to decode - Essential without integrated design tools 7 Structural model  Structural Models are built from gate primitives, switches, and other modules  Describe the logic circuit using logic gates 8  12 primitive logic gates predefined in the Verilog HDL  Advantanges:  Gates provide a much closer one-to-one mapping between the actual circuit and the model. There is no continuous assignment equivalent to the bidirectional transfer gate. Primitive gates 9 And/Or/Nand/Nor/Xor/Xnor One scalar output Multiple scalar inputs The first terminal in the list of gate terminals is an output and the other terminals are inputs wire OUT, IN1, IN2; // basic gate instantiations. and a1(OUT, IN1, IN2); nand na1(OUT, IN1, IN2); or or1(OUT, IN1, IN2); nor nor1(OUT, IN1, IN2); xor x1(OUT, IN1, IN2); xnor nx1(OUT, IN1, IN2); // More than two inputs; 3 input nand gate nand na1_3inp(OUT, IN1, IN2, IN3); // gate instantiation without instance name and (OUT, IN1, IN2); // legal gate instantiation Verilog automatically instantiates the appropriate gate. Terminal list Primitive gates 10 [...]... rise= 3, fall= 5, turn-off = min(3,5) // typdelays, rise= 4, fall= 6, turn-off = min (4, 6) // maxdelays, rise= 5, fall= 7, turn-off = min(5,7) and #(3 :4: 5, 5:6:7) a2(out, i1, i2); // Three delays // mindelays, rise= 2 fall= 3 turn-off = 4 // typdelays, rise= 3 fall= 4 turn-off = 5 // maxdelays, rise= 4 fall= 5 turn-off = 6 and #(2:3 :4, 3 :4: 5, 4: 5:6) a3(out, i1,i2); 29 Gate & Net delays 30 Built-in Gate... and # (4, 6) a2(out, i1, i2); // Rise = 4, Fall = 6 bufif0 #(3 ,4, 5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off = 5 27 Gate & Net delays • Min/Typ/Max values For each type of delay three values, min/typ/max, can be specified Min/typ/max values: model devices whose delays vary within a [min max] range because of the IC fabrication process variations min The minimum delay value that the designer... IN1[2], IN2[2]); nand n_gate3(OUT[3], IN1[3], IN2[3]); nand n_gate4(OUT [4] , IN1 [4] , IN2 [4] ); nand n_gate5(OUT[5], IN1[5], IN2[5]); nand n_gate6(OUT[6], IN1[6], IN2[6]); nand n_gate7(OUT[7], IN1[7], IN2[7]); 13 Primitive gates  Example: Gate-level multiplexer // Module 4- to-1 multiplexer // Port list is taken exactly from the I/Odiagram module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); // Port declarations... that the designer expects the gate to have max The maximum delay value that the designer expects the gate to have Min, typ, or max values can be chosen at Verilog run time Method of choosing a min/typ/max value may vary for different simulators or operating systems 28 Gate & Net delays • Min/Typ/Max values // One delay // mindelays, delay= 4 // typdelays, delay= 5 // maxdelays, delay= 6 and # (4: 5:6)... pull1, weak1, highz1 Charge strengths, representing the strength of a capacitive net: large, medium, small 22 Strength modeling Drive strength values of primitive gate outputs Ex: 23 Strength modeling Strength values of nets Strength0 Strength1 Drive strength Charge strength 24 Strength modeling Strength level The stronger signal shall dominate all the weaker drivers and determine the result 25 Gate &... i1, i2, i3; input s1, s0; 4- to-1 Multiplexer 14 Primitive gates  Example: Gate-level multiplexer // Internal wire declarations wire s1n, s0n; wire y0, y1, y2, y3; // Gate instantiations // Create s1n and s0n signals not (s1n, s1); not (s0n, s0); // 3-input and gates instantiated and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); // 4- input or gate instantiated... rtran R tranif0 , rtranif0 tranif1 R rtranif1 R inout2 control inout1 rtranif0 R tranif1, rtranif1 inout1 tranif0 R inout2 20 Switches  Ref “Verilog digital system design , Zainalabedin Navabi for design examples at switch level 21 Strength modeling  Allows specification of drive strength for primitive gate outputs     and nets Gate output or net signal strength values are specified in a set of... instantiated or (out, y0, y1, y2, y3); Logic Diagram for 4- to-1 Multiplexer endmodule 15 Switches  There are two kinds of switch: * MOS switches : cmos, nmos, pmos, rcmos, rnmos, rpmos * Bidirectional pass switches: tran, rtran, tranif1, rtranif1, tranif0, rtranif0  Advantages: - Gates provide a much closer one-to-one mapping between the actual circuit and the model - There is no continuous assignment... the input // basic gate instantiations buf b1(OUT1, IN); not n1(OUT1, IN); // More than two outputs buf b1_2out(OUT1, OUT2, IN); // gate instantiation without instance name not (OUT1, IN); // legal gate instantiation 11 Primitive gates Bufif/notif Gates with an additional control signal on buf and not gates Propagate only if control signal is asserted Propagate z if their control signal is de-asserted... delays 30 Built-in Gate & Switch A gate/switch instance declaration consists of: Ex: nand (pull0, pull1) #(3, 5) n1 [7:0] (w, a, b, c) 31 User-Defined Primitives • The set of predefined gate primitives by designing and specifying new primitive elements • Instances of these new UDPs can be used in exactly the same manner as the gate primitives • Way to define combinational and sequential elements using a . Agenda  Chapter 1: Introduction  Chapter 2: Modules and hierarchical structure  Chapter 3: Fundamental concepts  Chapter 4: Structural modeling. Switch-level modeling)  Chapter 5: Dataflow modeling (Expression)  Chapter 6: Behavioral modeling  Chapter 7: Tasks and Functions  Chapter 8: State