Tài liệu carbon nanotube synthesis device fabrication and circuit design pdf

Thus, this thesis aims 0 develop a suite of techniques, spanning fiom material synthesis 0 cifeuil solutions, compatible with verylarge-scale integration VLSI, Furthermore, thị thesis ti

CARBON NANOTUBE SYNTHESIS,

DEVICE FABRICATION, AND CIRCUIT DESIGN

FOR DIGITAL LOGIC APPLICATIONS

DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

Albert Lin May 2010

© 2010 by Albert Lin All Rights Reserved Resdisrbuted by Stanford University under Ticense with the author

‘This dissertation is online at hups/porlatanlon.edulhÖ64bd9471

1 ceriy that Ihave res this dissertation and that, in my opinion tis fully adequate

in scope and quality asa dissertation forthe degree of Doctor of Philosophy

Philip Wong, Primary Adviser

1 cenily that {have read this dissertation and that, in my opinion, i fully adequate

Ít scope and quality as dissertation forthe degece of Doctor of Philosophy

Subh

ish Mitra

1 comity that have reed this dissertation and that in my’ opinion itis fully adequae

In scope and quality as dissertation forthe degree of Doctor of Philosophy

Yoshio Nishi

Approved forthe Stanford University Committee on Graduate Studies

Patricia J Gumport, Vice Provost Gra

‘This signature page wa generated electronically upon subsson of thi dissertation ia

ectoni format An orginal signed bard cops of he sgeannrs page ison ite in

University Archives

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Abstract

Carbon Nanotube Field Eftect Transistor (CNFET) technology his received a ot of sdenlon in the past ew years as a promising extension to silican-CMOS for future digital logic intezrated circuits, due in patt to its potetil for ballistic transport and excellent intinsic delay While recent research has advanced CNEET technology past

‘many important milestones, robust and sealable solutions must be developed to realize the full potential of CNFETS, Techniques that simply enable the fabyietion of stand lone devices or single experimental demonstrations will not suffice Thus, this thesis aims 0 develop a suite of techniques, spanning fiom material synthesis (0 cifeuil solutions, compatible with verylarge-scale integration (VLSI), Furthermore, thị thesis tims to develop these processing, fabrication, and desien techniques to utilize opticl lidhography and other conventional processes and equipments, thereby delivering a

«athon nanotube technology that is realy adoptable in curent fabrication feilties, Specifically, to enable the re

and prefiminary optimization of such carbon nanotube synthesis, (2) wa

‘Transfer whieh decouples the wrowh processes fiom the device fabrication processes fo enable independent optimization ofthe respective processes, (3) wafer-scale device and circuit fabrication techniques, as well as techniques t0 tune device characteristics and their coresponding analyses, and (4) ACCNT, a VLSleompasible circuit design solution

to surmounting the problem of metallic CNT, along with comprehensive analyses and recommendations for optimal design These techniques culminated in the successful demonstration of CNT transistors, inverters, and NAND logic yates on a wafer scale Furthermore, this thesis sheds light on important design considerations for the demonstration of a simple CNT “computes” and suggests a few critical directions for

future work inthe field of carbon nanotube technology In contibuting the above, this

thesis hopes to propel carbon nanotube technology forward towards the vision of robust, Taruesseale integrated circuits using high-density carbon nanotubes,

Acknowledgments

First, would like to thank my thesis committee, ssthout which this work would be impossible I am forever indebted to my principle advisor Professor H.-S Philip Wong,

\who has offered his support, guidance, and insightfil perspective throughout the yeas,

A great deal of gratitude also goes to my associate advisor Professor Subliasish Mitra for

his guidance and direction, And, I lke to thank Professor Yoshio Nishi for is support in_my caybon nanotube synthesis work using his PECVD equipment and for his invaluable input while serving on my thesis orl and reading committee

Next, I would like to thank Nishant Patil and Hai Wei, with whom elose collaboration Fed to several great results, as presented in the frst Few chapters af this thesis work, This collaboration as unlike any other, and allowed this earbor nanotube work to achieve reat successes in very short periods of time

| would also like to thank several collzboratos for their help and cooperation,

‘cluding Deji Akinwande, Cara Beasley, Hong-yu (Hensy) Chen, Xinsuyu (Helen) Chen, Jie Deng, Arash Hazeghi, and Sie Zhang Through them, [leesned much reyanding carbon electronics, material science, chemistry and physics, which allowed me to be more effective in my work, this help also divectly contnibuted to parts of my work

In addition, 1 would especially like to acknowledge Dr, James MeVitie for his expertise and help in configuring and upgrading equipment for carbon nanotube synihesis, The staff members of the Stanford Nanofebrication Facility have also heen extremely helpful in my work on carbon nanotube device fabrication, offering ereat advice and always ensuring that any obstacles én the fab are quickly resolved, Tom Carver of Cinzton Laboratory has also been temendously helpfal in the icon catalyst deposition for nanotube growth

This work was funded in part by FCRP C2S2 and ENA, NSF, and the Stanford Fellowship Award This work was done partly in the Stanford Nanofabrication Facility (SNF) of the National Nanorechnofouy Intastructure Network (NIN).

(Chapter 3 Wafer-scale Transfer of Aligned Carbon Nanotubes and

4.1 Background - The Mu

5.2 Optimal Solutions and Design Flow “

Chapter 7 Concluion

List of Tables

‘TAHLEL CONSTRNCTION OF IIIs ACCNT CNFET The second column illustrates how

Tras "

the ACCNT CNFET (in this ease, “Parallel Rows” implementation) is

‘constricted from conventional CNFETS, The third column sunimarizes the probability (Pm) of obtaining overall semiconducting characteristics With high on-of? ratio, (For clarity, Pitan for a CNEET, ACCNT Row, and ACCNT CNFET is labeled as Peer, Pycosr non and Paco ewer respectively)

IMPLEMENTATION OF Staves poR I-HP ONE4MSIRUCHON-T.CNT CompUrran, Note tat the output of the branch condition comput

bbe divectly fed ito the instruction memory as the least-signiicant bit (LSB) inthe instruction adress

“4

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List of Figures

Figure 1.1 Carbon Nanotube Structure

Figure 2 Mlustation of Carbon Nanotube Field-Erfeet Transistor a Figure 2 1 Examples of CNT Grows (a) Disorderly (not aligned) CNT growth (6)

Aligned CNT growth using striped catalyst on quartz 8 Figure 22, Water-scale Aligned CNT Growth Process, Red diamonds indicate the a

B transition point Temperature curve is approximate 10 Figure 23, Example of Water-scale CNT Growth Results (a) Low-magnitication,

ued CNTs with a linear density of roughly

Figure 24 SEM Results em S Regions across a 4” Wafer Growth is observed

‘Figure 25 Mistograms of CNT 2-point Electrical Results fiom § Rewions across 2 4”

Figure 2.6 CNT Characterization Results (a) Diameter distribution measured using

Atomic Force Microscopy (AFM) (b) Summary of CNT teaath and

Figure 27 Opimization of Catalyst Stipe Pattern The best catalyst stripe

dimeasions consist of 4ym width with LO0 or 200, piteh, as shown in

Figure 32, Example of Waferscale CNT Transfer Results The left side shows SEM

images of CNTs on the original growth substrate (quattz) at various magnifications, the right side shows CNTS aller wansfer to a SiO3/Si substrate, Note thatthe CNTF density and alignment are preserved through

Figure 33, Histograms of CNT Device Electrical Results fom § Regions across a4”

Silicon Wafer after CNT Transfer and Device Fabrication Current ploted

is on-state cument of the CNFET device, (Buck-gated deviee, back-gate oxide is $oam SiO, Soy, jam, Va M, Vog=1V)

Figure 24, CNFET Device Structure Diagrams and SEM Image Diagram is not drawn

toseile

Figure 3.5 Example of CNFET Device Results The CNFETS have well-behaved Jo-

Vis and fy-Vos behavior For the fy-Pas eurve, Vis = -1V Por the fet curves, Ma= BV, -2V, -LV, and OV respectively fom top to bottom,

‘Threshold Voltage Setting was

igure 4.6 Example of Threshold Voltage Setting

Figure 3, Threshold Voltage Setting Design Curve with On-current mT, CNT density vs, Threshold

Voltaye Trade-off Threshold Volape Setting was repeatedly applied to 6 CNFETs to sweep the design space The black arrowed line is the corresponding Gaussian Cumulative Distribution Funetion (CDE) fit and represents the attainable design points For on-current vs threshold voltage trade-oft The results also suggest the distnibution of #9» is Gaussian

V and Fal,

With sor err 245V aM øn 20 2V, Uogrle at Fac

Wil=S0g0/ Im, CNT density = 13 CNTS/um),

Figure 38, Distibution of Overall CNFET Threshold Voltage for 11 Devices The

Uistibusion was measured after one Threshold Voltage Setting step (target, 1; = 3V), The average threshold voltage shifled down and the absofute variation" of the device threshold voltages also decreased significantly,

re 39 Example of On-off Ratio Tuning A multiplesube CNFET with metalic

‘ENTS already broken dawn shows an on-off ratio of $10", On-off Ratio Tuning is applied ice to improve the on-off rao 10 9-108 1" Tune")

an then 19 3-108 C2" Tune’) Fe ju; CNT density

Ratio Tuning on these metallic-CNT-void devices further removes hig

leakage semiconducting CNT and the on-of eatio can be adjusted (om

~5⁄10Ÿ to ~S:10') while wading off current density But iter all high leakage CNT are removed, high-on-current semiconducting CNTs begin

to break down with excessive application ofthe technique, so both eurrent density and on-off rato are reduced, The black curveiarrow in Region ®

SV, Lage a

approximates the attainable design points Ufo at V

¡ rs, CNT density = 1-3 CNTsium)

“The "Metallics NT Problem” (a), (b) Cartoons illustrating that CNFETS consisting of ealy metallic CNTS act like metallic wires; and CNFETS

consisting of only semiconducting CNTs have excellent on-of? ratios, up

to 10% (¢) Experimental dats lustating that CNFETS with @ mix of semiconducting and metallic CNTs have low on-off ratio; the inset shows the same data on a linear scale (Q) Experimental date illustrating that inveners (and cicuits in general) constructed from such CNEETS do not funetion correctly de to the presence of metallic CNTs,

Figure 42 Illustration of the Asymmetric Correlations Inherent in CNFETs

Fabricated on Aligned CNTS The top SEM shows aligned CNTS grown, fiom striped catalysts The bottom SEM also shows a conceptual cartoon illuscating that CNFETs fabricated along the same column consist of the same CNTS and are highly correlated (identical, and CNFETS fabricated

33

3s

38

(independent

Figure 43 Optical Micrograph and SEM Image of a Conventional CNFET

Consisting of 4 CNTs The conventional CNFET has severely degraded Golf ratio in the presence of metallic CNTs (also see Figure 4.10), making it unsuitable for CNT VSL

Figure 44 Thee Possible Implementations of the ACCNT Design (a) Cireut

schematics are drawn to bes illustrate the topographical hierarchy feom

Suits are redrawn to

where they derive their names (b) The same

highligh the differences as compared tothe Parallel Rows implementation inorder to illustrate the extra connections The three implementations are exact equivalents assuming all CNFETS within the same column are identical; however, the Weave reduces the number of contaets (and thus reduces area) by sharing the con ets of adjacent rows (see also Figure

49

Figure 4.5 Optical Micrograph, SEM Image, and Layout Diagram of the ACCNT

Weave Structure, The Weave combines contacts between adjacent rows to reduce the numberof confaets / denotes the mininnum feature size; Wand

1 denote the CNFET width and length

Figure 46, Verification of Asymmeric Coalations (6) Optical micrograph of 44

matrix of CNFETs (b) A close-up SEM image of 4 of the 16 CNEETS Notice that CNFETS within the same column consist of the same CNTS, while CNFETs in different columns consist of different CNTs () Electrical -’ data for each of the 16 CNFETS in the matrix, Within the same column, CNFETs show very similar characteristics (-identica However, within the same row but aevoss columns, the /Idata are not the same and no dependeney is observed (independent)

Figure 47 An ACCNT Row Consisting of Seriesconnected CNFETS with

Incermetiate Source/Drain Contacts Tapped for Probing, The CNFETS are connected in series along the x-direction (independent direction) (a) The

a

a

49

st

SEM inn

show that the CNFETs consist of diferent CNTs (b) Cireuit Schematic and electrical /-1° data illustates shat a semiconducting tink (NG-N8) can help che overall series chain (NO-NI6) exhibit semiconducting device characteristics, while no high on-off ratio is observed wien excluding this semiconducting link (e NO-NO),

Figure 48 ACCNT Rows Tiled in the y-ticection are Kéemical (a) The SEM images

show 12 ACCNT Rows tiled in the y-dieetion, exch with 24 series connected CNEETs The ACCNT Rows consist of the same CNTs (b) Scatter plot of electrical data showing similar (-identieal) characteristics among the rows, Visual guides for on-off ratios are also included (L1 of

12 data points are plated; | ACCNT row was defective due to faulty Tiduography and thos omited )

Figure 49, ACCNT Results, A comparison of a conventional CNEET and ACCNT

CCNFET Elecsical /1° data shows the conventional CNFET (blue) has # low on-off ratio of ~3 and an ACCNT CNFEF (zed) built from 24424 of such conventional CNFETS with a high on-off ratio of 2x10! The evo data plots represent the same data on Tnear nd Toy seale respectively W-Loym and CNT density=~1CNTiumn,

Figure 4.10, Pseudo-pMOS inverter Designed using ACCNT An ACCNT Weave

CNFET was used as the pull-up transistor; an ACCNT CNFET with 3

‘constant gate bias was used esa resistive pulldown, As compared tothe cconventional-CNFET inverter in Figure 4.1d, the ACCNT inverter has much better swing (-3.6V swi

8 shaper transition (~8« gain), and static power (eakage) that is negligible (below the noise Moor of the measurement equipment) For both ACCNT CNFETS

and Noyye=4 (W4um and CNT density=~ICNTIumn), Note that for this

‘demonstration, the area and layout was not optimized, (The inverter does

`

not pull down to ground in part due to the use of a p-type CNFET as a pulldown )

85

56

Figure 4.11, Pseudo-pMOS NAND Des

CNEETS were used for the pull-up network, an ACCNT CNFET with 3 ed using ACCENT Two ACCNT Weave constant gate bias was used as a tesstve pull-down, The ACCNT NAND has correct functionality with 4 3V swing and =7

tate does not pull down to ground in part due to the se of a p-type

Figure 4.12 Optical Photos of ACCNT Structures and Devices on a Wafer Scale

Figure 5.1 Mlustration of Pavsss ) Poyav,, đồ vatious mip and Nee

(= pron =66%0 is used for ease of comparison with experimental data,

Aosg only, 8 new desiun point is reached that exchanues metallic-CNT tolerance for current drive oF vice versa, AS mas is inreased, Pravin

improves, but the current decreases Current dkive is nommalized lo the single-nanowube current j For clarity of illustrating the general shape of

Figure $3 Poy, Space and Tradeof As my is increased,

Porous improves, bt area inereases as Neves increased, both area and metlli-CNT tolerance are made worse, Area is normalized to that of a conventional CNFET (ie ACCNT with tal & m=) (a) An example where thar is kept constant (b) An example here Moy, tracks

‘mag, Such that dane is kept constant along 8 given eurve, 6s Figure S4 Hiasation of Dejgn Guideline (DGI) under Constantams, (and

Constante.) Optimization, The eartoon compares a few designs forthe

case where Nu°2nnsFD, in which the original design pon iet lo the

Fight of the minimum, Point A marks the original design, Point B marks a better design which has the same area (and same current drive by construction), but has an improved Pris Since Noy is smaller Point

(C marks the minimum-area design point and designs to the let of Point C sue Pareto optimal in the context of constant, optimization sa Figure $$ N* and Nn Design Guidelines (DG2) and (DG3) (a) Values for N* and

1X" ‘The blue data shows the diserete-case solutions for N*; the rod data shows the discrete-case solutions for A” The black lines are the corresponding continuous-case solution where the design variable Nowy is not quantized The V’ equation is an approximate bes fit tine For Nn the range of Pins shown (b) N* (mentioned in Design Guideline (DG2)) represents the maximom-Py ism desis point under constant,

‘optimization, A necessary condition for Pareto optimality is that the design must have Neve © N* (€) NY (mentioned in Design Guideline (DG3)) represents the upper-bound estimate of the minimuss-area design

Point under constanto, us9 optimization, A necessary condition for Pareto optimality is that the design must have Nor N a Figure 5.6, Metalic-CNT Tolerance and Area TradeotT for Pareto Optimal ACCNT

CNFET Designs Metllie-CNT tolerance (Posi) is posted as “Yield Loss” (+ Posies) for clarity Area is normalized to that of a conventional CNFET The continsous-case results are show in dashes

black; the diserete-case solutions are shown in red dois (P=Inm,

Figurs 57 ACCNT Improvesthe Piebabily of Noise Margin Violation (PNMV) A

pair of cross-coupled inverters in an SRAM cell with 09V Tipp is sionulated using the Stanford University CNFET Model [42] to extract the noise masyin A noise margin less than 0.22SV (one-fourth of 1

defined asa violation, By using ACCNT, the PNMis greatly reduced 78 ois

Figure 58 Cireuittevel ACCNT Reduces Area Cost Data is for a one-million-

transistor chip By employing cicuit-level ACCNT, which uilizes sets of correlated ACCNT CNFETS that lie on the same CNTS, a tanger chip yield san be achieved with a smaller area, The correlated ACCNT CNPETs effectively reduce the requirements on the device-Tevel is, lich

Figure 6.1

Figure 62

Figure 63

Figure 64 Timing Diagram for Computer Signals The processing un

allows & smaller thoy, and may; to sufce, and significantly reduces the

aren overhead The continuous-case results are shown in dashed-black; the diserete-case solutions are shown in blue and red dots, Total device area is normalized 19 that of a conventional CNT design {marked as green “X")

low Chart Ilustrating Conditional Execution Branching tom: 1 I00gA, /,s;=4000mm,

Example of the 2-bit (oneg Instruction Implemented using L-bit Subne Instructions", Dy is @ memory location that alway’s Holds the value `0 and cannot be otherwise overwritten, DA, is memory location that allways holds the value “I” and cannot be otherwise overwritten, Note that the instruction addres inthe swbneg insiaution above consists of only the first 3 MSBs ofthe full 4-bit address

Simple CNT Computer Design with Integrated CNT Processing Unit The Integrated processing unit is a [bit combinational lovic block The memory blocks are off-chip components and the address bus widths are independent of the integrated processing unit design The memory blocks also have implicit input ané output latching, As shown in Figure 6.4, the Instusetion Memory and Data Memory operate in two different phases fn Phase 1, the Instruction Memory internally latches the address and the corresponding output settles upon read, in Phase 2, the output is latched

and fed Por the Data Memory the read is performed in Phase 2 (the data auddresses are intemally latched while the corresponding data output settles im Phase 1, the data output is latched and held, Furthermore, in Phase 1 the wste addtess and write data (B-4) are also internally latched, then write occurs: since the data output is already latched, the write

‘operation does not cause the output 0 change

Figure 5

Data Memory in Phase 2 (¢3), Write occurs inthe Data Memory in Phase

1 (91) The memory blocks have interna input and output latching 96 CNT Position Comtol is Important Precise density pitch contol alone is insufficient fn this example, a high-performance CNFET design targets 4 CNTs, bur depending on the exact postion of the CNTs (the two cases show different shits in the CNT positon), the result ean be either 3 o¢ 4 CNTs in the CNPET, regardless of precise pitch control It may be possible to guarantee exactly 4 CNTs in the CNFET by choosing s device width exactly equal to 4 times the CNT pitch, if daht lithouraphy tolerances can be achieved, Hovvever, even so, the Targer width results in larger parasitic capacitances without improving device drive current and

Figure 66, Hlustation of Sưuetore-lireetel CNT Growth (SD Growth) Structure:

directed CNT Growti allows precise pasition control of CNTs during srowth, This enables precise density and piteh control, among other advan ‘One and only ane CNT is assumed to be guided 10 completion

by each structure, Blue lines represent CNTs Figute not drawn to seal, 100 Figure 6.7 Preliminary Structae-diected CNT Growth Results A CNT is seen in

Figure 68 Sirucute-directed CNT Growth Prevents Problems Due to

this SEM image following the angled structure, then growing straight slong the preferred growth direction after reaching the end of te structure

‘The catalyst stripe (not-pictured) is located towards the bottomeft 101

(growth is in the +y-direction), Even though the «wo

«eases show there is no postion contro! in she nucleation (i.e starting point)

of the CNT growth, the structures force CNTS to segister to a precisely defined grid and the CNFET is patemed on these well-positioned CNTs Thus, the CNEET is ensured to have exactly: 4 CNFETs, Also note that stray unwanted CNTs are now blocked an do not come near the CNFET

Figure 6 Example of Potential Applications of Stucturesdirected CNT Growth

Figure 6 10 Simulation of Potential Energy Barrier and Well caused by a Structure

Van der Waals tnetive forces were simulated (a) Cross-section heatmap, Dark blue indicates the substrate The step height ofthe structure is 200m, The potential energy asa function of postion was calevlated for positions above the substrate Red indicates a lage negative potential energy: blue indicates a small negative potential energy (b) Potential energy evaluated slong the dashed line in (a) There exists & large ener’ harrier atthe top

of the step, there also exists a lare energy well a the bottom of the step (©) Comparison of potential energy governing CNT aligned growth versus that governing Stucturedirecied Growth The results show the detailed potential energy profile near the “lif {eneray hares) ~ the potenti energy is dominated by that caused by the step stucture (tye center peak) and not that caused by the quartz lattice quantization (small ripples to the side), which is representative of the enerpies that contibute to the CNT alignment observed for growth on single-crystal quartz os Figure 6.11, Interleaved ACCNT Design for Parallel Connections for Reduced

Transistor Variation, In addition, the interleaved design reduces the probability of failure due to open-cireuit defects, as well as reduces the

Figure 6.12, Sea of NANDs, The NANDs can be individslly tested to determine

those tha are defective from those that are fusetioning, The NANDs can, then be wired together to achieve higher-order functions via 2 die- customized lithoersphy and metal deposition step The left SEM image shows just one NAND, illustrating the implementation of the Desixs for Reduced Variability described in Section 63.3 The Sea of NANDs shown

Figure 6.13 Example of lteurated CNT Processing Unit Implemented using NANDs

‘The CNT processing unit is described in Section 6.1 This implementation

uses 6 NANDs However, the NAND in the top-left acts as an inverter and

is optional ~ the result isthe LSB of the nest instruction memory address (see Seetion 6.1), which can rem inverted as long as the memory locations are all switched correspondingly (ie provided a corresponding compiler correctly puts the non-branching instructions in the odd auddeesses as oppased to the even addresses, and the branching instructions

in the even addresses a opposed 10 the odd addtesses), In this ease, only S NANDs are needed, Ifthe NANDs are implemented in pseudo-pMOS (3 CNFETS per NAND), te total number of transistors requived here 1s 15,

28 opposed to 12 transistors asin Section 6.1.2 However, by creating a

se9 of NANDs to be connected post-testing the probability of obtaining 8

Figure 6 14, Pseudo-CMOS Logic Style for Improved Output Swing, The example

circuits above implement the NOR and NOR ates used in the integrated CNT processing unit in Tamir Hl, Similarly, the pseudo-CMOS style can

Figure A.L Custom-built Furnace used for Carbon Nanotube Growth Professor

Yoshio Nishi of Stanford University has kindly granted permission forthe use ofthis 4” furnace towards the research herein lại Figure C 1 Impact of Density Variation an ACCNT (a) Density vatiation can cause

ACENT CNFETS to have open cieuits, where an entire column of CNFETS are “void of CNTS due to correlation, as highlighted by the red

‘box (b) Experimenta Probability Mass Function (PME) thet characterizes the density variation observed (39] For ACCNT CNPETs with a small

target Nov, thete isa non-nepligible probability that some CNFETS end

Figure C2, Design Space of PZ With Density Variation, This new expression

fr Prati takes ine account de sity variation (Eq (C.1)) Por ease of comparison with Figure $14 (Pooassay without density variation),

Pan66% is used The gray dashes line represents the ideal ease if Pon

\were unity; this forms an upper bound marking the limitation imposed by

Chapter 1

Introduction

1 Background

Electronics have historically shown a steady evolutionary trend ~ the integration af

‘more features and complex functions into an ever smaller size, As this rend progressed,

‘nave after wave of innovative elecronies reached consumers, stating with those that rest fom desk, to those that sit on a lap, and now to these that ship ino & pocket, With d

Inthe future, one could expect tha ultra-mobie electonies, as well as smaller sensor and communication electronics, will continue to demand faster, smaller, and more powe

efficient integrated circuits as they become omnipresent and increasingly iniewrated sno cur dey fives As suc, itis more important than ever that technologies be developed to enable the continued scaling of power-elficient integrated citewits far into the future Unfortunately, continued scaling of slican-CMOS technologies is expected to face tough obstacles in the relatively nearfunure according 10 the Intemational Technology Roadmap for Semiconductors (ITRS) [1] Imposing power-elfcieney specifications further exacerbates the problem, As such, several new materials are being considered to complement oF replace silicon

1.2 Thesis Motivation and Contril

Carbon nanotube (CNT) technology offers a viable path forthe continued sealing of integrated circuits and has received much attention in recent years as a promising extension fo silicon-CMOS, Carbon nanotubes are a form of carbon arranged in a tube- like geometry (Figure 1.1) with excellent electrical conduction properties, among others

‘Specifically, they ate 1-dimensional materials with the potential for ballistic transport and sSunificantly reduced scattering, Thus, carbon nanotube field-effect transistors (CNFETS), transistors made from single-walled carbon nanotubes as illustrated in Figure 1.2, have excellent intrinsic delay ~ they offer superior curent conduction and less eapactance [2

“The excellent intrinsic delay translates into both higher performance (speed) as well

as lower power consumption in digital logic applications [3]{4)S] In simulation results, CCNFETS achieve significant performance advantage aver silicon-CMOS in both inverter fanoutof-4 (FO4) delay (47x) and energy per cycle (2.6%) [3] {4} and in a system-level

Figure 1.1 Carbon Nanotube Structure

Figure 1.2 llustraton of Carbon Nanotube Field-Etfect Transistor

comparison to Iinm partially depleted silicon-on-insulater (PDSON) teehnolosy, CNFETS are projected to achieve 5x speed improvement fora four-core processor [5] In addition, the small size of we carbon nanotube (-Inm in diameter) potentially allows for

‘high transistor density and thus small chip size Consequently, carbon nanotubes can enable faster, smaller, and more powereffcient integrated circuits and consumer electronics

While recent research has advanced CNFET technology past many important milestones, to realize the fll potential of CNFETS, robust and scalable solutions must be

‘developed Techniques tha simply enable the fabrication of stand-alone devices or single experimental demonstrations will not suffice, Thus, ths thesis aims to develop a suite of techniques, spanning fiom material synthesis to circuit solutions, compatible with very large-scale integration (VLSI), Furthermore, this thesis aims to develop these processing, fabrication, and design techniques to ulize optical lithography and other conventional

processes and equipments, thereby delivering a carbon nanotube technology that is readily adoptable in current fabrication facies

Specifically, to enable the real-world engineering of carbon nanotube int

circuits, this thesis presents (1) wafer-seae aligned CNT growth, and the characterization and prelimina ‘optimization of such catbon manotuhe synthesis; (2) wafer-seale CNY Transfer, which decouples the growth processes ftom the device fabrication processes to enable independent optimization ofthe respective processes; (3) wafer-scale device and circuit fabrication techniques, as well as techniques to tune device charactecistcs and their corresponding analyses; (4) a VLSL-compatible cireuit design solution to surmounting the problem of metallic CNTs, along with comprehensive analyses and recommendations for optimal design, and (5) directions towards the demonstration of 3 simple CNT “computer” and Fate work

In contributing the above, this thesis hopes to advance earbon nanotube technofouy forward towards the vision of robust, large-scale integrated circuits using high-density carbon nanotubes

1.3 Thesis Organization

‘his thesis is organized as follows Chapter 2 presents matte: eoncesning CNT synthesis, including quartz annealing, CNT growth, and results and charaeterizations Chapter 3 describes techniques for carbon nanotube device fabrication, inluding water- scale CNT Transfer to relocate CNTs fiom the growth substrate to the fabrication substrate, Chapter 3 also explores device tuning techniques to achieve threshold voltage and on-off ratio control Chapters 4 and $ intraduce 2 novel design solution, called ACCNT, to the problem of metalic CNTs, first, concepts and experimental

demonstrations are presented (Chapter 4) and then in-depth analyses and design

guidelines for optimal ACCNT design are examined (Chapter 5), Next, Chapter 6

discusses design considerations towards the demonstration of simple CNT “computer” 2s well as rections for future work Finally, Chapter 7 concludes tis thesis dissertation.

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Chapter 2

Wafer-scale Growth of

Aligned Carbon Nanotubes

Material synthesis is fundamentally an important topic in cebon nanowbe technology ~ by symhesizing better carbon aanotube (CNT) gariag mateiils upon which CNT devices and circuits are built, beter device characteristics and circuit performance can be attsined In this chapter, thesis contributions to the domain of CNT

‘material synthesis are deseribed

24 Background

Ealy forms of CNTs lacked alignment and directionality; Figure 2.18 shows an example of such CNTs These CNTS can be synthesized in a chemical vapor deposition (CVD) furnace using metal or ferritin! particles and silicon as substrate [6] Subsequently wwellaigned nanotubes on single-crystal quartz substate were demonstrated,

2 200 TREE, Pat of Us capt has hsm rep ih ernisdoa, (on N ai Á La, E R Me

K Bạn A Dalnues, C Zhan IES P Wong ane § Mts, Mlaer Sele Grow ad Tras of

roduate students at University of Southern Catenin olvsed by Prov Chong Zhou

"Fern sigan psi tht sre eo as ore Dang the CNT poh rest tev

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©) Figure 2.1 Examples of CNT Growhs (a) Disordery (not aligned) CNT

‘grovan,(b) Aligned CNT growth using striped catalyst on quartz

further improvements have been made by employing a striped catalyst technique [7] (Figure 2.1b shows an example result) Such aligned nanotubes are preferable for circuit

design as they allow predictable channel lengths and ballistic nanotube transistor structutes to be designed However, many ofthe aligned CNT results thus far are done on small samples in small growth furnaces, eg I-inch furnace that use a furnace tube only

‘-ineh in diameter [6]; typical sample sizes in such furnaces are less than 1 in in size This is simply inadequate for large-scale applications

For CNT VLSI large-scale CNT growth is needed Growing CNTS on small pieces

‘may suffice for single-device demonstrations consisting of few CNTS, but to engineer and build citeuits consisting of more than thousands of devices, each with multiple nanotubes in the channel, waferscale growth is needed This chapter presents work on wafer-scale aligned CNT growth which addresses this concern

22 Wafer-scale Growth Process

There ate two primary obstacles regarding wafer-scale CNT growth The First obstacle is that the single-rystal quartz substrate? often will shatter if conventional

“pieces-yiowih” processes are directly applied to an entire quartz, wafer That is, those processes may work fine on small samples (pieces), but they are not fine for wafer-sized samples This is because single-crystal quartz is very brittle and underaoes a quartz, leansformation at around S73°C [8], while most existing CNT CVD growth processes involve temperatures of 800-900°C for the growth phase So, if the thermal gradient fromm the temperature ramp-p is to great during this wf transition, the quartz ean shatter In addition, even at low temperatures, ifthe thermal spatial uniformity is not well controlled, the quartz will also shatter Thus, to overcome this fst obstacle, the solution is to cateflly control the thermal change across both space and time The second obstacle is

that growth must not only ogcur, but it must also eccur across the entire wafer and Uniformly so To achieve this, the groval process mist be appropriately sealed and optimize

Prior to growth, the quartz is strengthened through an extensive

‘quartz annealing process In short, the process involves 4 slow ~Ashour ramp-up {w 900°C, followed by » -8-hour anneal in Os st 900°C, and thes a ~4-Nour ramp- down O; is owed during most of the ramp-up and ramp-lown as well, The Ueuils of the process sieps ean be found in Appendix A It was found enopiically that the quartz isles likely to shatter during growth after this annealing treatment This annealing provess also repairs the surface of the quartz, which improves cnr,

‘Veoderntomation Holton Materia, LC, Case Peony ania USA,

°

(2) Improve thermal uniformity and ramp

Next, the CVD fumace was modified (© operate with 3 heating zones to improve thermal uniformity across a ~16-inch region in the furnace tube In addition, the pressures are reduced (iypical“pieces-growth” processes use Tatm), particularly during the a-B quartz transition, to further improve thermal uniformity

as temperature is ramped up and down, That is, with & lower pressure, the thermal ass of the gases inside the furnace is smaller, which allows the temperature controller to better contol the temperature across the entire region-oFintrest hưởng the ramp, Also, the temperature ramp rate is reduced, particularly around the a-B transition temperature range, With quanz annealing and bette thermal control, the single-crystal quartz substrate no longer shaters

(6) 4" water-scale grow process

Lastly, to achieve waferscale growth, the gas flows and calcination steps

‘ust be sealed appropriately and adjusted to achieve good CNT density, length,

AT Time (minutes)

Figure 22 Wafer-scale Aligned CNT Growth Process Red diamonds

Indieale the œB transition point Temperature curve Is approximate

tô

including lyst preparation and the growth process, can be found in Appendix

‘A In summaty, the growth process employs the striped catalyst technique with e« beam evaporated iron as nanoparticle catalyst The growth is performed at 864°C with methane as the carbon source (and 8 co-flow of hydrogen)

2.3 Results and Characterization

Wafer-scale aligned CNT growth was successfully demonstrated using the process described in Section 22 The SEM results in Figure 23 show good CNT alignment and density

Nex, SEM images are obtained to verify that growth is obtained faisly uniformly* across the wafer, Figure 24 shows SEM images taken across 5 different regions of the

|

®) Figure 2.3 Example of Waler-scale CNT Growth Resulls (a) Low

‘magnification, millmeter-scale SEM image of CNT growth, (6) High-

‘magnification SEM image showing aligned CNTs with a near density of roughly TCNTslum

@

"nom ona macs, comparing werge deasty rm eon 0 region

"

wafer, the regions all show CNT growth with approximately the same average CNT linear density In addition, 2-point measurements are taken (Figure 25) to verify thatthe (CNTs are indeed electrically conducting, also shown i the variation in each wafer region

Figure 2.4 SEM Results from 5 Regions across a 4” Water Growin is observed across the ene wafer

R

Right

Figure 2.5 Histograms of CNT 2-point Electrical Results from 5 Regions across a 4° Wafer (WS0um, L=1ym, Vos=-1V)

the CNT diameter distribution was characterized using

nic force iiiccoseopy (AFM), The results are shown in Figure 2.68 ~ the average CNT diameter is

| 2am, indicating these are indeed single-walled CNTS The majority of the diameter Aistrbution is also in an appropriate range for semiconductor applications ~ a typical Inmtiameter semiconducting CNT has a band gap of roughly 0:9eV [9], Figure 2.66 Iso summarizes the length and density statistics obtained from this waferscae aligned CNT growth process

15

o=0.3nm _10

measured using Atomic Force Microscopy (AFM) (b) Summary of CNT

length and density statistics

Lastly, the CNT growth process was further optimized by investigatiny the optimal catalyst stripe pattern A large catalyst stipe yields more CNTs, resulting in @ higher linear density, however, it reduces the useful area for CNT deviees (whieh ae patterned fourside the stripes) On the other hand, a small catalyst stripe may yield insuficient rowth to produce stisetory CNT density Similarly, the pitch ftom stipe to stipe val affect the CNT density, maximum possible CNT length, andthe faction of useful area

In conclusion, this chapter presents the development of wafer-seale aligned CNT srowth and ts results This wafer-scale aligned CNT growth process i subsequently used

in all ofthe work presented in this thesis

10ff'

Figure 27 Optimization of Catalyst Stripe Pattern The best catalyst

stripe dimensions consist of 4m width with 100 oF 200um pitch, as

shown in the bottom right images