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Trang 636 CMP Fill Synthesis:
A Survey of Recent Studies
Andrew B Kahng and Kambiz Samadi
CONTENTS
36.1 Chemical–Mechanical Polishing 737
36.2 Impacts on Interconnect Design and Manufacturing 739
36.3 Characterization and Modeling Approaches 741
36.3.1 General CMP Process Models 741
36.3.2 Oxide CMP Modeling 742
36.3.3 Copper CMP Modeling 743
36.3.4 STI CMP Modeling 745
36.4 Density Analysis Methods 747
36.4.1 Fixed-Dissection Regime 748
36.4.2 Multilevel Density Analysis 748
36.5 CMP Fill Synthesis Methods 749
36.5.1 Density-Driven Fill Synthesis 749
36.5.1.1 LP-Based and Monte-Carlo-Based Methods 751
36.5.1.2 Iterated Monte-Carlo and Hierarchical Methods 752
36.5.1.3 Timing-Driven Fill Synthesis 753
36.5.2 Model-Based Fill Synthesis 754
36.5.3 Impact of CMP Fill on Interconnect Performance 754
36.5.3.1 Fill Patterns 755
36.5.3.2 CMP Fill and Interconnect Capacitance 757
36.5.4 STI Fill Insertion 758
36.6 Design Flows for Fill Synthesis 760
36.6.1 RC Extraction and Timing Closure 761
36.6.2 Impact of Spatial Variation 762
36.6.3 Topography-Aware Optical Proximity Correction 763
36.6.4 Intelligent CMP Fill Synthesis 763
36.7 Conclusion 765
References 765
36.1 CHEMICAL–MECHANICAL POLISHING
Chemical–mechanical polishing (CMP) is the planarizing technique of choice to satisfy the local and global planarity constraints imposed by today’s advanced lithography methods [36,58] As device geometries scale, there is an inevitable need for better planarization of the multilevel interconnect structures Older planarizing methods, such as flowing oxide layers, spin-on glass (SOG), and reverse etchback (REB) can no longer meet the lithographic and other requirements of modern multilevel metallization processes [52]
737
Trang 7Wafer
Conditioner Slurry
FIGURE 36.1 Thin film formation in SOG method (Modified from Toan, N.N., Spin-on-glass materials and
applications in advanced IC technologies, Ph.D Dissertation, Universiteit Twente, Netherlands, 1999.)
SOG is a method that consists of coating the surface of a particular layer with SOG materi-als These materials can be categorized into three different groups: (1) silicate-based compounds, (2) organosilicon compounds, and (3) dopant-organic compounds In SOG, the silicon wafer must be cleaned before coating The wafer is placed on a spinner and approximately 1 mL of SOG material
is dropped on the center of the wafer Then the carrier holding the wafer (Figure 36.1) is rotated
at several thousand cycles per minute to create a thin layer of SOG material on the wafer In most cases, a film thickness between 50 and 500 nm will result Controlling the thickness is a matter of controlling the solution viscosity Among the various techniques for planarization, the SOG method
is advantageous because of the simplicity of the process, the good adhesion characteristics, and the low level of stress and shrinkage in the SOG material [67] Implementation of the SOG technique requires thorough understanding of the glass and the stability of the remaining material, which leads
to considerable variation in the practicality of this technique [52]
REB uses a second mask to etchback-raised areas to lower the pattern density The etchback mask
is created by shrinking all features on a given layout by a fixed amount called etchback bias This results in removal of the majority of the raised material if the features are large Selective reverse etchback uses customization of the etchback mask to reduce the amount material that is etched away [37] Although the REB method is understood, it suffers from complexity and significant cost due to extra masking steps It also requires a significant amount of monitoring to control the level of defects caused by the process [52]
Chemical–mechanical polishing uses both mechanical and chemical means to planarize the surface of the wafer In a typical CMP tool, the wafer is held on a rotating holder as shown in Figure 36.2 The surface of the wafer being polished is pressed against the polishing pad (i.e., a resilient material), which is mounted on a rotating disk In addition, a slurry composed of particles suspended in a chemical solution is deposited on the pad as the chemical abrasive
The material removal mechanism of silicon dioxide (oxide) CMP is similar to the removal found
in glass polishing First, a chemical reaction softens the deposited film surface, then a mechani-cal surface abrasion aided by slurry particles removes the material [15,36] The chemimechani-cal reaction between the slurry and the surface of the wafer creates a -form material The new material has weaker atomic bonds It is therefore more easily removed during the polishing process [45] The second step involves the removal of the weakened film surface through abrasion The actual wear mechanism is not well understood There is speculation that a fluid layer exerts the force necessary to remove the film surface [56] Others speculate that the removal of the film surface is due to a complex interac-tion of particle, fluid, and pad [16] In either case, the abrasion removal mechanism is a dynamic process that depends on surface characteristics of the pad and slurry particles, although the exact contributions of these factors are not known [36]
Compared with conventional planarization methods, CMP offers a more deterministic behavior and does not incur extra processing cost such as extra masking steps However, CMP has its own drawback which is its dependence on layout pattern density This dependency causes variations in
Trang 8Conditioning head is not shown
Polish pad Slurry Slurry feed
Wafer carrier
FIGURE 36.2 Typical CMP tool (From Lee, B., Modeling for chemical–mechanical polishing for
shal-low trench isolation, Ph.D Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002)
post-CMP layout parameters (i.e., variations in interlayer dielectric [ILD] thickness, metal height, etc.), which in turn impact circuit performance In Section 36.2, the impact of the CMP process on interconnect design is reviewed
Major planarization defects are caused by the pattern dependency of the CMP process Among the significant defects are metal dishing and dielectric erosion, which account for approximately
50 percent of yield loss in IC fabrication processes In Section 36.2, these defects are introduced and their impact on interconnect design is reviewed Section 36.3 discusses several traditional as well as recent work on oxide (dielectric), copper, and shallow trench isolation (STI) CMP characterization and modeling approaches To increase predictability, the layout pattern density variation must be kept
to a minimum A current solution is to insert dummy metal shapes (CMP fill features) in the layout
to decrease the density variation Different density analysis methods are reviewed in Section 36.4 In Section 36.5 the problem of how to insert the required amount of CMP fill after calculating density
is discussed Section 36.6 reviews the parts of design flow that are affected by CMP fill insertion Finally, the conclusion is presented in Section 36.7
36.2 IMPACTS ON INTERCONNECT DESIGN AND MANUFACTURING
In the very deep-submicron VLSI regime manufacturing steps including optical exposure, resist development, and etch, and CMP have varying effects on device and interconnect features depending
on local properties of the layout Foundry economics dictate that the process window volumes be maximized, which in turn requires that device and interconnect features be fabricated as predictably and uniformly as possible To achieve this goal, the layout must be made uniform with respect to a certain density parameter The physics of semiconductor processing make predictable and uniform manufacturing difficult [7,18,35,55] In particular, the quality of post-CMP depends on the pattern density of the layer beneath a given dielectric layer
The layout pattern density is one of the dominant factors in determining the post-CMP thickness profile of the deposited film [6,9,48,63] Pattern density can be defined as the fraction of the raised areas that affect the CMP process at a particular region on the layout Figure 36.3 illustrates the concept of pattern density in one-dimensional and two-dimensional cases Intuitively, the higher the pattern density the larger the contact area with the pad and the lower the pressure on raised features High-density regions are polished more slowly than low-density regions resulting in locally planar but globally nonplanar regions [36]
Trang 9Deposited film
Density ~50 percent
Density ~25 percent
Layout feature
Top–down view of layout
Underlying metal Cross section of layer
FIGURE 36.3 Pattern density in one and two dimensions (From Lee, B., Modeling for chemical–mechanical
polishing for shallow trench isolation, Ph.D Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.)
In the past decade, CMP has emerged as the predominant planarization technique for multilevel metallization processes However, significant surface topography variation can still exist for some layout patterns; this impacts depth of focus in lithography which in turn leads to variations in critical dimension (CD) Two other major defects caused by CMP are metal dishing and oxide erosion In the copper CMP process, metal dishing is defined as the difference between the height of the oxide
in the spaces and that of the metal in the trenches Oxide erosion is defined as the difference between the oxide thickness before and after CMP [69] In this chapter, dishing and erosion refer to metal dishing and oxide erosion, respectively Figure 36.4 shows metal dishing and oxide erosion in copper CMP process These two phenomena impact the performance of the circuit because variation in ILD thickness profile and interconnect height lead to variations in interconnect capacitance and resistance This variation will increase the timing uncertainty of the circuit, hence it is crucial to minimize dishing and erosion However, due to CMP nonidealities there will always be some amount of dishing and erosion It is important to model the effect of these variations during parasitic extraction to obtain a more accurate estimation of the circuit performance [54]
Even though pattern density is the major cause of the CMP defects, there are other factors such
as slurry flow rate and pad conditioning temperature that contribute to the amount of dishing and erosion The slurry acts as a coolant material at the interface of the pad and wafer contact and takes away a significant part of the heat through convective heat transfer [42,59,60,72] The dissipated heat changes the chemical kinetics and the physical properties of the polishing pad [42,59] As the amount
of dissipated heat increases, the polishing pad tends to become softer that results in an increase in
Oxide erosion
Copper dishing
Cu Cu
SiO2
FIGURE 36.4 Dishing and erosion in copper CMP process (From Tugbawa, T., Chip-Scale modeling of
pattern dependencies in copper chemical mechanical polishing processes, Ph.D Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.)
Trang 10the area contact at the interface In addition, pad conditioning has a major impact on the removal rate (RR) during the CMP process, as underconditioned pads will lose their surface roughness, which eventually leads into RR reduction [43] For more details on effects of slurry flow rate and pad conditioning temperature on metal dishing and dielectric erosion reader is encouraged to look into Ref [43]
To increase the fabrication process uniformity and predictability, the layout must be made uni-form with respect to a certain density parameter One solution for designers and manufacturers is to use techniques like CMP fill insertion and slotting to increase and decrease the pattern density [26] CMP fills are dummy features that do not directly contribute to the functionality of the circuit and can either be grounded or left floating CMP fill insertion reduces the amount of dishing and erosion
by increasing the pattern density uniformity However, it is well known that CMP fill insertion can increase the coupling and total interconnect capacitance and consequently deteriorate circuit perfor-mance [38,62] If not modeled appropriately, this can directly affect yield and time-to-market In the next section, characterization and modeling approaches of different CMP processes are represented
36.3 CHARACTERIZATION AND MODELING APPROACHES
This section, first presents a number of early works on CMP modeling which have been reviewed in Ref [45] and then introduces three recent works [36,47,68] on CMP characterization and modeling
of oxide CMP, copper CMP, and STI CMP
36.3.1 GENERALCMP PROCESSMODELS
The combination of the chemical and mechanical aspects of CMP makes it a complex process
to model based on physical principles Typical characterization of a CMP process requires exten-sive experimentation that must be repeated for each particular CMP process (combination of tool, consumable, and process settings) The main objective of CMP is to remove the extraneous material from the surface of the wafer and planarize it The process of material removal can be described by Preston’s equation:
dT
dt = KP ds
where
T is thickness of the wafer
P denotes the pressure caused by polishing process
s is the total distance traveled by the wafer
t is the elapsed time
The RR is proportional to the pressure exerted on the wafer as well as the speed in which the
wafer is rotating Any other physical considerations are put into the constant K, which is independent
of pressure and velocity In this subsection, a few CMP models are introduced and their advantages and disadvantages are reviewed [45]
The first model is based on works by Sivaram et al [57] The proposed model uses Preston’s equation and considers the bending of the polishing pad The bending of the polishing pad has
a significant impact on the quality of the planarization and must be modeled in RR expression However, this model only considers the effects of bending between two neighboring step heights on the wafer It does not take into account the three-dimensional information of the structures, which limits its applicability
The next model proposed by the authors of Ref [6] depends on the degree of nonplanarity The model has two parts: an analytical expression based on an ordinary differential equation and a more complex model which iteratively adjusts the polishing rate to the actual nonplanarity Even though