Handbook of algorithms for physical design automation part 78 doc

Flat-fill cleanup phase i.e., LP, Monte-Carlo, etc., which will fill any remaining sparse or underfilled regions that were not satisfactorily processed during the first two phases 36.5.1

Minimize ε

subject to

0≤ p(T ij ) ≤ slack(T ij )

M−ε

2 ≤ ρ(T ij ) ≤ M + ε

2i, j = 1, , nr

w − 1 The above formulation is also called a ranged LP formulation where the manufacturability is guaranteed by the constraints

In addition to the LP approaches, Ref [14] introduces the Monte-Carlo method for min-variation objective In the Monte-Carlo approach, a tile is chosen randomly and its content is increment with

a predetermined fill amount Tiles are chosen based on their priority, which is the probability of

choosing a particular tile T ij The priority of a tile T ij is zero if and only if either T ij belongs to

a window that has already achieved the density upper bound U, or the slack of T ij is equal to the

already-inserted fill area As described in Ref [14], the priority of a tile T ijis chosen to be proportional

to U – MinWin(T ij ), where MinWin(T ij) is the minimum density over windows containing the tile

T ij The only drawback of the Monte-Carlo method is that it may insert an excessive amount of total fill A variant of the Monte-Carlo approach is the greedy algorithm At each step, the min-variation greedy algorithm adds the maximum possible amount of fill into a tile with the highest priority, which causes the priority of that particular tile to become zero

In the presence of two objectives, namely min-variation and min-fill, the intuitive approach would

be to first find a solution that optimizes one of the objectives then modifying the solution with respect

to the other objective Min-fill objective tries to delete as much previously inserted fill as possible, while maintaining the density criteria

To optimize the min-fill objective problem with the Monte-Carlo approach, a filling geometry from a tile randomly chosen according to a particular priority is iteratively deleted Priorities are chosen symmetrical to the priority in the min-variation Monte-Carlo algorithm, that is, proportional

to MinWin(T ij ) − L Again, symmetrically no filling geometry can be deleted from the tile T ij(i.e.,

T ij is locked) if and only if it either has zero priority or else all fill previously inserted into T ijhave been deleted Thus, the min-fill Monte-Carlo algorithm deletes fill geometries from unlocked tiles, which are randomly chosen according to the above priority scheme Similarly, the min-fill greedy algorithm iteratively deletes a filling geometry from an unlocked tile with the current highest priority

A variant of the Monte-Carlo approach is the deterministic greedy algorithm where at each step the greedy min-variation algorithm adds the maximum possible amount of fill into a tile with the highest priority The runtime for this approach is slightly higher than Monte-Carlo because of finding highest-priority tile rather than random ones [12]

36.5.1.2 Iterated Monte-Carlo and Hierarchical Methods

Monte-Carlo and greedy approaches are both suboptimal for the min-variation objective resulting in a minimum window density that may be significantly lower than the optimum Reference [12] proposes

a new iterative technique alternating between the min-variation and min-fill objectives, to narrow

the gap between the upper window density bound U and the minimum window density bound L.

As described in Ref [12] the iterated Monte-Carlo and greedy filling algorithms are modified as follows:

1 Interrupt the filling process as soon as the lower bound L on window density is reached, that is, when M = L, instead of improving the minimum window density (while possible)

for the min-variation objective

2 Continue iterating, but without changing the lower density bound M = L An improved

solution can typically be obtained by keeping track of the best solution oserved over all iterations

All the filling methods mentioned above were proposed for flat designs; however, the filling problem for hierarchical layouts (standard-cell) is similar to the one for flat layouts The constraints for the hierarchical filling problem as described by the authors in Ref [13] are as follows:

• Filling geometries are added to master cells

• Each cell in a filled layout is a filled version of the original master cell

• Layout data volume should not exceed a given threshold

The proposed method by the authors in Ref [13] first computes the slack value for all the master cells Then a keep-off zone around master cells will be created to avoid overfilling the regions near master cell boundaries Then master cells are filled using a Monte-Carlo method where master cells that are more underfilled will be assigned a higher priority This process is continued until either all the master cells are filled above their minimum density lower bound or the slack in the underfilled master cells becomes zero

However, due to overlaps between different instances of master cells and features or the inter-actions among the bloat regions in the vicinity of the master cells, pure hierarchical filling may result in some sparse or unfilled regions This could result in high layout density variation An intu-itive solution would be to apply a postprocessing phase, that is, apply a standard flat fill approach However, this will greatly increase the resultant data volume and runtime and diminish the benefit

of the hierarchical approach Reference [13] proposes a three-phase hybrid hierarchical flat-filling approach as follows:

1 Purely hierarchical phase

2 Split-hierarchical phase, where certain master cells that were considered underfilled in phase 1 would be replicated so that distinct copies of a master cell may be filled differently than other copies of the same master cell

3 Flat-fill cleanup phase (i.e., LP, Monte-Carlo, etc.), which will fill any remaining sparse or underfilled regions that were not satisfactorily processed during the first two phases

36.5.1.3 Timing-Driven Fill Synthesis

One of the largest concerns in fill synthesis, apart from meeting the CMP design rules, is the impact

of fill insertion on the interconnect capacitance An excessive increase in wire capacitance can cause a net to violate its setup timing constraint A large value for keep-off distance (i.e., minimum distance from fill to wire) reduces the impact but it erodes into available areas to insert fills and sometimes makes it impossible to meet the minimum density constraint Reference [11] proposes the first formulation of the performance impact limited fill (PIL-Fill) problem with the objective of either minimizing total delay impact or maximizing the minimum slack of all nets, subject to a given predetermined amount of fill They also developed simple capacitance models to be used in their delay calculations The PIL-Fill synthesis formulation has two objectives:

• Minimizing layout density variation

• Minimizing the CMP fill features’ impact on circuit performance (e.g., signal delay and timing slack)

Because it is difficult to satisfy both the objectives simultaneously, practical approaches tend to optimize one objective while transforming the other into constraints Using the terminology in Ref [11], the two problem formulations proposed are as follows (note that these formulations are for fixed-dissection regimes):

1 Given tile T , a prescribed amount of fill is to be added into T , a size for each fill feature, a set of slack sites (i.e., sites available for fill insertion) in T per the design rules for floating

square fill, and the direction of current flow and the per-unit length resistance for each

interconnect segment in T , insert fill features into T such that total impact on delay is

minimized

2 Given a fixed-dissection routed layout and the design rule for floating square fill features, insert a predetermined amount of fill in each tile such that the minimum slack over all nets

in the layout is maximized

The first formulation corresponds to minimum delay with fill constrained formulation while the second one is the maximum min-slack with fill constrained formulation A weakness with the first formulation is that it minimizes the total delay impact independently for each tile Hence, the impact due to fill features on signal delay of the complete timing path is not considered The second formulation, therefore has been proposed to alleviate this problem by maximizing the minimum slack

of all nets, subject to a constraint of inserting a predetermined amount of fill in every tile of the layout Reference [11] proposes two integer linear programming (ILP) methods and a greedy approach for the minimum delay and maximum min-slack formulations, respectively However, the capacitance models used in delay calculations of Ref [10] are not accurate as they do not consider the presence

of fill features on the neighboring layers This incurs inaccuracy in the estimated capacitance values and eventually causes uncertainty in the timing analysis Also, they do not account for signal flow direction, which causes layout nonuniformity (i.e., as fills are pushed to the receiver edge, the driver edge becomes less dense)

In addition to the timing-driven fill synthesis, recently an auxiliary objective-driven fill synthesis has been introduced by the authors in Ref [41] In this work, in addition to meeting the layout pattern density criteria, the IR-drop of the power distribution network is also reduced IR-drop is an increasing challenge in 90 nm (and beyond) designs The tolerance for IR-drop is becoming smaller

as the voltage source scales It also adds excess burden on routing resources The work by Leung

et al [41] addresses these issues and according to their experimental results achieves an average IR-drop reduction of 62.2 percent

36.5.2 MODEL-BASEDFILLSYNTHESIS

Methods for fill insertion can be categorized into two groups: rule-based and model-based Rule-based fill insertion is usually performed by Boolean operations considering design rule constraints such as minimum fill-to-fill spacing, and minimum fill-to-wire spacing (keep-off distance) On the other hand, the model-based fill insertion approach is based on analytical expressions that define the relationship between local pattern density and ILD thickness Figure 36.15 shows possible rule- and model-based fill insertion approaches

The model-based fill insertion approach, given a CMP process model, is to find the amount and the location of the fill features to be inserted in the layout so that certain electrical and physical design rules are preserved and certain post-CMP topography variation is met Reference [65] proposes a two-step solution with consideration of both single- and multiple-layer layouts in the fixed-dissection regime The first step uses linear programming to compute the necessary amount of fill to be inserted

in each of the dissection’s tiles In the second step, the amount of fill calculated by the first step will

be placed into each tile such that certain local properties (i.e., electrical, physical, etc.) are preserved Experimental results with the single-layer formulation (i.e., the cumulative variation of underlying layers is ignored) show reduction of post-CMP topography variation from 767 to 152 Å

36.5.3 IMPACT OFCMP FILL ONINTERCONNECTPERFORMANCE

In this subsection, the impacts of CMP fill on both interconnect resistance and capacitance have been reviewed CMP fill insertion can change both coupling and total capacitance of interconnect In

(a) (b)

FIGURE 36.15 (a) Example layout with features lightly shaded and exclusion zone in dashed lines.

(b) Twenty-five percent density fill insertion before Boolean operations (c) Rule-based fill insertion after the application of the Boolean operations (d) Possible model-based fill insertion (Tian, R., Wong, D.F., and

Boone, R., Proceedings of ACM/IEEE Design Automation Conference, 2000.)

addition, metal dishing and dielectric erosion change interconnect cross section and therefore affect interconnect resistance He et al [23] report an increase of more than 30 percent in interconnect resistance due to dishing and erosion, while the impact on interconnect capacitance is insignificant Reference [24] proposes a wire sizing approach to lessen the amount of interconnect resistance variation due to the CMP process Increased wire size compensates for the increased resistance caused

by dishing and erosion and also reduces the effect of the large Reff (i.e., driver output resistance) variation on delay

36.5.3.1 Fill Patterns

CMP fill insertion, even as it contributes to layout pattern density uniformity, increases the coupling and total interconnect capacitance Therefore, it is important to assess the impact of CMP fill on inter-connect capacitance to reduce the uncertainty in circuit timing calculations Reference [22] explores

a space of different fill patterns that are equivalent from the foundry perspective (i.e., respecting all the minimum design rules, etc.) and their respective impact on interconnect capacitance All the fill features are assumed to be rectangular, and are aligned horizontally and vertically as shown in Figure 36.16 Using the notation from Ref [22], conductors A and B are active interconnects and the metal shapes between them are CMP fills Each distinct fill pattern is specified by (1) the number of

fill rows (M) and columns (N); (2) the series of widths {W i}i=1 N and lengths{L j}j=1 M of fills; and (3) the series of horizontal and vertical spacings,{S x,i}i =1 N−1and{S y,j}j =1 M−1between fills Enumeration of all the possible combinations of the above parameters is not feasible Therefore,

to restrict the space of exploration, Ref [22] proposes a positive distribution characteristic function

(DCF), denoted f (k), where k is an integer variable that takes the index of the element in the series.

A A

X

A B

S x, 2

S x, 1

A

(d)

S y, 4

S y, 3

S y, 2

S y, 1

FIGURE 36.16 Examples of fill pattern (a) Traditional fill pattern, (b) fill with different length and spacing, (c)

fill with different width and spacing, and (d) fill with different length, width and spacing (L He, Kahng, A B.,

Tam, T H., and Xiong, J., Proceedings of International VLSI/ULSI Multilevel Interconnection Conference,

2004.)

For example, the value of the ith element of the width is calculated as W i = f (i) +  W l, where W lis the minimum width design rule Figure 36.17 shows an example of three different DCFs for width Reference [22] uses combinations of different DCFs for the parameters mentioned On the basis of the results of the experiments, Ref [22] proposes two guidelines as to what a “good” fill pattern might be among all the possible valid fill pattern combinations The criteria for this assessment are based on the impact of the pattern on interconnect capacitance According to these guidelines

• In a fixed length budget, the number of fill columns should be maximized

• In a fixed width budget, the number of fill rows should be minimized

In addition to the parameters covered in the previous experiments, Ref [20] adds four more parameters in its space of exploration These parameters are, metal width, metal height, dielectric constant, and keep-off distance The trend of changes in interconnect capacitance were observed for the corresponding parameters A recent work by Kahng et al [30] systematically studies the impact

of various floating fill configuration parameters, such as fill size, fill location, interconnect size, separation from interconnect edges, multiple fill columns and rows, etc., on coupling capacitance

On the basis of their studies, Ref [30] proposes certain guidelines for fill insertion to reduce their impact on coupling capacitance while achieving the prescribed metal density The following are the proposed guidelines in order of decreasing importance:

1 High-impact region Fill insertion impacts the coupling capacitance most in the area between the two overlapping interconnects and in a close proximity to it

2 Edge effects Fill insertion should be preferred at the edges of the above region

3 Wire spacing Impact on coupling capacitance is smaller if spacing between the two interconnects is large Hence, fill must be inserted where spacing is large

Z

FIGURE 36.17 Examples of DCFs and their corresponding geometrical interpretation (a) f (z) is a constant,

(b) f (z) is nearly increasing, and (c) f (z) is a triangular function (L He, Kahng, A B., Tam, T H., and

Xiong, J., Proceedings of International VLSI/ULSI Multilevel Interconnection Conference, 2004.)

D B C

(a)

D B

A

C (b)

FIGURE 36.18 (a) Regular fill pattern and (b) fill insertion with guidelines.

4 Wire width Large-width wires are more susceptible to increase in capacitance due to fill insertion Thinner wire must be preferred as neighbors of fill

5 Maximize columns The number of columns should be maximized That is, fill must be split up subject to the minimum size design rules in a column and spread evenly between the two interconnects

6 Minimize rows Fill rows may be merged to reduce the coupling capacitance

7 Increase length not width Increasing fill length must be preferred to increasing width to attain the same fill area

8 Centralize fill Fill or fill configurations when centered between the two interconnects have

a smaller impact on the increase in coupling capacitance

Figure 36.18 shows an application of the proposed guidelines for a represented fill/wire config-uration In this configuration Guidelines 1, 2, 3, 6, and 8 have been utilized Increase in coupling capacitance is 27 percent and 11 percent when fill is inserted in a regular pattern and with the proposed guidelines respectively Reference [30] reports that on average 53 percent reduction in coupling capacitance increase is achieved through applying the guidelines for fill insertion

36.5.3.2 CMP Fill and Interconnect Capacitance

CMP fill features despite their role in uniforming layout pattern density have a significant impact

on coupling and total interconnect capacitance There is a body work that addresses different issues regarding the estimation or optimization of the capacitance impact of the CMP fill

Reference [50] briefly described a model-library-based approach to extract floating-fill Results demonstrating the accuracy of the approach and characterization time were, however, not presented Reference [40] presented a methodology for full-chip extraction of total capacitance in presence

of floating-fill and Ref [39] extended their analysis Their approach adjusts the permittivity and sidewall thickness of dielectric to account for the capacitance increase due to fill According to Ref [34] capacitance of a configuration is directly proportional to the charge accumulated on one of the electrodes(Q = CV) The charge density on an electrode depends on the electric field close to the

electrode(E = σ/A) Therefore, the electric field close to an electrode determines the capacitance

of a configuration When a floating plate of thickness t (t < d) and the same size as the conductor

plates is inserted in the space between the conductors, the capacitance increases toεA/(d − t).

Also, Ref [1] has proposed an extraction methodology, where fills are eliminated one by one using a graph-based random walk algorithm while updating the coupling capacitances In this method,

a network of capacitors is collapsed into the equivalent capacitance between two nets In addition,

Yu et al [75] propose enhancements to the current field solvers by taking into account floating fills and their conditions in the direct boundary element equations The basic idea in their approach is

to add additional equations about the floating CMP fill features to generate a solvable system of linear equations In the conventional approach, the field solver is called as many times as the number

of conductors and floating fill features, whereas in the proposed method the field solver is only called as many times as the number of conductors Hence, the proposed method has reduced the computation runtime of the field solving process compared to traditional methods Reference [8] presents a charge-based capacitance measurement methodology to analyze the impact of fills And finally Ref [33] proposes three techniques of fill insertion to reduce the interconnect capacitance and the number of fills inserted It also provides an estimation of the required number of fill geometries for each of the proposed techniques However, it fails to report the accuracy and reliability of the methods and estimations for densities greater than 30 percent

36.5.4 STI FILLINSERTION

Shallow trench isolation is the isolation technique of choice for IC manufacturing designs STI is used to created trenches in silicon substrate between regions that must be isolated Today’s STI processes involve many steps of which nitride deposition, oxide deposition, and CMP are of interest Nitride is deposited on silicon to protect the underlying regions and to act as a polish stop (i.e., in overburden oxide removal stage) In the next stage, oxide is deposited to fill in the trenches and cover the nitride regions by means of chemical vapor deposition (CVD) CMP is required to remove the overburden oxide over the nitride and in the trenches to ensure the planarity

In STI, the oxide is polished until all the deposited oxide over the nitride regions have been removed However, due to the pattern-dependent nature of CMP, the planarization is imperfect as shown in Figure 36.19 Depending on the underlying pattern density, different regions have different polish rates causing oxide thickness variation which results in functional and parametric yield loss

Oxide Nitride

Si

FIGURE 36.19 Cross section of silicon substrate with nitride and oxide being deposited (From Kahng,

A B., Sharma, P., and Zelikovsky, A., Proceedings of IEEE International Conference on Computer-Aided

Design, 2006.)

Si Oxide

FIGURE 36.20 Desired planarization profile after CMP (From Kahng, A B., Sharma, P., and Zelikovsky, A.,

Proceedings of IEEE International Conference on Computer-Aided Design, 2006.)

Figure 36.20 shows an ideal planarization case after CMP process where there is no nitride erosion

or oxide dishing

In STI CMP, the planarization quality depends on pattern densities of both nitride and oxide Because the oxide is deposited over the nitride, the oxide density is dependent on nitride pattern density Owing to the variation in underlying nitride pattern density, three key failures may occur after STI CMP process First, the CMP process may fail to completely remove the excess oxide Second, even if it does remove the excess oxide completely, it may cause erosion of the underlying nitride Third and finally, it may remove an excessive amount of oxide within the trenches causing oxide dishing [4] If the overburden oxide is not completely removed, it will prevent the stripping

of the underlying nitride resulting in a circuit failure Nitride erosion exposes the underlying active devices and causes device failure On the other hand, oxide dishing results in poor isolation These failures due to the CMP process have been shown in Figure 36.21 Traditionally, CMP imperfections have been addressed by reverse etchback and fill insertion However, the etchback process incurs extra processing cost (i.e., mask cost and others) and hence is not economically desirable Fill insertion for STI is the other technique that involves the addition of dummy nitride features to increase the nitride (and hence oxide) density

The postplanarization topography in STI CMP is dependent on the overburden oxide den-sity, which is affected by the underlying nitride density Due to the high density plasma (HDP) process, which is used widely as the oxide deposition technology, the deposited oxide exhibits an interesting property (i.e., slanted sidewalls) Hence, features on the oxide layer are a shrunk version

of the nitride features [2,49,73] For example, a square feature on the nitride layer with sides of five times will have sides of three when deposited on the oxide layer Therefore, features with sides less than two times will not appear on the oxide layer As mentioned earlier, the density of the oxide is dependent on the underlying nitride density Therefore, fill is inserted in the nitride layer to control the densities of both nitride and oxide layers

FIGURE 36.21 Three main defects caused by CMP process (From Kahng, A B., Sharma, P., and

Zelikovsky, A., Proceedings of IEEE International Conference on Computer-Aided Design, 2006.)

Failure to remove the overburden oxide completely is the main cause of failure in the oxide CMP process This phenomenon happens over the regions where oxide density is higher than average In higher density regions, the CMP pad pressure is reduced and hence the RR is less than that of the regions with lower density [47] Oxide dishing and nitride erosion can be significantly reduced by increasing the nitride density In fact, because nitride is used as a polish stop, higher nitride density makes the detection of the nitride more accurate In a recent work, Kahng et al [31] propose a new fill insertion methodology for STI CMP processes In the problem formulation they propose the following fill insertion objectives in the order of their priority:

• Minimize oxide density variation

• Maximize nitride density

Correspondingly, a bicriteria problem formulation was introduced by Ref [31] as follows

Given:

• Set of rectilinear nitride regions contributed by the devices in the design

• Parameterα by which nitride features shrink on each side to give oxide features

• Design rules: minimum nitride width, maximum nitride width, minimum nitride space and notch, minimum nitride area, and minimum enclosed area by nitride

Find:

• Locations for fill insertion

Such that:

1 Oxide density variation is minimized

2 Nitride density is maximized

For the first objective, Ref [31] uses the same LP formulation proposed in Ref [29], as mentioned

in Section 36.4 The fill slack in the STI method is the maximum oxide density due to fill insertion and the maximum contribution is made by maximum fill insertion on the nitride layer Using the terminology of Ref [31], the maximum fill region, the union of all regions where fill can be inserted subject to design rule constraints, is denoted by Nitridemaxand its density is denoted as|Nitridemax| The proposed procedure for finding the region Nitridemaxis shown in Figure 36.22

Maximum oxide density could be achieved by shrinking Nitridemax by x on all sides for any

polygon To address the second objective of the bicriteria formulation, Ref [31] introduces|Oxidemax|

to denote the oxide density due to Nitridemax, which is highest oxide density achievable by fill insertion Experimental results show that using the proposed method, averaged over two testcases, the oxide density variation is reduced by 63 percent and minimum nitride density is increased by

79 percent compared with tiling-based fill insertion Also, the quality of post-CMP topography is improved as the maximum final step height is reduced by 9 percent with only 17 percent increase in the planarization window [31]

36.6 DESIGN FLOWS FOR FILL SYNTHESIS

The impact of CMP-induced variations on yield and performance can be controlled by inserting CMP fill features When it comes to CMP fill insertion, there are two different hypotheses The first hypothesis is that the fill synthesis and timing should be closed inside the detailed router This might sound like an intuitive solution due to the following:

Nitride STI (a)

Min spacing rule-correct fill regions (b)

Region for fill (Nitridemax)

Width too small (c)

FIGURE 36.22 Computation of maximum fill region (Nitridemax) (a) Unfilled layout (b) Possible regions for fill insertion (c) Spaces of small width and area (shown in the lightest shade of gray) are not available for

fill (From Kahng, A B., Sharma, P., and Zelikovsky, A., Proceedings of IEEE International Conference on

Computer-Aided Design, 2006.)

• Routers lay down geometries and close timing, and so they are the natural candidate to perform fill synthesis

• Timing closure will be more certain for the design team before hand off to manufacturing

• Multi-grounded fill, which reduces timing uncertainty and improves IR drop, is a natural extension of power/ground routing capability

The other hypothesis suggests that the router should not perform the fill insertion due to the following:

• Complicated density analyses that support high-quality CMP modeling are not easily performed by the router (wrap-around, full-chip, width-distribution dependent, etc.)

• Routers cannot deliver high-quality fill without a runtime hit

• With the possible exception of hold time slack and coupling-induced delay uncertainty issues, grounded fill is a bad idea from a performance standpoint (there are some verification and planning closure issues as well) Floating fill synthesis is preferable, but is unnatural for a router

• Foundries want to own more and more of the RET (reticle enhancement technique), includ-ing CMP fill, because RET exposes the process Extraction, coverage, and fill pattern rules provide a huge amount of leverage, to avoid any need for solving fill in the router

• Better passing of design intent from design to manufacturing can reduce the need to solve the problem in the router as mentioned in Ref [11]

36.6.1 RC EXTRACTION ANDTIMINGCLOSURE

CMP fill insertion must not compromise the sign-off timing and signal integrity However, it has been shown that CMP fill insertion will adversely impact the interconnect capacitance and therefore the signal delay [22] Gupta et al [10,11] propose CMP fill insertion approaches aimed at minimizing the impact of the fill features on the circuit performance Their method has two objectives, minimizing the layout density variation, and minimizing the CMP fill features’ impact on circuit performance (i.e., signal delay and timing slack) Practical approaches tend to find an optimized solution for one objective and then the solution will be adjusted to satisfy the other objective while preserving the first constraint The PIL-Fill approach discussed in Section 36.5.1.3 can reduce the negative timing slack impact of floating fill by more than 80 percent [11]