Handbook of algorithms for physical design automation part 70 pptx

The voltage on the victim Aggressor net Victim net VA Cc Cg ta VB VA Rh A B V t FIGURE 34.2 a Circuit and b waveforms of capacitive coupling noise injection... A formula for the height o

Journal of Algorithms, 9:114–128, 1988.

33 P Saxena, N Menezes, P Cocchini, and D Kirkpatrick Repeater scaling and its impact on CAD

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(4):451–463, 2004

(ISPD 2003)

34 C E Radke A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios

In Proceedings of ACM/IEEE Design Automation Conference, pp 257–267, 1969.

35 B Landman and R Russo On a pin versus block relationship for partitioning of logic graphs IEEE Transactions on Computers, C-20:1469–1479, December 1971.

36 P H Madden SuperSized VLSI: A recipe for disaster In Proceedings of Electronic Design Processes Workshop, Monterey, CA, 2005.

34 Coupling Noise

Rajendran Panda, Vladimir Zolotov,

and Murat Becer

CONTENTS

34.1 Coupling Noise Phenomenon 674

34.1.1 Interconnect Capacitance 674

34.1.2 Coupling Noise Injection 675

34.2 Noise Analysis 676

34.2.1 Noise Calculation 676

34.2.2 Failure Criteria 679

34.3 Simplifying Models and Analysis 681

34.3.1 Simplification of Models 681

34.3.1.1 Aggressor Driver Model 681

34.3.1.2 Quiet Victim Model (for Functional Noise) 681

34.3.1.3 Switching Victim Driver Model (for Delay Noise) 682

34.3.1.4 Receiver Characterization 683

34.3.2 Conservative Filtering of Nonrisky Nets 683

34.4 Reducing Pessimism in Crosstalk Noise Analysis 684

34.4.1 Logic Correlation 685

34.4.2 Switching (Timing) Windows 687

34.5 Noise Avoidance, Noise-Aware Design, and Noise Repair 688

34.5.1 Noise Prevention and Noise-Aware Design 688

34.5.1.1 Slew Control 688

34.5.1.2 Congestion Minimization 689

34.5.1.3 Noise-Aware Routing (Spacing, Shielding, Layer Assignment) 689

34.5.2 Postroute Noise Repair 689

34.5.2.1 Gate Sizing, Buffer Insertion 689

References 690

As a result of the scaling of physical geometries of wires and devices to ultra-deep submicron (UDSM) dimensions, signal integrity has become, in addition to area, timing, and power, an impor-tant design challenge Although signal integrity problems can arise from many sources, such as capacitive coupling between signal wires, inductive and substrate coupling, power supply variation, degradation of devices and interconnect, and leakage current, capacitive coupling is the single major source of noise in current technologies In UDSM technologies, its contribution has grown to be a major fraction, as much as 60–70 percent, of the total wiring capacitance Depending on the signal levels on the coupled wires, this capacitance can speed up or slow down switching, and introduce signal-dependent variations in the delays The domination of wire delays over gate delays in these technologies has the effect of making a significant part of the circuit delay susceptible to wide vari-ation because of capacitive coupling As a result, delay varivari-ation effects of coupling noise must be

673

also cause functional failures, increase power consumption, and accelerate degradation of devices For these reasons, physical design and circuit design must seriously consider coupling noise issues Serious noise issues, if not caught and fixed early, may require significant design modifications at very late design stages and impact adversely the design completion schedule Because noise analysis and repair cost significant time and resources, noise avoidance techniques should be embraced at all design stages

In this chapter, we look at the coupling noise phenomenon, noise analysis, and some of the criteria for determining noise failures We then present modeling and analysis techniques suitable for efficient noise analysis at the global routing, detailed routing, and postrouting stages Techniques for reducing pessimism in noise analysis are also provided in some detail Finally, noise avoidance, noise-aware physical and circuit design, and noise repair are discussed

34.1 COUPLING NOISE PHENOMENON

Coupling noise can be broadly defined as distortion of a signal by other signals The net with the distorted signal is usually called a victim net, and the nets affecting a victim net are called aggressor nets The victim net and its aggressor nets collectively form a noise cluster In real circuits, coupling

noise is a bidirectional phenomenon: if net A injects noise into net B, then net B injects some noise into net A too However, this symmetrical consideration of coupling noise [1] is not very popular in very

large scale integration (VLSI) design, except during a full SPICE-level circuit simulation, because it complicates the analysis Asymmetrical consideration of coupling noise significantly simplifies the analysis but may have lower accuracy

A noise event occurs when a victim net is electrically coupled with an aggressor net Capacitive coupling is the most important cause of coupling noise in VLSI interconnects There are several reasons for the strong effect of capacitive coupling in UDSM technologies Complementary metal oxide semiconductor (CMOS) transistors have a very high input gate resistance and a small gate capacitance, as compared to the coupling capacitance of interconnects With technology scaling, the minimum spacing between wires is decreased while the ratio of thickness to width of wires

is increased (to control wire resistance) The net result of this is that, in successive technology generations, the wire coupling capacitance increases relative to the wire capacitance to ground Moreover, strict constraints on power dissipation require the use of small drivers with rather high output resistance, which accentuates the contribution of the coupling capacitance to the total delay All these factors exacerbate coupling noise injection

34.1.1 INTERCONNECTCAPACITANCE

The total wire capacitance consists of grounded and coupling capacitances, as shown in Figure 34.1 The grounded capacitance results from several sources First, an important component of the grounded capacitance is wire capacitance to orthogonal wiring on upper and lower metal layers The coupling capacitance to each of the orthogonal wires is quite small and although these wires may switch at different time moments in different directions, the total noise injected by these wires is close to zero Therefore, the capacitance to orthogonal wires is considered as grounded capacitance Second, if the wire is on the lowest metal layer, its grounded capacitance includes also coupling capacitance to the substrate Third, the coupling capacitance between a wire and the power and ground distribution networks on the same or different layers contributes to the grounded capaci-tance The coupling capacitance of a wire is usually the sidewall capacitance to other (nonsupply) wires in the same metal layer This capacitance can be high compared to the capacitance to the other metal layers, because wires in modern chips are rather tall and narrow

Although detailed capacitance extraction involves a three-dimensional field solver, for the pur-poses of analyzing large networks of interconnects, it is sufficient to use much simpler models The

Coupling capacitance to

Grounded capacitance Coupling capacitance

Orthogonal wiring

FIGURE 34.1 Coupling and grounded capacitances of interconnect wires.

coupling capacitance between two parallel wires is approximately proportional to the height of the wires and the distance that they run parallel to each other, and inversely proportional to the spacing between the wires On the other hand, the grounded capacitance of a wire is proportional to the wire length and wire width, and inversely proportional to the thickness of the interlayer dielectric

34.1.2 COUPLINGNOISEINJECTION

The injection of capacitive coupling noise is illustrated on a simple model, as shown in Figure 34.2a

Here, the aggressor net transitions from zero voltage to Vdd during time ta The resistance Rhmodeling

the driver of the victim net is trying to hold the victim net at zero potential The capacitance Cg is

the total grounded capacitance of the victim net, and the capacitance Ccis the coupling capacitance between the victim and aggressor nets When the aggressor transitions, it increases voltage on one

terminal of the coupling capacitance Cc, which increases the voltage on the other terminal of Cc

The pair of capacitors Ccand Cgacts as a capacitive voltage divider If the holding resistance Rh is

infinitely large, the voltage on the victim net would be Va∗Cc/(Cg+ Cc) The voltage on the victim

Aggressor net

Victim net

VA

Cc

Cg

ta

VB

VA

Rh

A

B

V

t

FIGURE 34.2 (a) Circuit and (b) waveforms of capacitive coupling noise injection.

the current flowing through this resistance discharges the grounded capacitance Cgand charges the

coupling capacitance Cc This slows down the voltage increase on the victim and eventually makes this voltage return to zero after the aggressor completes its switching The speed of this process and, correspondingly, the height and the widths of the noise pulse depend on the amount of current flowing through the holding resistance The smaller the holding resistance, the higher the current it provides

to the victim net and the shorter and narrower is the noise pulse The waveforms of noise injection are shown in Figure 34.2b A similar situation occurs if the victim is at Vdd and the aggressor net switches from Vdd to 0

The circuit shown in Figure 34.2a can be solved analytically A formula for the height of the noise pulse is expressed as follows [2,3]:

Vn= Vdd ·RhCc

ta

1− exp



−ta

Rh(Cg+ Cc)



(34.1) From the above formula, it is clear that noise can be reduced by the following methods:

• Slowing down the aggressor transition, i.e., increasing its transition time ta

• Reducing the coupling capacitance Cc

• Increasing the grounded capacitance Cg

• Reducing the holding resistance Rh

These methods form the basis for the noise avoidance and repair techniques discussed in the sequel

34.2 NOISE ANALYSIS

Depending on the victim net behavior, there are two possible types of coupling noise: functional noise and noise on delay Functional noise occurs when the victim net is not expected to switch during noise injection There are four types of functional noise corresponding to the combinations of undershoot and overshoot from signals that are nominally at low and high logic levels These types

of coupling noise are shown in Figure 34.3 Typically, low overshoot and high undershoot are most harmful types of noise for circuit operation If a noise pulse on a logic low wire is high enough,

it can change the state of the victim receiver gate and create a circuit logic failure However, high overshoot and low undershoot can be problematic for some kinds of circuits, such as circuits with pass-transistors Additionally, they affect circuit reliability by magnifying the hot electron injection (HCI) and the negative bias temperature instability (NBTI)

Noise on delay occurs when the victim net transitions from one state to the other during noise injection The injected noise pulse affects the victim transition, making it either faster or slower, depending on whether the aggressor net switches in the same or opposite direction as the victim net

If the delay variation because of the noise pulse is too high, it may create a circuit timing failure Figure 34.4 shows waveforms of victim and aggressor transitions for noise on delay

34.2.1 NOISECALCULATION

The goal of noise analysis is to identify all nets susceptible to noise that may result in circuit failure

To be useful, the noise analysis should be conservative so as not to miss any potentially dangerous noise On the other hand, noise analysis should not be too pessimistic, or it will report too many false noise violations, which are difficult to repair and will lead to wasted power and design effort Thus, a good noise analysis tool should be both conservative and sufficiently accurate The simplified model shown in Figure 34.2, while useful for understanding the coupling noise phenomenon, is not accurate for computing the actual noise in VLSI interconnects

(a)

Vvictim

Vvictim

0

0

Vdd

t t

FIGURE 34.3 Types of functional noise (a) Noise injected to high logic level and (b) noise injected to low

logic level

Aggressor transition

Noise injected into quiet victim

Additional delay owing to noise

t

t

FIGURE 34.4 Waveforms of noise on delay.

Victim receiver 1 Victim net

Victim receiver 2 Victim driver

Aggressor net 2 Aggressor

Aggressor

FIGURE 34.5 Example of noise cluster with capacitive coupling.

Figure 34.5 shows a more accurate model of a noise cluster The interconnect wires are broken into segments, and each segment is modeled with its resistance, grounded capacitance and coupling capacitance The noise is injected into the victim net along the whole length of the victim wire by multiple aggressors The victim driver is trying to hold the victim net at the correct potential by providing the current for charging or discharging the capacitances of the victim net This current is

a nonlinear function of the voltage at the input and output of the victim driver The injected noise pulse is propagated through the victim interconnect to the input of the victim receiver gates affecting their state and behavior

Noise analysis requires solving two main problems: calculating the amount of injected noise and determining whether the injected noise pulse is critical for circuit operation or not The calculation

of the actual noise waveform is a difficult problem because a noise cluster is a complex nonlinear circuit This can be solved most accurately by performing a SPICE-level transient analysis, and by solving differential equations describing the transient behavior of the noise cluster Unfortunately, this approach is too slow for large designs because VLSI chips may have many millions of noise clusters Moreover, the simulation-based approach with a single stimulus is not necessarily conservative enough There can be an extremely large number of possible noise injection scenarios and we cannot guarantee that the worst of these has been chosen for simulation The aggressors can switch at different moments in time and have various waveforms with different transition times The actual aggressor behavior depends on many factors such as the state of the circuit, its input signals, supply voltage, temperature, and process variation Therefore, SPICE simulation of noise clusters is resorted to only

in special cases such as verifying and tuning noise analysis techniques, or in analyzing complicated situations

To simplify the computation of an injected noise pulse, it is common to approximate the non-linear circuit of the noise cluster with a non-linear circuit The approximation should be conservative enough so that the noise computed from this approximation is not less than the worst possible actual noise The transformation of the nonlinear circuit into a linear circuit is performed by modeling the aggressor and victim drivers with linear models, as will be discussed in Section 34.3 The receivers are modeled by their input capacitances The resulting linear circuit can be analyzed using the super-position principle, which is a key benefit of linear modeling The noise injected by each aggressor net is computed separately assuming that all the other aggressor drivers are quiet A model order

reduction technique [4,5] is usually used for this computation The total noise pulse is calculated by superimposing the noise pulses injected by each aggressor net The noise pulses are aligned at their peaks to obtain the maximum possible combined noise pulse

34.2.2 FAILURECRITERIA

The second main problem of noise analysis is making a decision whether the injected noise is dangerous for circuit operation or not This problem is solved differently for functional noise and noise on delay In case of noise on delay, delay variation even from small injected noise can be harmful for correct circuit operation if the affected net is on a critical-signal propagation path Therefore, in case of noise on delay, we must compute not only the noise pulse but compute also the delay variation due to that pulse and perform timing analysis with the delay variations obtained from noise analysis Accurate computation of the delay variation because of an injected noise pulse is a difficult nonlinear problem One of the common approximate methods to solve this problem is to superimpose linearly the transition of the victim net and the injected noise pulse According to Ref [6], the maximum delay variation is obtained if the peak of the noise pulse is aligned with the 50 percent crossing time of the victim transition in the presence of noise This alignment is demonstrated in Figure 34.4 However, this method maximizes the delay variation of the victim net as seen at the victim receiver's input and does not take into account the propagation of the resulting signal transition through the victim receiver gate To improve the accuracy of delay computation, it was proposed

to maximize the delay measured from the output of the victim driver to the output of the victim receiver [7] This takes into account nonlinear and low-pass filtering properties of the victim receiver gate However, because it is difficult to compute this delay variation without nonlinear simulation

of the victim receiver gate, precharacterized multidimensional tables are used for this computation

in Ref [7] After the noise analysis, the calculated delays are used for noise-aware timing analysis that verifies whether the circuit meets timing requirements in the presence of noise

An alternative approach to estimating delay variation because of coupling noise is based on the observation that the noise pulse injected during victim net transition results in additional charge flowing either from or into the victim driver From this, it was concluded that the injected noise pulse can be modeled with a change of the effective load capacitance [8,9] The degree of the effective load capacitance variation is called the Miller coefficient The main benefit of this approach

is its simplicity and convenience for integration of the noise analysis into a timing analysis engine The noise analysis tool simply updates values of the effective load capacitance, and then performs the timing analysis in the usual way with the updated load capacitances Unfortunately, the accuracy

of this approach is not very good because it does not take into account the fact that the waveforms in the presence of the injected noise are significantly different from the waveforms without noise, and a simple change of the victim load capacitance cannot accurately capture the effect of noise injection

In case of functional noise, a noise pulse is injected into a victim net when it is in its stable state If the noise pulse is large enough, it can propagate through combinational gates to memory elements (latches or flip-flops) and change their state, resulting in a circuit failure Digital gates suppress propagation of narrow short pulses for two reasons: (1) their voltage transfer characteristic attenuates small deviations of the input voltage from the values corresponding to logic 1 and 0 and (2) CMOS gates act as low-pass filters

There are two main classes of failure criteria for functional noise One of them is propagation

of the injected noise pulse though the circuit until memory elements [10] The computation of the propagated noise pulse can be carried out either by precharacterized tables or by using simplified nonlinear models of gates [10,11] The noise propagation failure criterion takes into account that the propagated noise pulse combines with noise pulses injected into the nets along the noise propagation path Unfortunately, the noise propagation criterion requires rather complex computations Therefore,

it is more suitable for sign-off analysis

Low noise margin: NML=VIL−VOL

Vin

VIH

VOH

VIL

VOL

FIGURE 34.6 Inverter voltage transfer characteristic and noise margins.

The other class of noise failure criteria is based on using local noise threshold values [10–15] Only noise signals that are higher than a specified threshold level are considered dangerous The main difficulty with such criteria lies in the selection of the appropriate threshold One of the common approaches is to use the static noise margin of the victim receiver gate [16] derived from the unity gain points of the transfer characteristic, as shown in Figure 34.6 This derivation is based on the consideration that, for safe operation, the differential DC amplification coefficient of the gate should

be less than 1 However, this criterion does not take into account the low-pass filtering properties of CMOS gates, and therefore, it can be too pessimistic There are several modifications of the local noise failure criteria that either directly compute a propagated noise pulse or use a noise rejection curve [12] An example of a noise rejection curve, whose coordinates are the height and the width

of the noise pulse, is shown in Figure 34.7 The points lying higher than the noise rejection curve

Noise in this region is dangerous

Noise width (ps) Noise in this region is not dangerous

Noise

FIGURE 34.7 Noise rejection curve.

correspond to the combinations of noise height and width that are dangerous for circuit operation.

To take into account the noise propagating from the input of the victim driver to its output, the local criterion can increment the injected noise by some predefined margin In this case, the criterion checks that the noise propagated through the victim's receiver gate is less than this predefined margin This approach is called noise budgeting, and although it is computationally efficient, the local criteria

of noise failure are not very accurate because they cannot take into account how the noise pulse propagates through the circuit However, because of their efficiency, the local noise criteria are very popular for noise avoidance, noise-aware routing, and repairing methodology

34.3 SIMPLIFYING MODELS AND ANALYSIS

For chip-level signal-integrity verification, it is essential to analyze millions of net clusters (each cluster consisting of a victim net and its significant aggressors) Moreover, the chip-level analysis will have to be carried out several times before a complete noise sign-off, nearly as often as significant changes are made to the design layout Design productivity requires this analysis be performed with

a reasonable computational time, typically within a few hours A fast noise analysis turnaround is made possible mainly through two simplifications discussed in this section: simplification of models and conservative filtering of nonrisky nets These simplifications are indispensable for early noise estimation during the global and detailed routing procedures, wherein noise is to be estimated in an inner loop of routing optimization

34.3.1 SIMPLIFICATION OFMODELS

Linear models for the victim and aggressor drivers, receivers, and the interconnection significantly speed up noise simulation while providing acceptable accuracy Linear simulation is extremely fast compared to nonlinear simulation Moreover, in certain situations, even analytical formulations can

be used Another key advantage of working with linear models is the ability to apply the principle

of superposition, which permits simulating the victim and aggressor driver sources individually and later combining their effects This is crucial for determining a temporal alignment between the switching of the victim and aggressors that produces conservative noise estimation Searching for

a proper alignment of source waveforms that will maximize the noise effect (i.e., glitch or delay variation at a receiver gate) is prohibitively expensive for nonlinear circuits Using superposition, the results of independent simulations of linear aggressor and victim driver sources can be easily combined to maximize the noise effect The construction of linear models of drivers and receivers is described in the following subsections

34.3.1.1 Aggressor Driver Model

A simple linear model of the aggressor driver consists of a Thevenin voltage source with a series resistance, as shown in Figure 34.8 Typically, a saturated ramp is used as the voltage source, although other waveforms can also be used Such a model is fitted by matching the salient time points (e.g., 10,

50, and 90 percent crossing points) of the output waveforms obtained with the linear model and with the actual nonlinear driver, for a given load capacitance The model is precharacterized for a range

of load capacitance values During noise analysis, the effective capacitance [17] of the distributed parasitic elements of the interconnect wires and the driver slew are determined using either iterative

or noniterative techniques

34.3.1.2 Quiet Victim Model (for Functional Noise)

For a small noise height, the driver can be approximated by a holding resistor connected to ground

or Vdd The holding resistance can be characterized in several ways: