Handbook of algorithms for physical design automation part 18 ppsx

8.6 FLOORPLAN SIZING METHODS Given a floorplan topology, the second task is to obtain the aspect ratios of the modules so that the overall area, total netlength, and maximum netlength is

or four modules/rectangles at any level with their given connectivity and size specifications takes constant time

Another strong motivation for employing a hierarchical approach is that because floorplanning decisions affect the subsequent phases of placement or global routing, it is desirable to integrate these phases as much as possible A hierarchical method makes this computationally feasible as designed and implemented by Dai et al [16,39] and Lengauer et al [40]

As part of the macrocell based layout system called BEAR, the hierarchical floorplanner by Dai et al consists of three steps:

Step 1—Bottom-up clustering: A hierarchical tree is constructed in a bottom-up fashion

by clustering strongly connected modules greedily Each cluster has a limited number of modules, typically upto four For each cluster, the shapes of the blocks are also considered

so that there is no mismatch within the cluster Issues with size incompatibility at higher levels between two neighboring clusters with fewer connections may arise, but these can

be resolved by limiting the sizes of the clusters at the higher levels so that the smaller sized clusters are dealt with earlier, thereby reducing the percentage of wasted area

Step 2—Top-down placement: The cluster tree is traversed from the root, which has its

desired shape and terminals specified These requirements are propagated to the children clusters and their respective shape and terminals are determined The small number of possi-ble floorplan templates (Figure 8.11) are enumerated and clusters are assigned to rectangles

or rooms in a template to obtain a floorplan topology In most cases, the winning topology

is determined by computing the estimated routing space for each of the possible topologies This is continued till the orientations of the leaf modules are decided It may be pointed out that this method works well when the leaf level modules can be of flexible shape A certain amount of look ahead to the grandchild level is also added during top-down shape determination The system allows the user to monitor the trade-off among shape, area, and connections costs

Step 3—Floorplan optimization: This step improves the solution obtained above by

iter-atively selecting certain blocks and resizing them The blocks selected usually lie on the longest paths through the placement based on the routing estimates Such paths are either between the left and right sides of the chip or the top and bottom sides The routing cost is computed by adding the edge weights (number of net connections) between pairs of clusters multiplied by the distance between their centers in the current placement The global routing information is updated incrementally after each iteration The stopping criterion is that the longest paths contain fixed size blocks only or flexible blocks that belong to the longest path in the perpendicular direction as well Although this method is very efficient for small circuits, it needs to be executed in a two-pass mode iteratively, one for each direction, to achieve fast convergence for larger circuits

In the hierarchical approach taken by Lengauer et al [40], the hierarchy or cut-tree is generated in

a top-down manner by recursive mincut method initially and then the bottom levels of the tree are obtained by bottom-up clustering Once again the degree of the cut-tree is restricted to 4 Floorplan

FIGURE 8.11 Some templates used in hierarchical floorplanner BEAR with at most degree 4 branching at

any node of the hierarchy

sizing is done by bottom-up traversal of the cut-tree to compute the floorplan alternatives based

on the shape function for the children modules/rectangles Finally, a particular floorplan alternative and its corresponding global routing are constructed simultaneously For a floorplan topology, there exists a breadth-first top-down labeling of the nodes of the cut-tree with a particular pattern The pattern selection performed at each node is guided by the external wiring costs computed for the previous cut-tree level without the need for penalty functions à la Dai et al for assigning modules to rectangular regions smaller than the requirement Moreover, the number of patterns is bounded by a small integer The sizing algorithm employs shape function instead of the penalty-oriented method

by Dai et al Thus, this method implemented in the system FRODO reports better results over BEAR

8.6 FLOORPLAN SIZING METHODS

Given a floorplan topology, the second task is to obtain the aspect ratios of the modules so that the overall area, total netlength, and maximum netlength is optimal Some of the major techniques are listed below and more details of two important ones appear in the subsequent sections

1 Force-directed with slicing [41]: The PIONEER system is an iterative method It pro-vides two capabilities: extraction of initial layout from a user-specified data and interactive graphics for improving the initial layout The improvement of initial layout proceeds in three steps First, macrocenters are determined, then a slicing structure is generated, and finally the layout is expanded

2 Relaxation method [42,43]: This iterative floorplanning method is different from improve-ment by interchange because relaxation implies an obvious next state In Ref [42], dimensional relaxation is used to improve a floorplan It consists of modifying the shapes

of cells as well as the topology of the horizontal and vertical line segments that define the floorplan

3 Simulated annealing: Timber Wolf [44] is one of the first floorplanning systems based on simulated annealing technique It produces not only the relative positions of the modules but also their aspect ratios and pin positions The algorithms for optimal floorplan design, reported in Ref [21,38], also use simulated annealing The first algorithm can generate slicing structures with rectangular modules only, whereas the second one can produce non-slicing floorplans and even L-shaped modules A new representation of floorplans using normalized Polish expressions facilitates selection during iterative improvement by pair-wise interchange (see Chapter 9 for details) The major disadvantages of these systems are that they are computation intensive and may not be readily adapted to deal with various constraints on floorplan

4 Genetic algorithm [45]: This stochastic iterative method requires appropriate encoding of

a floorplan and its associated cost function along with the definition of effective crossover and mutation operators for iterative moves Each move has an activation probability It can handle large floorplans and the quality of the solutions are comparable with simulated annealing-based methods

5 Analytic force-directed method with packing [46,47]: Iterative floorplanning by this method consists of two subtasks First, an initial placement is obtained either by potential energy method, or by attractive and repulsive force method as in the CHAMP system Then a semiautomatic block packing process is undertaken by relocating and reshaping modules

as well as the chip boundary Constraint-based analytic sizing methods have also been proposed [48–50]; further details are elaborated in the following section

6 Branch-and-bound [29]: Layouts occupying minimum area can be obtained by this method using graph-theoretic representation of floorplan and suitably formulating a network flow optimization problem Graph-theoretic representation can also yield optimal aspect ratios

of modules in any floorplan by a branch-and-bound heuristic

8.7 ANALYTIC SIZING

The floorplan sizing algorithms that adopt an analytical approach essentially model the problem as a set of constraints on the dimensions and connectivities of the rectangular modules such that a certain objective function is minimized Among these, a method based on potential energy modeling of overlap and separation was proposed by Ying et al [48] The shape constraints are met by bounding penalty functions An unconstrained minimization problem is then solved heuristically As the time complexity is high, the authors mention incorporating hierarchical floorplanning by using the method recursively

The most effective and widely referred analytic floorplan sizing algorithm based on mixed integer programming formulation was proposed by Sutanthavibul et al [49] The essence of this is described next The assumption is that the area of a rectangular module is known a priori, but its actual shape may be either fixed or flexible within certain limits for the aspect ratios (width to height ratio) The variables in the mixed integer programming are of two types, namely integer variables(x i , y i )

indicating the x- and y-coordinates of the lower left corner of module i, and certain 0–1 variables that primarily take care of different constraints The width and height of module i is denoted by (w i , h i ) Constraints for nonoverlap of modules i and j: If both modules are rigid, we have the four linear

inequalities (I.a) Typically, the bounds on the width W and height H of the chip may be specified By employing two 0–1 integer variables x ij and y ij, we can ensure that at least one of the four inequalities

(I.b) holds for any pair of modules i and j Thus for any one of the four possible values of (x ij , y ij ),

only one of the four inequalities is applicable, the other three being vacuously true It is assumed

that for all i, the values of (x i , y i ) are nonnegative and definitely less than the chip width or height as

the case may be

Constraints for nonoverlap of two rigid modules i and j

x i + w i ≤ x j , i left of j x i + w i ≤ x j + W(x ij + y ij )

x i − w j ≥ x j , i right of j x i − w j ≥ x j − W(1 − x ij + y ij )

y i + h i ≤ y j , i below j y i + h i ≤ y j + H(1 + x ij − y ij )

y i − h j ≥ y j , i above j y i − h j ≥ y j − H(2 − x ij − y ij )

(I.a) Variable-size chip (I.b) Fixed-size chip

If rotation by 90◦is to be permitted for the rigid modules, then an additional 0–1 integer variable

z i is introduced and the constraints are modified to the following where M = max(W, H):

x i + z i h i + (1 − z i )w i ≤ x j + M(x ij + y ij )

x i − z j h j + (1 − z j )w j ≥ x j − M(1 − x ij + y ij )

y i + z i w i + (1 − z i )h i ≤ y j + M(1 + x ij − y ij )

y i − z j w j + (1 − z j )h j ≥ y j − M(2 − x ij − y ij )

Next, modules with flexible shapes but fixed area s iare considered in the inequalities (I.c and I.d) by

converting the quadratic relation w i h i = s i to a linear one, i.e., by expressing h ias a linear function

of w i based on the first two terms of the Taylor series expansion about the point w i maxas given below:

h i= s i

w + (w i max − w i ) s i

w2 or, h i = h i0 + w iλi

where h i0= si

wi max,λ i = si

w2 i max, andw i = w i max − w i

Constraints for nonoverlap of a flexible module i

x i + w i max − w i ≤ x j x i + w i max − w i ≤ x j

y i + h i0 + w iλi ≤ y j y i + h i0 + w iλi ≤ y j

x i − w j ≥ x j x j + w j max − w j ≤ x i

y i − h i ≥ y j y j + h j0 + w jλj ≤ y i

(I.c) With rigid module j (I.d) With flexible module j

Constraints on interconnection length can also be thrown in with few continuous positive variables per net and the half-perimeter metric is used The complexity of the entire mixed integer linear programming problem may be reduced by considering the constraints for critical nets only as this number is far smaller Routability is modeled by linear constraints based on the rule that the total net length is 0.5 times the length of the routing tracks in the chip This ensures that enough empty space around each module is reserved for routing For each pair of modules, two continuous and one integer variable is introduced

The package LINDO is used to solve for the values of the variables and arrive at a floorplan solution If the topology is given, then all the 0–1 integer variables acquire specific values and the problem of determining the shapes of the modules reduces to standard linear programming one and

is hence polynomially solvable The number of continuous variables and the linear constraints are

respectively 2n and O (n) where the floorplan has n modules.

The major drawback of this approach is the huge solution time for mixed integer linear pro-gramming For example, a floorplan with 25 modules may need about 600 integer variables The technique devised to overcome this is to consider very few, typically 10–12, modules at a time and then successively augment the floorplan in a locally optimal way by adding a new group of mod-ules each time till all modmod-ules have been processed The selection of the groups of modmod-ules can be performed either by clustering based on connectivity or linear ordering depending on the I/O con-nections The key to reducing the complexity is to have fewer number of variables, thus the already positioned modules in a partial floorplan are replaced by fewer number of covering rectangles The floorplanning algorithm by analytical method [49] is given in Algorithm 2

Algorithm MILP_Floorplan

begin

Select a group S of k modules as seed;

Formulate MILP for S;

Solve to generate partial floorplan for S;

while (k ≤ n)do/ ∗ n is total number of modules ∗/

Select a new group of e modules based on connections to already positioned modules; Find a set of d covering rectangles for the present partial floorplan where d ≤ k;

Formulate MILP for d covering rectangles and e unpositioned modules;

Solve to obtain new partial floorplan;

k = k + e;

endwhile;

end.

8.8 BRANCH-AND-BOUND STRATEGY FOR SIZING

One of the early algorithms for optimal sizing of general floorplans with rigid modules was devised

by Wimer et al [29] The input to this algorithm is a floorplan topology represented by a pair of

dual polar graphs, also known as the x-graph or horizontal constraint graph, and the y-graph or

vertical constraint graph Each graph is planar, directed acyclic with a single source and a single sink corresponding to the left (top) and right (bottom) edges of the bounding rectangle of the floorplan A

vertex in the x-graph corresponds to a vertical side of a rectangular module in the floorplan There is

a directed arc from a vertex i to a vertex j if there is a rectangular module in the floorplan whose left and right edges correspond to i and j, respectively In the y-graph, the vertices denote the horizontal edges of the modules and the directed arc goes from the top edge i lying above the bottom edge j of a module Each module M kin the floorplan topology has a set of one or more specified dimensions, so

in the x-graph the directed edge from the left to the right vertical edge of M khas an associated weight

denoting the width w k of M k Similarly, in the y-graph the weight of a directed edge corresponds to

the height of the module whose top and bottom edges form the endpoints of the edge

In the floorplan sizing problem, the goal is to determine the positions of all the modules for a given topology such that the total area of the bounding rectangle is minimized For slicing topologies, the two graphs belong to the special class called series parallel If each leaf has finitely many possible shapes, then Stockmeyer’s bottom-up sizing algorithm [22] becomes applicable However, for the general case the problem is NP-hard so a branch and strategy is chosen It proceeds as follows: First, a module is chosen based on some criterion for a particular level In other words, if there

are n modules, then there are n levels in the branch-and-bound tree and the degree of a node in the

ith level is equal to the number of possible shapes of module M i A linear order of the modules is

obtained so that along any directed path of x- or y-graph, the predecessors of a module appear in the linear order before the module At the root, each edge of the x- and y-graphs is assigned the smallest

possible value it may take among all given shapes for the first module in the linear order While

going from the ith level to the (i + 1)th, appropriate values are assigned to the edges corresponding

to the module M i+1in the two graphs At each node of the tree, the width and height of the partial floorplan is computed When going down along a path in the tree from root to a leaf, the area is

nondecreasing in the number of already positioned modules Let Amindenote the minimum value of area achieved thus far The forward processing is performed in level order from the root If at a node

in ith level, the area A is greater than the current Aminof the(i + 1)th level processed thus far from

left, then this node is not expanded any further (Figure 8.12) and the process backtracks upward till

it finds a suitable node for branching downward

The efficiency of the method is influenced by the following factors: (1) the value of Amin as early backtracks are desirable; (2) the area of a partial floorplan obtained is a lower bound on the area of the complete floorplan, hence if the lower bound is raised, early backtracks will occur; and

(3) the order in which the possible dimensions of module M i are examined at the ith level of the

branch-and-bound tree

Intuitively, a module whose size is likely to have greater effect on the area of the complete floor-plan, such as one with large size or one which lies on a critical (longest) path or many directed paths in the polar dual graphs, should be considered earlier Along with a branching strategy that guarantees attainment of global minimum, a very effective bounding value for the area of the remaining modules

is computed to guide the search

Additional efficiency of the method is attained by decomposing the floorplan topology into maximal slicible structures for which series-parallel algorithm is applied Branch-and-bound strategy

is used only for the maximal rectangles as discussed in Section 8.4.1

Another constraint-based floorplanning algorithm proposed by Vijayan et al [50] also can handle flexible, fixed (rigid), and preplaced modules The input is specified as two sets of constraints in the form of the two directed acyclic horizontal and vertical constraint graphs A linear time algorithm for topological sorting of directed acyclic graphs is used to find the critical (longest) paths in the

(a) (b) (c)

0

(d)

4 4,1

1,4 2,2

2,5

27 45 99

9,1 3,3 1,9 9,1 3,3 1,9 9,1 3,3 1,9 9,1 3,3 1,9 9,1 3,3 1,9 9,1 3,3 1,9

B1

B2

B3

B1 B2

B3

FIGURE 8.12 (a) Example floorplan topology with three modules, (b) its x-graph, (c) its y-graph, and (d) its

branch-and-bound tree where shape lists are B1: (4,1),(2,2),(1,4), B2: (5,2),(2,5), and B3: (9,1),(3,3),(1,9) The width–height pair appears inside the node and the area of the subfloorplan at that level, outside it A node marked

“∗” has area greater than minimum bound at that stage and hence no further branching from it is required (From

Wimer, S., Koren, I., and Cederbaum, I., IEEE Trans Computer-Aided Design, 8, 139, 1989.)

two graphs Redundant constraints are removed and flexible blocks on the more critical paths are reshaped Certain criteria to characterize two different notions of redundancy among constraints are formulated and utilized to reduce the time complexity This heuristic is iterated until a floorplan solution of desired dimensions is obtained

8.9 KNOWLEDGE-BASED FLOORPLANNING APPROACHES

Floorplanning is meaningful for very large designs tackled in a top-down fashion There is generally

a vast amount of design data and the optimization problems are computatinally hard Often more than one objective has to be optimized Thus, artificial intelligence techniques have been attempted

by a few researchers, especially when details of modules are not known

FLOYD, one of the early rule-based expert systems for floorplanning, was designed and imple-mented by Dickinson [1] The key idea in another system FLUTE [2] is to produce a rectangular topology by placing the modules on a rectangular grid graph using a set of rules that take shape and connectivity constraints into account Then sizing or geometric realization is achieved by a heuris-tic method to solve a system of linear and quadraheuris-tic inequalities Like many artificial intelligence systems, this is implemented in LISP

Jabri and Skellern [4] adopt a combination of algorithmic and knowledge-based approach for

a top-down floorplanning system called PIAF Rectangular dualization method is used to generate topologies and then other constraints are introduced for knowledge-based estimation and prediction

of dimensions and areas of modules The final phase consists of a greedy algorithm for determining the exact shapes and locations of the modules The system FLAIR developed by Brück et al [3] employs a band of expert systems for estimating a broad range of design parameters relevant to

transforming an architectural plan to a geometric one in two steps—first producing a rough or postulative plan and then a final one

In general, these systems are fairly complex to design, implement, and validate Accurate def-inition of the rule base and its fine tuning are required for attaining optimality These have greater potential in interactive design environments

8.10 UNIFIED METHOD FOR TOPOLOGY GENERATION AND SIZING

With exponentially many feasible topologies for a given neighborhood graph, design space explo-ration and optimality are limited if the sizing is performed on a particular feasible topology Among the very few methods that integrate the two subtasks of floorplanning, two are notable

The first one is a dynamic programming based method [51] that can handle slicible floorplans only A set of slicing trees is enumerated by top-down partitioning of the adjacency graph and represented by an enumeration tree model Size optimization is carried out simultaneously by Stock-meyer’s method [22] for each topology enumerated The role of dynamic programming is to reduce the time complexity to polynomial time by memoization of optimal solutions for subfloorplans The second method [52] is a two-phase technique applicable to nonslicible floorplans including inherently nonslicible ones Canonical embedding results of Section 8.4.3 are applied to establish that a binary tree representation for general floorplans exists where the internal nodes correspond

to either straight cutlines or Z-cuts having two monotonic staircase bends The possible topologies are derived by top-down partitioning and kept in an AND–OR graph A bottom-up sizing phase finally reports the optimal floorplan The slicibility criterion in Ref [34] can provide additional improvement in the speed of the floorplanner with negligible sacrifice of solution quality

ACKNOWLEDGMENTS

The author would like to thank all her floorplanning research collaborators, especially Professors Bhargab B Bhattacharya of Indian Statistical Institute and Parthasarathi Dasgupta of Indian Insti-tute of Management, Kolkata Part of the Sections 8.3, 8.3.1, 8.4.2, and 8.7 has been published in

Sur-Kolay, S and Bhattacharya, B.B., Foundations of Software Technology and Theoretical Computer

Science, LCNS 338, 88, 1988; Bhasker, S and Sahni, S., Algorithmica, 3, 274, 1988; Sur-Kolay, S.

and Bhattacharya, B.B., Proceedings of the ISCAS, pp 2850–2853, 1991; Sutanthavibul, E.,

et al., IEEE Trans Computer-Aided Design, 10, 761, 1991, respectively With permission.

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9 Slicing Floorplans

Ting-Chi Wang and Martin D.F Wong

CONTENTS

9.1 Introduction 161

9.2 Preliminaries 162

9.3 Slicing Floorplan Representations 163

9.3.1 Slicing Tree 163

9.3.2 Polish Expression 164

9.4 Optimizations on Slicing Floorplans 164

9.4.1 Area Optimization 164

9.4.1.1 Oriented Slicing Tree 164

9.4.1.2 Unoriented Slicing Tree 168

9.4.2 Area/Power Optimization 168

9.5 Classical Slicing Floorplan Design 169

9.5.1 Mincut-Based Slicing Floorplan Design 170

9.5.2 Point-Configuration Based Slicing Floorplan Design 171

9.5.3 Simulated Annealing Based Slicing Floorplan Design 171

9.6 Slicing Floorplan Design Considering Placement Constraints 172

9.6.1 Boundary Constraints 173

9.6.2 Range Constraints 174

9.6.3 Abutment Constraints 175

9.6.4 Clustering Constraints 176

9.7 Other Advances in Slicing Floorplans 177

9.7.1 Theoretical Results for Area-Optimal Slicing Floorplans 177

9.7.2 Completeness of Slicing Tree Representation 178

9.7.3 Heterogeneous FPGA Floorplanning 179

9.7.4 3D Floorplanning 181

9.8 Conclusion 182

References 183

9.1 INTRODUCTION

A floorplan is a dissection of an enveloping rectangle R by horizontal and vertical line segments

into a set of nonoverlapping basic rectangles (or rooms) such that each room is large enough to accommodate the module assigned to it Note that in some situations, there may be some basic rectangles without any modules assigned to them We call them empty rooms

An important class of floorplans is the set of all slicing floorplans [1,2] A slicing floorplan is one that can be obtained by recursively cutting a rectangle into two smaller rectangles by either a vertical

or horizontal line segment Typically, a slicing floorplan for n modules has n rooms each of which

161