Models in Hardware Testing- P7 ppt

Disturb coupling fault CFds: an operation write or read performed on theaggressor cell forces the victim cell into a given logic state.. Write destructive coupling fault CFwd: a non-tran

6.4.3.2 2-Coupling Static Faults

2-coupling static FFMs are faults described by FPs involving two f-cells (jf j D 2)and sensitized by the application of at most a single memory operation (m  1) In

this condition, one of the two f-cells (usually denoted by the generic address v) is the

victim cell where the effect of the faulty behavior manifests, while the second cell(usually denoted by the generic addressa) is the aggressor cell, responsible with the

victim for producing the faulty behavior With this distinction three classes of SOSs

can be generated:

1 No cell accessed: the state of the cells sensitizes the fault

2 Only the aggressor cell is accessed

3 Only the victim cell is accessed: the aggressor contributes to the fault simplywith its initial state

Starting with this classification it is possible to enumerate the space of 2-couplingFPs of Table6.2composed of 36 different FPs Only those combinations of opera-tions that actually represent a faulty behavior have been considered

As for the single-cell static FFMs, this set of FPs can be grouped to define a set

of seven well established and characterized FFMs:

1 State Coupling Fault (CFst): the victim cell is forced into a given logic state

when the aggressor cell is in a given state, without performing any operation

As for the state fault, this FFM is special, as no operation is required to tize the fault Four types of state coupling faults exist, defined as CFst.xy/ Df< xayv

sensi-= Nyv

= >g, where x; y 2 f0; 1g This covers FP1, FP2, FP3, and FP4

Table 6.2 2-coupling FP space

2 Disturb coupling fault (CFds): an operation (write or read) performed on the

aggressor cell forces the victim cell into a given logic state Any ation performed on the aggressor is accepted as sensitizing operation (aread, a transition write, or a non-transition write) Twelve types of disturb

oper-coupling faults exist, defined as CFds .xz;wy/ D ˚

< xaz v

; way=Nz v

= > , and

CFds .xz;ry/ D f< xayv

; rxa= Nyv

= >g where x; y; z 2 f0; 1g This covers FP5,

FP6, FP7, FP8, FP9, FP10, FP11, FP12, FP13, FP14, FP15, and FP16

3 Transition coupling fault (CFtr): the state of the aggressor cell causes the

fail-ure of a transition write operation performed on the victim cell This fault issensitized by a write operation on the victim cell, while the aggressor is in a

given state Four types of transition coupling faults exist, defined as CFt r.x0/D

4 Write destructive coupling fault (CFwd): a non-transition write operation

per-formed on the victim cell while the aggressor cell is in a given state results in atransition of the cell itself Four types of write destructive coupling faults exist,

5 Read destructive coupling fault (CFrd): a read operation performed on the

vic-tim cell, while the aggressor cell is in a given state, destroys the data stored

in the victim Four types of read destructive coupling faults exist, defined as

6 Incorrect read coupling fault (CFir): a read operation performed on the

vic-tim cell returns the incorrect logic value, while the aggressor is in a given

state Four types of incorrect read coupling faults exist, defined as CFir .xy/ D

7 Deceptive read destructive coupling fault (CFdr): a read operation performed on

the victim cell returns the correct logic value and changes the contents of thevictim while the aggressor is in a given logic state Four types of deceptive read

destructive coupling faults exist, defined as CFdr.xy/ D˚

The presented set of FFMs allows covering all FPs proposed in Table6.2, and anytest covering these FFMs is therefore able to cover all possible 2-coupling staticfaults Other sets of fault models have been presented in the literature, such as:

 Idempotent coupling fault (CFid): a transition write operation on the aggressor

cell forces the victim in a given state: CFid .xy;wNx/ D ˚

< xayv

; waNx= Nyv

= > ,wherex; y 2 f0; 1g

 Inversion coupling fault (CFin): a transition write operation on the aggressor

cell flips the content of the victim cell: CFin .x;wNx/ D ˚

 Non-transition coupling fault (CFnt): a non-transition write operation performed

on the aggressor cell forces the victim cell in a given state: CFnt .xy;wx/ Df< xayv

; wax= Nyv

= >g, where x; y 2 f0; 1g

Nevertheless, all these FFMs are either subsets of the seven FFMs presented before

or can be expressed as a combination of these basic FFMs

6.4.4 Dynamic Fault Models

As operations are added to the SOS we enter into the dynamic fault space that

re-sults in a theoretically infinite number of potential FFMs Equation6.7describes arelation between the number of possible FPs and the numberm of operations in SOS

for single-cell dynamic faults (Al-Ars 2005):

#FPsinglecell D

(

2 m D 0

The equation clearly shows an exponential relation between the number of FPs and

the number of operations in SOS This actually reduces the ability of exploring this

huge space of faults for defining FFMs, due to limited availability of simulation timeand computation power

In order to cope with this problem, experiments on an extensive set of memorydevices showed that the probability of dynamic fault decreases whenm increases(Al-Ars et al 2002) Based on this assumption, two-operations dynamic faults havebeen the most studied in the literature and will be considered in this chapter Asfor static fault models, two-operations dynamic faults can be additionally clustered

according to the number of f-cells.jf j/ involved in the fault We shall focus on:(i) single-cell two-operations dynamic faults.jf j D 1; m D 2/, and (ii) 2-couplingtwo-operations dynamic faults.jf j D 2; m D 2/ This leads to a space of 30 single-cell FPs, plus 192 2-coupling FPs

This space is in some way already too huge to be explored For this reason inVan de Goor et al.(2000), a limited set of these FPs has been simulated on realisticdefective memory devices and the following established FFMs have been defined:

1 Dynamic Read Disturb Fault (dRDF): a write operation immediately followed

by a read operation on the same cell changes the logical value stored in the faultymemory cell and returns an incorrect output Four types of dRDFs exist, defined

as dRDF .xy/D˚

< x; wyry= Ny= Ny >

, wherex; y 2 f0; 1g

2 Dynamic Deceptive Read Disturb Fault (dDRDF): a write operation immediately

followed by a read operation on the same cell changes the logical value stored inthe faulty memory cell, but returns the expected output Four types of dDRDFs

exist, defined as dDRDF .xy/D˚

< x; wyry= Ny=y >

, wherex; y 2 f0; 1g

3 Dynamic Incorrect Read Disturb Fault (dIRF): a write operation immediately

followed by a read operation on the same cell does not change the logical value

stored in the faulty memory cell, but returns an incorrect output Four types of

dIRFs exist, defined as IRF .xy/D˚

< x; wyry=y= Ny >

, wherex; y 2 f0; 1g

4 Dynamic Disturb Coupling Fault (dCFds): a write operation followed

im-mediately by a read operation performed on the aggressor cell causes the

victim cell to flip Eight types of dCFdss exist, defined as dCFds .xyz/ D

5 Dynamic Read Disturb Coupling Fault (dCFrd): a write operation immediately

followed by a read operation on the victim cell when the aggressor cell is in

a given state changes the logical value stored in the victim, and returns an

in-correct output Eight types of dynamic dCFrds exist, defined as dCFrd .xyz/ D

˚

< xayv ; w v zr z v =Nz=Nz >

, wherex; y; z 2 f0; 1g.

6 Dynamic Deceptive Read Disturb Coupling Fault (dCFdr): a write operation

immediately followed by a read operation on the victim cell when the gressor cell is in a given state changes the logical value stored in the victimcell, but returns the expected output Eight types of dCFdrs exist, defined as

7 Dynamic Incorrect Read Disturb Coupling Fault (dCFir): a write operation

im-mediately followed by a read operation on the victim cell when the aggressorcell is in a given state does not affect the logical value stored in the victim

but returns an incorrect output Eight types of dCFirs, defined as dCFir .xyz/ D

of the set of realistic defects can be used to restrict the fault space (see Section6.6)

6.4.5 n-Coupling Fault Models

In-coupling faults represent fault models wheren different memory cells are volved in the fault mechanism (f -cel ls D n) They are usually referred to as

in-pattern sensitive faults In general the content of a celli (or the ability of i to changeits state) is influenced by the contents of all other memory cells, or by the opera-tions performed on them A pattern sensitive fault is the most general definition ofn-coupling fault in whichn is equal to the size of the memory

In a more realistic situation, the so called neighborhood pattern sensitive faults (NPSFs) are usually considered, in which a reduced set of cells spatially located in

adjacent positions are responsible for the fault mechanism The neighborhood is thetotal number of cells in this set Traditionally the victim cell is called in this context

base cell, while the aggressor cells are called the deleted neighborhood.

In the PSF the neighborhood can be anywhere in the memory while in the NPSFthe neighborhood must be in a single position surrounding the base cell These type

Fig 6.12 Type-1 and Type-2 NPSF

of fault models are particularly indicated when dealing with high density DRAMs,due to the reduced memory cell capacitance

In general two types of neighborhood patterns are considered: Type-1 includingfour deleted neighborhood cells, and Type-2 including eight deleted neighborhoodcells (Suk et al 1979) The type-2 model is more complex and allows to modeldiagonal coupling effects in the memory matrix Figure6.12shows the two types ofneighborhood

Three types of NPSF have been considered in the literature:

1 Active NPSF (ANPSF) (Suk et al 1980), also called dynamic NPSF (Saluja

et al.1985) where the base cell changes its value based on a change in the pattern

of the deleted neighborhood In particular, a cell of the deleted neighborhood has

a transition while the rest of the neighborhood including the base cell has a givenpattern For example< x1d 0x2d1x3d 2xd 34 x5B; wd 0Nx1= Nx5B= >, where xi 2 f0; 1g,denotes a generic FP belonging to the ANPSF FFM

2 Passive NPSF (Suk et al 1980): a certain neighborhood pattern prevents the basecell to change

3 Static NPSF (Saluja et al 1985): the base cell is forced into a particular statewhen the deleted neighborhood contains a particular pattern This differs fromthe ANPSF as no transition is required to excite the fault

6.4.6 Multiple Faults

It may happen that the effects of two FFMs link together If the faults share the

same aggressor cell and/or the same victim cell, the FFMs are said to be linked.

As an example let’s consider the CFdsdenoted by the following two FPs: FP1D <

Fig 6.13 Example of linked

fault

Figure 6.13 shows a memory with n cells affected by FP1 and FP2 havingdifferent aggressor cells with addressesa1 anda2, the same victim cell with ad-

dress v, anda1 < a2 < v According to FP1, starting witha1 equal to 0 and by

performing wa1, the victim cell v flips from 0 to 1; then, starting witha2equal to

0 and performing wa2, according to FP2the victim cell v changes its value again,

from 1 to 0 The global result is that the fault effect is masked by the application of

FP2, since FP2has a faulty behavior opposite to FP1

Based on this example, two FPs, FP1 D <SOS1=FB1>, and FP2 D

<SOS2=FB2> are linked, and denoted by FP1 ! FP2, if both of the ing conditions are satisfied:

follow- FP1masks FP2, i.e., FB2! FB1

 SOS2is applied after SOS1, on either the aggressor cell or the victim cell of FP1.

To detect linked faults (LFs), it is necessary to detect in isolation at least one ofthe FPs that compose the fault (i.e., preventing the other FP to mask the fault)(Hamdioui et al 2004)

Among the extended space of possible linked FFMs, based on several simulations

on defective memory devices, the following established realistic linked FFMs havebeen defined (Hamdioui et al 2004):

 Single cell linked faults: involve a single memory location where all FPs are

sequentially applied Table6.3reports the list of realistic single-cell linked faults

 2-coupling linked faults: 2-coupling linked faults involve two distinct memory

cells: one aggressor cella, and one victim cell v Two different situations may

happen: (i)a < v, and (ii) v < a Based on this distinction realistic 2-coupling

linked faults can be clustered in three different classes: (i) linked faults based on

a combination of 2-coupling FPs that share both the aggressor and the victim cell.LF2aa/, (ii) linked faults where FP1is a 2-coupling FP and FP2is a single-cell

FP.LF2av/, and (iii) linked faults where FP1 is a single-cell FP and FP2 is a

Table 6.3 Single-cell linked faults

[Hamdioui et al 2004] belong to the following two situations: (i)a1 < v < a2,and (ii)a2 < v < a1 Realistic 3-coupling linked faults can be represented bythe same FPs used to represent 2-coupling linked faults

6.4.7 Fault Models for Specific Technologies and Architectures

The space of fault models defined in the previous sections is far from representing

a complete taxonomy of possible memory faults It actually focuses on a set of veryhigh level, technology independent faults that can be easily applied to any type ofmemory

As we start exploring all the dimensions of the multidimensional space duced in Section6.2, several specific functional fault models can be defined, as forexample:

intro- Fault models for multi-port memories (Hamdioui et al 2001)

 Fault models for cache memories (Al-Ars et al 2008)

 Fault models for DRAMs (Al-Ars 2005)

A detailed analysis of all these fault models is out of the scope of this chapter, and,

if interested, the reader should refer to specific publications

6.5 From Fault Models to Memory Testing

In order to inspect memory devices for possible faulty behaviors, all memory ponents are usually tested at the end of production and sometimes in the field Asalready stated in Section6.1, common practice for memory testing is to apply func-tional test patterns that try to cover FFMs

com-Table 6.4 2-coupling linked faults

2-coupling linked faults L aa

Several testing approaches have been proposed in the literature to buildfunctional memory test algorithms One of the first proposed algorithms was theGALPAT (Van de Goor 1991) It is composed of the following steps:

1 Initialize all memory cells with ‘0’

2 For each celli do:

a) Complement the cell content

b) For each cellj ¤ i read the content of j and the content of i

c) Complement the content ofi

3 Repeat step 2 starting with the memory initialized with ‘1’

The main drawback of this approach is that its complexity isO.4n2/ where n is thenumber of memory cells

Several improvements of this algorithm have been proposed:

 Galloping Diagonal Test: similar to GALPAT (Van de Goor 1991), but it movesdiagonally checking both column and row decoders simultaneously Its complex-ity isO.n3/

 Walking Pattern: similar to GALPAT except that the test cell is read once andthen all other cells are read Its complexity isO.2n2/

All these tests have two common drawbacks: (i) the complexity is in general too high

as it is not linear with the number of memory cells, and (ii) the fault coverage is ingeneral low as they to not systematically try to address specific fault models Forthese two reasons these tests have been abandoned and nowadays common practice

is to resort to a well-known category of test algorithms known as march tests.

The idea of march tests is to construct a number of operation sequences and toperform each sequence on all memory cells, one after the other, before performingthe next sequence in the test A march test is therefore defined as a sequence of

march elements, where a march element is a sequence of memory operations

per-formed sequentially on all memory cells In a march element, the way one proceedsfrom one cell to the next is specified by the address order, which can be increas-ing (denoted by *) or decreasing (denoted by +) The * address order has to bethe exactly opposite of the + address order For some march elements, the addressorder can be chosen arbitrarily as increasing or decreasing and denoted by the m

symbol In a march element, it is possible to perform a write 0 (w0), write 1 (w1),read 0 (r0), and read 1 (r1) operation The 0 and 1 after the read operations representthe expected values of the read By arranging a number of march elements one afterthe other, a march test is constructed

Among all published march tests, a very interesting march algorithm able tocover all static, dynamic, and linked FFMs proposed in the pervious sections ofthis chapter is the March AB (Bosio et al 2008) reported in Eq.6.8

m w1/+ r1w0r0w0r0/

* r1w0r0w0r0/

* r0w1r1w1r1/

m r0/March tests are a preferred method for RAM testing either by means of externaltesters or through built in self test (BIST) solutions Their linear complexity, regu-larity, and symmetry are the reason for this preference However, tests for NPSFs(see Section 6.4.5) cannot be performed by march tests (Mazumder et al 1996),since the base cell needs to be addressed differently from the cells in the deletedneighbor, thus requiring test algorithms with higher complexity difficult to imple-ment in embedded test environments

6.5.1 Generation of March Tests

The generation of a march test begins with the analysis of a set of target FPs used

to identify so-called detection conditions providing the minimum requirements amarch test has to achieve in order to detect the target faulty behaviors Detectionconditions can be then combined together to provide a complete march test

As an example, starting with the following FP< 0; w1=0= > modeling a TF1

transition fault, it is easy to derive that any march test containing the followingconditions: m .: : : w0: : :/ m : : : w1: : :/ m : : : r1: : :/, is able to detect the targetfaulty behavior Multiple detection conditions needed to detect a number of differentFPs have to be combined together to generate a single march test to fully test thememory for all targeted faulty behaviors

The automatic generation of march test is a deeply studied and analyzed problemand several generation algorithms are available in the literature:Smit et al.(1994),Zarrineh et al.(1998),Wu et al.(2000),Zarrineh et al.(2001),Cheng et al.(2002),Benso et al (2002), Al-Harabi et al (2003), Niggemeyer et al (2004), Benso

as technology continuously scales down, and we fully enter the VDSM era, thesensitivity of memories to physical defects is strongly increasing This turns intothe continuous identification and definition of new dynamic faulty behaviors (seeSection6.4.4) to model the effect of new memory defects

As a consequence, the traditional test generation flow proposed in Section6.5.1,where a list of FFMs described in terms of FPs defines a set of conditions able

to detect the target faulty behaviors to be later combined into a resulting marchtest, is becoming a bottleneck Due to the increased number of FPs to consider, thecomplexity of the resulting test algorithms is drastically increasing Increased com-plexity means increased test time and therefore increased test cost (see Section6.1)

In several situations such a significant overhead is not justified with respect to thevery marginal improvement in defect coverage they provide

This makes it mandatory introducing a stronger link between functional test and

physical defects, thus moving from fault-based test approaches to defect-based test approaches.

Defect-based testing typically aims at targeting the following questions:

What can go wrong with this design? How would the design’s behavior change if this pen, and how can that be measured? (Aitken et al 2003 )

hap-Several publications already proved that, working with device level memory models,the set of realistic fault models for a specific memory architecture and technol-ogy can be drastically reduced Moreover, resorting to the detailed informationabout memory architecture and technology, optimized test algorithms can be imple-mented, drastically reducing the overall test time and complexity while guaranteeingvery high fault coverage (Dilillo et al 2003,2005a,b,2006,2007)

While defect-based test represents a key element to reduce test cost, it presentsthe main drawback that test algorithms should be deeply customized to the targetmemory technology and architecture Defect-based testing for memory concentrates

on defect analysis of key parts of the layout and the development of test patterns thatwill test for likely failures This is completely in contrast with the architecture andtechnology independent form of traditional march tests In order to be effectivelyapplicable in an industrial scenario, defect-based memory testing requires a stronginvestment in automating all steps, from defect analysis and simulation, to realisticfault models extraction, and to test generation Few publications addressed theseproblems so farCheng et al.(2003),Al-Ars et al.(2005), andDi Carlo et al.(2008)with all the proposed solutions still far from being applicable in real scenarios Such

a big challenge will most likely be leading several researchers in the field of based memory testing in next years

defect-6.7 Summary

We would like to conclude this chapter with a thought about the future of memorymodeling and testing The first era of memories lasted roughly 10 years, the secondone 20 years We are now around 30 years of semiconductor memories What’snext? Which technologies will allow us to store the hundreds of terabytes we aregoing to need tomorrow? How shall we model and test these monster devices?

Not having a so powerful crystal ball, we simply conclude wishing that the era

of purely academic test algorithms is going to finish soon, to be quickly replaced bythe era of new automated approaches to generate effective and efficient defect-basedalgorithms, capable of supporting memory testing, diagnosing, repairing, and, whynot, on-the-flight real-time autonomic reconfigurations

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Models for Power-Aware Testing

Patrick Girard and Hans-Joachim Wunderlich

Abstract Power consumption of circuits and systems receives more and more

attention In test mode, power consumption is even more critical than in systemmodel and has severe impact on reliability, yield and test costs This chapter de-scribes the different types and sources of test power Power-aware techniques fortest pattern generation, design for test and test data compression are presented whichallow efficient power constrained testing with minimized hardware cost and test ap-plication time

Keywords Low power test  Design for test

7.1 Introduction

Before 2005, the trend stopped to exponentially increase system frequency whilescaling down the geometrical dimensions Instead, scaling is now mainly usedfor implementing highly parallel systems and increasing performance not by fre-quency but by parallelism The main reason of this development is found in the in-creased power consumption which reaches economical and technical limits (Borkar

H.-J Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum

in Honor of Christian Landrault, Frontiers in Electronic Testing 43,

DOI 10.1007/978-90-481-3282-9 7, c  Springer Science+Business Media B.V 2010

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