Models in Hardware Testing- P6 potx

5 Generalized Fault Modeling for Logic Diagnosis 143Dynamic pattern faults contain an additional block describing an initial conditionfor a set of signals.. A single fault tuple covers e

5 Generalized Fault Modeling for Logic Diagnosis 141

Fig 5.4 Example of aliasing

in diagnosis The response to

a test set in (a) is explained

by a single stuck-at fault The

defective behavior is actually

more complex because the

additional test in (b) produces

a 0 at the output

a Test set detects all single stuck-at faults:

x

c b

x 1 1 1 1

a

d

c b

x 1 1 1 1 0

The first part of the condition is true, if there is an event on linea, and the secondpart is true, if the final value ofa is different from the current value of line b

At the first glance, the explanations for observed responses with the minimumnumber of CLFs are the most reasonable ones, however, there is the risk of alias-ing as demonstrated in Fig.5.4 Thus, not only the number of CLFs, but also thecomplexity of their conditions should be considered

In most cases, the goal for production test generation is to achieve high

stuck-at fault coverage It is likely, thstuck-at standard ATPG would generstuck-ate the four pstuck-atternsshown in case (a) This test set provides complete single stuck-at fault coverage andleads to two fails The most reasonable explanation of this behavior is a stuck-at 1

at the outputx However, if one additional pattern is added to the test set like incase (b), the circuit produces a 0 This response cannot be explained anymore by astuck-at fault at the output In fact, there exists no single stuck-at fault, which wouldproduce such a response One possible explanation involves two stuck-at faults atlinesa and d

142 H.-J Wunderlich and S Holst

5.3.1.1 Other General Fault Models

The idea of generalizing fault modeling to describe complex defects is not new.However, the main motivation of the previous works was more related to test gen-eration than to diagnosis For efficient test generation, the initial values of internalsignals, the preconditions and the fault effects have to be given explicitly in a formalway Therefore, these notations are more restrictive in their formulation of condi-tions than CLFs We will take a quick look at three modeling approaches and discusstheir relation to the CLF calculus

Pattern faults (Keller 1996) distinguish between static and dynamic faults Staticfaults have a condition in the form of a set of required signal values If the condition

is met, the fault is active and its impact is described as a set of value changes oninternal signals The following example shows the description of a static OR-bridge:STATIC f

Signalb changes from 0 to 1 if the aggressor signal a is 1 Two conditions have

to be met in order to detect this fault Signala has to be 1, and signal b has to be 0

In CLF notation, this fault is equivalent tob ˚ Œa Nb

In general, a pattern fault may require multiple signals to carry a specific value.This corresponds to a conjunction of these signals in the condition of a CLF Ifthe condition of CLF is a Boolean formula with only one minterm, the fault can

be expressed in the pattern fault model The faulta ˚ Œb Nc for instance can be pressed as:

5 Generalized Fault Modeling for Logic Diagnosis 143Dynamic pattern faults contain an additional block describing an initial conditionfor a set of signals This initial condition has to be met first, and then the signalsmust change to match the values given in the REQ section The signal values given

in the initial condition correspond to the indexed (x1/ values in CLF notation Adynamic pattern fault corresponds to a CLF with one minterm in the condition Inaddition, the minterm may contain both current and indexed previous signal values

An example of a dynamic pattern fault is described below where a transition onsignala causes a faulty value on signal c:

A similar notation is used inKundu et al.(2006) which also targets test tion The fault effect can be described as slow-to-rise or slow-to-fall signal with acertain delay This way, ATPG can be advised to sensitize a path of sufficient lengthfrom the fault site to an observation point to observe the fault effect This explicitdefinition of the temporal behavior of the fault impact has no direct representation

genera-in CLF as it cannot be directly observed genera-in logic diagnosis

Another very general fault modeling technique with a wide application field usesfault tuples (Blanton et al 2006) A single fault tuple covers either a condition inthe form of a required signal value or a fault impact in the form of a new value for

a victim signal For example, the condition fault tuple.a; 0; i/c requires the signal

a to carry the value 0 at time i, and the excitation fault tuple b; 0; i/e describes

a stuck-at 0 on lineb at time i The product of fault tuples combines conditionsand excitations, so that the described fault impact is only present, if all conditionfault tuples are satisfied For instance, the product of the two tuples above models abridge, where signala AND-dominates signal b Multiple products can be combinedwith the OR-operation to model more complex faults

144 H.-J Wunderlich and S HolstThis modeling technique is very similar to pattern faults or the notation inKundu

et al (2006) Again, any CLF with a Boolean function can be noted with fault tuples,more complex conditions cannot be expressed

5.3.1.2 A Taxonomy of Static Bridging Faults

As already described in the second chapter, bridges are an important fault class.They usually involve two signal lines which interact in a certain manner Depending

on the type of bridge and the current values of the signal lines, one or both signalsmay change their logic value The types of bridges are described by two CLFs atmost

Static bridges provide a good example of how the CLF calculus can be used toexpress a class of fault models There are many different fault models available forstatic bridges (e.g wired-logic, dominant-driver).Rousset et al.(2007) presents ataxonomy for the most common models Common to all these fault models is thefact that they do not model timing related behavior The conditions can therefore

be expressed using Boolean functions which depend on the current values of theinvolved signals

Another basic property of static bridge fault models is the fact that errors onlyoccur, if the two involved signal lines carry different values This necessary precon-dition is described by an XOR-term in the conditions If this precondition is true,the actual behavior of the two signals is determined by two Boolean functionsfaandfb The functionfa depends only on signalb, because the value of signal a

is already determined by the precondition Similarly, functionfb depends only onsignala This leads to the following generalized CLF formulation of an arbitrarybridge between two signal linesa and b:

a ˚ Œfa.b/  a ˚ b/;

b ˚ Œfb.a/  a ˚ b/

There are exactly four basic expressions forfaandfb, respectively An expressionmay be constant 0, constant 1 or may use the positive or the inverted value of theother signal in the bridge:

fa.b/ 2 f0; 1; Nb; bg; fb.a/ 2 f0; 1; Na; agAny more complex Boolean formula can be simplified by using the precondition andBoolean identities The formulas given above therefore model every possible staticbridge configuration There are 42= 16 possible configurations that are derived bychoosing one of the four possible expressions forfaandfb From these 16 config-urations, there are six, that are actually derived from other bridges by interchangingthe roles of the signalsa and b This leads to ten unique bridge types including thefault free case (Table5.1)

5 Generalized Fault Modeling for Logic Diagnosis 145

Table 5.1 The ten possible

static bridge types f a b/ f b a/ Bridge type

0 a a OR-dominates b

1 1 a and b swap values (4-way bridge)

1 Na b dominates a & a AND-dominates b

1 a b dominates a & a OR-dominates b

5.4.1 Effect Cause and Cause Effect

The classic diagnosis algorithms follow two different paradigms: Effect-cause ysis looks at the failing outputs and starts reasoning using the logic structure ofthe circuits (Abramovici and Breuer 1980;Waicukauski and Lindbloom 1989) Oneexample of effect-cause analysis is the ‘Single Location At a Time’ (SLAT) tech-nique introduced inBartenstein et al.(2001) A diagnostic test pattern has the SLATproperty, if there is at least one observable stuck-at fault which produces a response

anal-on that pattern identical with the respanal-onse of the device under diagnosis (DUD)

In SLAT diagnosis, the explaining stuck-at faults for all available SLAT patternsare combined to form possible explanations for the erroneous behavior of the DUD

as a whole Cause-effect analysis is based on a fault model For each fault of themodel, fault simulation is performed, and the behavior is matched with the outcome

of the DUD

Standard debug and diagnosis algorithms usually work in two passes First, a fasteffect-cause analysis is performed to constrain the circuits region where possible

146 H.-J Wunderlich and S Holstculprits may be located Second, for each of the possible fault sites, a cause-effectsimulation is performed for identifying those faults, which match the real observedbehavior (Desineni et al 2006;Amyeen et al 2006) The resolution of a test set cor-responds to the number of faults which cannot be distinguished any further (Veneris

et al.2004;Bartenstein 2000;Bhatti and Blanton 2006) The main drawback of thecause-effect paradigms is the dependency on a fault model

5.4.2 Fault Dictionaries vs Adaptive Diagnosis

Cause-effect diagnosis can be speeded up, if for each fault and each failing patternthe erroneous output is determined by simulation and then stored in a dictionary(Pomeranz and Reddy 1992) Even after an effect-cause pass, the size of such adictionary may explode, and significant research effort has been spent for reducingthe size of fault dictionaries (Boppana et al 1996;Chess and Larrabee 1999;Liu

et al.2008) During debug and during diagnosis of first silicon, there exists an ficient alternative to precomputed fault dictionaries in so-called adaptive diagnosis(Gong and Chakravarty 1995)

ef-Here, we use faulty and fault free responses of the device under diagnosis (DUD)

in order to guide the automatic generation of new patterns for increasing the lution A pattern analysis step extracts information from responses of the DUD andaccumulates them in a knowledge base This knowledge in turn guides an automatictest pattern generator (ATPG) to generate relevant patterns for achieving high di-agnostic resolution Such a diagnostic ATPG does not rely on a precomputed faultdictionary, and significant memory savings are obtained The loop ends, when anacceptable diagnostic resolution is reached (Fig.5.5) The definition of the exactabort criterion depends on the number and confidence levels of fault candidates Inthe subsequent sections we present the ‘Partially Overlapping Impact couNTER’(POINTER) approach (Holst and Wunderlich 2009)

reso-5.4.3 Pattern Analysis

In this section, we present a method to analyze the behavior of the DUD for a giventest set and a measure to quantify how well it is reflected by a certain CLF TheSLAT paradigm will be just the special case of a perfect match for one pattern Let

FM(f) be a fault machine, i.e the circuit with stuck-at faultf injected For each testpatternt 2 T , we define the evidence

e.f; t/ D t;  t t/

as tuple of natural numberst;  t t2 N (see Fig.5.6) where:

5 Generalized Fault Modeling for Logic Diagnosis 147

Fig 5.6 Definition of evidence

tis the number of failing outputs where both the DUD and the fault machine

FM match It can be interpreted as the number of predictions by assuming faultf

148 H.-J Wunderlich and S HolstFor a SLAT test patternt, the evidence will provide maximum t and t D

t D 0 as this fault explains all the errors and there is no single stuck-at fault with

a higher number of predictions

The evidence of a faultf and a test set T is

e.f; T / D T; T T/; with

T DXt2T

t;

T DXt2T

 t; and

t2T t

Again, if the real culprit is indeed the stuck-at faultf , we get T T D 0 and

If the fault in the DUD is not always active due to nondeterministic ior or some unknown activation mechanism, the measure still provides consistentevidences

behav-For instance, let f0 be a slow to rise transition fault For some patterns t,fault f0 will appear as a stuck-at 0 fault, for others it is not observable In thiscase, e.f; t/ D t;  t t/ provides t  Qt for all the other evidences

e Qf ; t/ D  Qt; Q t t/ As a consequence, we have T QT for all evidences

e Qf ; T / and the evidence e.f; T / still contributes information for locating the fault.However, the value T will not be zero anymore and can be used for ranking faultcandidates

Now we definetD minft;  tg and T D P

t2Tt.Under the single fault assumption, letf be a stuck-at fault which models at least

a part of the DUD behavior for some patterns under some conditions If the tions are satisfied for a patternt 2 T , the set of failing outputs of FM(f) corresponds

condi-to the fails of the DUD and there is no misprediction ( t D 0/ Otherwise, the

failing outputs of FM(f) and DUD are disjoint (t D 0/ Hence, all tand also

T are zero for faultf If there is a pattern t with t > 0 like in Fig.5.6, thecorresponding conditional stuck-at is not a single fault candidate When assumingmultiple faults, we observe that mutual fault masking is rather rare, and ranking thestuck-at fault according to the size ofT provides a good heuristic

5 Generalized Fault Modeling for Logic Diagnosis 149

Table 5.2 Fault models and

Stuck-at, more fault sites present 0 >0 0 Single conditional stuck-at >0 0 0 Cond stuck-at, more fault sites

present

>0 >0 0 Delay fault, i.e long paths fail >0 0 >0

This fault model independent pattern analysis approach is able to identify circuitparts containing arbitrary faulty behavior However, if the behavior of the DUD can

be explained using some classic fault models, certain evidence forms are observed.Table5.2shows suspect evidences for some classic models

If T, T andT are all zero, a single stuck-at fault explains the DUD behaviorcompletely If T andT are zero, a faulty value on a single signal line under some

fault explains a subset of all fails, but some other faulty behavior is present in theDUD These other fault sites are independent from the stuck-at fault at hand, i.e.for each pattern an output is either influenced by the stuck-at fault only or by someother fault sites With onlyT D 0, a faulty value on the corresponding single signalline explains a part of DUD behavior and more fault sites are present again If only

T is zero, the suspect fails are a superset of DUD fails

If all suspects show positive values in all components T, T,T, the responseswere caused by multiple interacting fault sites, and all simplistic fault models wouldfail to explain the DUD behavior

For further analysis, the evidences in the knowledge base are ordered to create aranking with the most suspicious fault sites at the beginning (lowest rank) Firstly,evidences are sorted by increasingT, i.e

For a brief example of the pattern analysis approach, consider the circuit in Fig.5.7

It contains two gates and four exemplary stuck-at faults for fault simulation.The exhaustive test set and the response from the DUD are shown in the first twocolumns of Table5.3 The erroneous bits are shown in bold, the DUD has failed onoutput x in the third pattern

150 H.-J Wunderlich and S Holst

Fig 5.7 Circuit model for

Table 5.3 Syndrome and

result from stuck-at fault

Table 5.4 Evidences and

is derived for the other stuck-at faults as well; Table5.4shows the result

All evidences showT D 0, so the ranking procedure continues with T Only

f2has positiveT, so this fault is ranked above all other faults The other faults areranked by increasing T The top-ranked evidencef2shows positiveT and positive

T Therefore, none of the simulated faults can explain the syndrome completely, but

f2explains a subset of all fails This leads to a CLF of the forma ˚ Œa  cond withsome arbitrary condition

5.4.4 Volume Diagnosis and Pattern Generation

If the resolution provided by the evidences of a test pattern setT is not sufficient ing adaptive diagnosis or design debug, we have the option to use the evidences forguiding further diagnostic ATPG In volume diagnosis, the pattern set is fixed, and

dur-we have to extract as much diagnostic information as possible from rather limitedinformation Usually, only the firsti failing patterns are recorded, and in addition,all the passing patterns up to this point can be used for diagnosis

5 Generalized Fault Modeling for Logic Diagnosis 151The number of suspects reported by logic diagnosis must be limited in order

to be used for volume analysis If the number of suspects exceeds a parameterk,significance for certain flaws is hardly obtained and further analysis may be tooexpensive If diagnosis successfully identified the culprit, the rank describes theposition of the corresponding evidence within the ordered list

For each faultf with e.f; T / D T; T T/ we have TC T > 0, if T detects

f Otherwise, f may be undetected due to redundancy, or T must be improved todetectf

Even if there are no suspects withT > 0, the possible fault sites are ranked

by T This way, multiple faults on redundant lines can be pointed out For thespecial case of T D 0, at least a subset of DUD failures can be explained with anunconditional stuck-at fault

The faults withe.f; T / D T; T T/ and T > 0 are the suspects, and bysimple iteration over the ranking, pairs of suspectsfa; fbare identified with equalevidencese.fa; T / D e.fb; T / To improve the ranking, fault distinguishing pat-terns have to be generated (Veneris et al 2004;Bartenstein 2000) and applied to theDUD To reduce the number of suspects and the region under consideration further,diagnostic pattern generation algorithms have to be employed which exploit layoutdata (Desineni et al 2006)

5.5 Evaluation

5.5.1 Single Line Defects

The fault machine for a stuck-at faultf at a line a will mispredict, if the condition ofthe CLFa ˚ Œcond  is not active while the CLF is actually modeling the defectivebehavior of line a We split the conditions into cond D cond0 _ cond1 withcond0D Na ^cond and cond1D a^cond Now, a˚cond0models a conditionalstuck-at 1 fault anda ˚ Œcond1 models a conditional stuck-at 0 fault

The unconditional stuck-at 0 fault at linea explains all the errors introduced by

a ˚ Œcond1, and there is no unconditional fault which can explain more errors.The same argument holds for the stuck-at 1 fault at linea and a ˚ Œcond0 As aconsequence, assuming faults at linea will explain all the errors, and there is no linewhere assumed unconditional faults could explain more errors However, there may

be several of those lines explaining all the errors, and the ranking explained in thesection above prefers those with a minimum number of mispredictions

In ? (?) the calculus described above is applied to large industrial circuits up to 1

million of gates, and analysis of stuck-at faults was used for validating the method.For a representative sample of stuck-at faults, the ranked lists of evidences are gen-erated, and for all the fault candidatesf with e f; T / D T; 0; 0/ and a maximumnumberT of predictions, additional distinguishing patterns are generated as far aspossible

152 H.-J Wunderlich and S HolstEven for the largest circuits, an average rank better than 1.2 was obtained, andthe real culprit was most often on top of the list Only in cases where distinguishingpatterns could not be generated and the faults seemed to be equivalent, multipletrials were required.

If volume diagnosis is performed, the test set cannot be enhanced and only a ited number of failing patterns is observed By storing eight failing pattern outputs

lim-at maximum, the method described above puts the real culprit in average lim-at rank1.5 within the candidate fault list This value is highly sufficient for deciding aboutfurther adaptive diagnosis in a second step

The conditions for single stuck-at faults are rather simple, and diagnosis of morecomplex single line faults is more challenging An example which fits for both logicdebug and complex CMOS cells is the analysis of gates of a wrong type For in-stance, the exchange of ana D b OR c by an a D b AND c is described by theCLFa ˚ Œb ˚ c Experiments are reported about randomly changing the gate typewhile the rank of the real culprit is still better than 1.5 on average

Similar results are known, if timing has to be considered in the activating tion of the CLF An example is crosstalk fault as described above where the rank ofthe real culprits still remained at the top level

condi-5.5.2 Multiple Line Defects

If multiple lines are faulty, the corresponding fault effects may mask each other

As a consequence, predictions and mispredictions on an actual CLF may be fected in the presence of other active CLFs Yet, it is known that test sets for singlestuck-at faults are able to detect a large part of multiple stuck-at faults The samereasoning does also hold for CLFs, however, it is not any more true that the (uncon-ditional) stuck-at fault at one of the defect lines always explains the highest number

af-of errors

The reasonings described above form just a heuristic and still works in a ratherefficient way as evidenced by the results reported The 4-way bridges discussedabove affect two lines, and just by looking only into 8 failing output patterns thealgorithm described above points to the defect region with an average rank of 2

5.6 Summary

Faults in circuits, those implemented in modern technology, show a more and morecomplex behavior Diagnosis algorithms cannot assume any more a simplified faultmodel but have to do both locating the flaws in the structure and layout and extract-ing the faulty behavior at these lines The chapter introduced a method to modelfaulty behavior of defective lines sufficiently precise for debug and diagnosis

5 Generalized Fault Modeling for Logic Diagnosis 153The method can be used for implementing an effect-cause analysis and allowsidentifying faults sites under all technology dependent fault models like delay faults,opens, bridges or even more complex functional faults.

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