Models in Hardware Testing- P2 pot

In nanometer technologies, it has been shown how, in the presence of an interconnect full open defect due to the impact of gate leakage currents, a transient evolution is induced in the

The history effect must be minimized when performing a delay test Otherwise,

resistive open defects may escape the test For this reason, when a test is applied to a

specific target net in order to test for a rising (falling) transition, the net must remain

at a low (high) logic value for a sufficient number of cycles before the initializationpattern is applied In this way, it is assured that the target node covers the maximumvoltage excursion to reach its final logic state

Finally, another factor is known to influence the detectability of resistive open

defects, i.e the dynamic behavior of neighboring lines coupled to the defective line.Figure1.12shows how the largest delay was obtained when the neighboring linesunderwent the opposite transition related to the defective line In fact, the effectivecapacitance between two nets depends on their state as well as on the skew betweenthe transitions generated on every line Let us assume that CNiis the capacitance be-tween the neighboring line and the defective line when both lines are in a quiescentstate In the case of a null skew, when a transition is generated in the defective line,the effective capacitance

(1.8)

According to Eq.1.8, obtaining the largest delay caused by a resistive open defect

requires maximizing the total effective capacitances between the defective line andits neighboring lines

Although usually applied to resistive opens, delay considerations can also be useful for interconnect full open defects In nanometer technologies, it has been shown how, in the presence of an interconnect full open defect due to the impact

of gate leakage currents, a transient evolution is induced in the floating line until itreaches the steady state, which is determined by the technology and the topology

of the downstream gate(s) Experimental measurements show that these transient

Fig 1.19 IDDQ time-dependent behavior of a 0:18 m technology defective device ( Arum´ı

et al 2008b )

evolutions are in the order of seconds for a 0:18 m technology, as depicted inFig.1.19 The evolution of the floating line was observed by monitoring the currentconsumption of the circuit over time This evolution influences the logic behavior

of the floating line since its interpretation changes from logic 1 to logic 0 after fewseconds In this technology, these evolutions are too slow for testing purposes How-ever, analytical and simulation results report that these transient evolutions might bereduced by several orders of magnitude for future technologies, opening a new field

of study on the detectability of such defects

1.3.1.3 Alternative Techniques for the Detectability of Interconnect

Open Defects

The modification of power supply voltage.VDD/ especially by High Voltage (HV)testing (Li et al 2001;Kruseman and Heiligers 2006) has been successfully applied

to detect interconnect open defects The key in using high voltages stems from the

idea that the delay added by a resistive open located in the interconnection is

al-most insensitive to power supply voltage However, circuit delay depends on powersupply voltage, increasing as VDDdecreases Therefore, for high voltages, althoughthe delay added by the defect is approximately the same, the circuit delay is smallerand consequently the defect delay becomes more observable Figure1.20shows theshmoo plot for a defect free device in comparison with two defective devices with

an interconnect resistive open of 1 and 3 M, respectively

In the presence of an open, the exact voltage-delay relationship depends strongly

on the open location In the work byYan and Singh(2005), the difference betweentransistor-related defects and resistive interconnect defects was reported by sweep-ing the power supply value Simulations were conducted for defective circuits atdifferent VDDvalues The results showed that the delay added by transistor-relateddefects increased non-linearly when decreasing the power supply value whereas thishad little impact on the delay added by resistive interconnect defects

20 J Figueras et al.

Fig 1.20 Pass/fail boundary

(Shmoo Plot) for defect-free

silicon and with an

interconnect open resistance

of 1 and 3 M , ( Kruseman

and Heiligers 2006 )

In some cases, high voltages are also used as voltage stress testing for ity screening (Kawahara et al 1996;Chang and McCluskey 1997;Aitken 2002).Stressing the device with high voltages may improve the detection of some defects.This technique is particularly useful for detecting oxide thinnings and via defects,which shorten device lifetime The goal of stressing devices is to make these flawsevident, causing via defects to become opens and oxide thinnings to become oxidebreaks However, two parameters must be thoroughly controlled, i.e., power supplyvoltage and stressing time If any of these two parameters exceeds the allowed limit,defect-free devices could be damaged

reliabil-Observation of quiescent current consumption of the circuit

IDDQmay also beeffective in technologies with reduced background leakage currents (i.e., low non-defective IDDQ) In these circumstances, the detection of interconnect open defectsmay sometimes be possible although this technique is not as useful as for other types

of defects, such as bridges The detection of open defects by IDDQis strongly

depen-dent on cell design and circuit topology Assuming an interconnect full open defect,

if an intermediate voltage is induced on the floating line, the two transistors driven

by the floating line may be in a conduction state, generating a current path fromVDD to GND, and thus resulting in extra current consumption (Singh et al 1995;

Champac and Zenteno 2000)

Temperature can also help to detect resistive opens Assume, as a first

approxi-mation, that the open resistance is not modified with temperature As temperaturedecreases, the dominant effect is usually the increasing mobility, which decreasesthe on resistance of transistors In such situation, the relative importance of the de-lay added by the defect increases Hence, cold testing improves the observability of

resistive opens However, the open resistance does vary with temperature as well.

Therefore, the delay induced by the open changes The temperature coefficient of

the resistance depends on the resistive open material Hence, the delay added by the open may increase or decrease with temperature In fact, resistive opens may pass

the test at nominal conditions, but can be detected at a temperature different fromthe nominal one For instance, the work ofNeedham et al.(1998) reported a resis- tive open between an interconnect and a via causing a functional failure at 20ıC,which was not detected at room temperature

1.3.2 Detectability of Intra-gate Open Defects

Early research to detect intra-gate open defects was founded on logic-based niques Nevertheless, these cannot always ensure the detectability of such opens.Logic based techniques and alternatives are presented in this section

tech-1.3.2.1 Logic Detectability of Intra-gate Open Defects

As already seen in Section1.2.2, the detectability of stuck open faults depends onthe pattern order The output of the defective gate is in a high impedance state for

at least one input combination In this situation, the output voltage depends on thestate induced by previous patterns Therefore, with the appropriate pattern order,logic testing is suitable for the detection of such defects (Wadsack 1978;Soden

et al.1989)

If an open causes a single floating gate, its detectability depends on several tors (Champac et al 1993,1994;Ivanov et al 2001), namely topological parameters,trapped charge and unpredictable poly-to-bulk capacitance

fac-Cpb The detectability

of the fault can be ensured depending on the Cpbvalue The final value of the put voltage of the affected gate increases with Cpb Therefore, a critical value ofthe unpredictable parameter Cpbcan be defined to detect a single floating gate Thedetectability interval is defined as the range of Cpd values where the open fault can

out-be detected

1.3.2.2 Delay Detectability of Intra-gate Open Defects

Like interconnect resistive opens, intra-gate resistive opens influence the transient

behavior of defective devices In general, the higher the resistance, the larger the

delay Furthermore, the exact location of the intra-gate resistive open also has a

significant impact on the transient behavior of the affected circuit, as analyzed by

Baker et al.(1999) This work considered a0:25 m standard cell library Transistorlevel netlists and interconnect parasitics were extracted from layout to find the criti-cal resistances For resistive drain/source faults, simulation results showed that mostcritical resistances were about 50 k However, for resistive single transistor gatefaults, critical resistances ranged between M and a few tens of M depending onthe duty cycle of the input waveform

In some cases, time considerations can also be useful in the detectability of

intra-gate full open defects For single floating nMOS (pMOS) transistors, a

ris-ing (fallris-ing) transition applied to the defective input may detect the presence of suchfaults provided that the delay is large enough to generate a fault (Ivanov et al 2001).This delay depends on topological parameters and Cpb In general, the higher Cpb,the larger the delay

IDDQtesting is another alternative for detecting intra-gate opens for technologieswith low background leakage currents However, even in these technologies, the ef-ficiency of IDDQtesting is strongly dependent on cell design, circuit topology andopen location For example, the work byChampac et al.(1994) presented the IDDQdetectability of a single floating transistor It was reported that the location of thepoly-break, modeled by the poly-bulk and metal-poly capacitances, determined thedegree of conduction of the floating gate transistor and its detectability by currenttesting For sufficiently high values of the poly-bulk capacitance, the defective tran-sistor may work in the subthreshold region, where it can be modeled as a stuck-opentransistor It is therefore not detectable by an IDDQtest However, for sufficiently lowvalues of the poly-bulk capacitance and sufficient metal track influence, the floatinggate transistor operated above threshold, generating non-negligible IDDQvalues.

Singh et al.(1995) reported the results of an experimental test chip for analyzingthe IDDQdetectability of open defects Open faults were divided into five differentgroups, see Fig.1.21, namely open disconnecting a transistor pair O1/, a singlefloating net belonging to a transistor being the only conduction path to the powerrails.O2/, an open source/drain on the only conduction path to the power rails O3/,

a floating gate in a transistor on one of multiple conduction paths to VDDor GND.O4/, and finally an open source/drain on one of multiple conduction paths to VDD

or GND.O5/ Based on the experimental results, the authors reported that opens O1and O2were the most likely to be detected by a IDDQtest although their detectabilitycould not be ensured for all configurations For opens O4 and O5, if the affected

Fig 1.21 IDDQdetectability

of open defects ( Singh

et al 1995 )

Z B A

transistors were in the off state, it was possible to detect the defect by capturing anintermediate voltage at the floating node due to hazards that may affect the CMOSnetwork Finally, open O3was the most difficult to detect by current testing becausethis class of faults usually had a stuck-at behavior.

Finally, Nigh and Gattiker (2004) reported that IDDQ versus time may giveadditional information about open defects Some defective devices showed time-dependent IDDQ behavior with evolution in the order of seconds The authorsconjectured that this dynamic behavior could be associated with an open defect andthe subthreshold, gate and reverse bias pn junction leakage currents flowing into andout of the affected node

1.4 Diagnosis of Open Defects

Accurate diagnosis of failure sites is important for solving process problems, lyzing failures and improving yields The current diagnosis effort related to opendefects has focused mostly on interconnect opens Accordingly, in this section

ana-we will first analyze the strategies to diagnose interconnect opens folloana-wed by anoverview of the techniques used to diagnose intra-gate opens

1.4.1 Diagnosis of Interconnect Open Defects

One of the first works on diagnosis of interconnect open defects was conducted

byVenkataraman and Drummonds(2000) The proposed methodology was based

on logic information using the net diagnostic model This model takes the ent branches of the defective line into account Let us now look at the example inFig.1.22 The line is composed of stem A and branches B and C The logic errorscaused by a 0/1 error at locations A, B and C are saved in the erroneous observation(EO) sets EO1, EO3and EO5, respectively, as described in Table1.4 Similarly, theerrors caused by a 1/0 error are saved in the sets EO2, EO4 and EO6, respectively.The diagnostic signature EO for stem A is then computed as the union of sets EO1,

differ-EO2, EO3, EO4, EO5and EO6 In the presence of an open on net ABC, only a set of set EO is faulty A path-tracing procedure can be used to identify the logicnets potentially associated with an interconnect open

sub-Fig 1.22 Net diagnostic

model ( Venkataraman and

Drummonds 2000 )

C

Fig 1.23 Segment fault model ( Huang 2002) (a) Target net driving three gates and (b) segment

division according to layout information

In a subsequent work, Liu et al (2002) presented a model-free diagnosisalgorithm for multiple interconnect open faults In the presence of an open fault,this procedure considered the worst case scenario Each fan-out branch of the stemwas assumed to behave randomly, that is, independent of the value on the stem.Hence, every branch could take an arbitrary logic 1 or 0 for each test pattern Aniterative algorithm using X values identified possible faulty locations Subsequently,simulations were carried out to reduce the set of candidates

Unlike these previous works, some recent studies have considered physical formation to improve diagnosis resolution Huang (2002) proposed a diagnosisprocedure using the segment fault model A segment.Si/ is a part of a net based

in-on routing informatiin-on By knowing the layout, the target net can be divided intoseveral segments, as shown in Fig.1.23 Symbolic simulation is performed to findopen segments on the target line The main drawback of this methodology is thatthere are cases where segments are still too long and the open cannot be preciselylocated along the line

In the work bySato et al.(2002), a technique to find open vias by using physicalinformation was proposed The capacitances between the floating net and its neigh-boring lines were taken into account to predict changes in the floating node voltagefor every test pattern (P), as described by Eq.1.9:

E.P / D C1.P /

C1.P/ is the sum of the capacitances between the floating net and coupled structurestied to logic 1 for a specific test pattern, and C0.P/ stands for the sum of the ca-pacitances between the floating net and its coupled structures set to logic 0 for thesame P pattern The patterns exciting the fault are divided into two sets:0and1,where0.1/ is composed of patterns which set the floating net voltage to a value

lower (higher) than the threshold voltage of the downstream gate Assuming that

E.0/ D Œmin E.p/; max E.p/ for 8p 2 0 and E.1/ D Œmin E.p/; max E.p/for 8p 21, to obtain consistent results in the presence of an open defect, Eq.1.10

should be satisfied

This methodology neglected capacitances between internal nodes Its feasibility wasalso limited in situations where the floating net had fan-out and the threshold volt-ages of the inputs of the driven gates were different, since Eq.1.10 may not besatisfied Furthermore, this work focused on open vias only and discarded findingopens due to broken metal tracks

The diagnosis technique presented byZou et al.(2006) was founded on the ment fault model previously proposed byHuang(2002) In this methodology, thesegment model was used as a first step to get the set of potential open segments re-sponsible for the faulty behavior Subsequently, SPICE simulations were carried out

seg-to calculate the input threshold voltages of the driven gates With all this informationand the charge conservation principle, a prediction of the initial trapped charge wasmade According to the above principle, once the initial charge is trapped in thecircuit during the fabrication process, the total amount of charge does not changeand is redistributed among the capacitors when different test patterns are applied, asdescribed by Eq.1.11:

QtrapD Qwire

P; Vfn

In the proposal ofRodr´ıguez-Monta˜n´es et al.(2007a), the target net was dividedaccording to the FOS (Full Open Segment) model to diagnose interconnect full opendefects in long floating lines where the impact of transistor capacitances are low TheFOS model considered any possible location of the open along the line With thismodel, the floating line is partitioned into several segments (Seg i) Segment breaksare caused by a change in the neighborhood layout For the example in Fig.1.24, thetarget line is divided into nine different segments Hence, each segment consists ofthe target line and zero to two neighboring lines since only coupling neighbors be-tween the same metal layer are considered It is therefore possible to extract theparasitic capacitances for every segment easily Given an open location (segment k)and a test pattern (P), the floating line voltage is determined by the parasitic capaci-tances of the segments located after the open, as reported in Eq.1.12

26 J Figueras et al Seg_1

N1

N3Seg_2 Seg_3 Seg_4 Seg_5 Seg_6 Seg_7 Seg_8 Seg_9

Fig 1.24 Segment division according to the FOS model ( Rodr´ıguez-Monta˜n´es et al 2007a )

0 0.2 0.4 0.6 0.8 1

Cupi N

PiDkC1

Cup iC PNiDkC1

This methodology predicts the floating line voltage at the far end of every ment for every test pattern exciting the open fault (the voltage at intermediatelocations within any segment is found by interpolating the voltage results at their endpoints) These predictions were associated with the experimental results obtained onthe tester The voltage predictions for a real defective device of a0:18 m technol-ogy can be seen in Fig.1.25a Patterns generating a floating line voltage interpreted

seg-as logic 1 on the tester are plotted in dotted lines, whereseg-as patterns generating alogic 0 in the floating line are plotted in plain lines To find a location where the pre-dicted results are consistent with the experimental results obtained on the tester, the

predicted voltage of the floating line for the dotted patterns must be above those forthe plain patterns Note that the methodology is based on relative predictions of thefloating line Thus, uncertainty due to the trapped charge and the threshold voltage

of the downstream gate is eliminated The predictions in Fig.1.25a are consistentfor two ranges of locations (A and B) The rest of locations can be discarded.Based on the same methodology, the authors also proposed, when feasible, theuse of IDDQmeasurements to improve the accuracy of diagnosis results The pre-dictions of the floating line voltage allowed, in turn, the extra current consumed bythe downstream gate to be predicted by SPICE simulations The predicted currentswere compared with the results obtained from the IDDQtest, and the correlation co-efficient between the predicted and measured currents was calculated Results forthe same defective device are shown in Fig.1.25b By combining both logic andcurrent results, the authors determined that the most likely location for the open isregion A (at the beginning of the defective net, close to the driver)

Liu et al.(2007) presented a diagnosis methodology minimizing the layout formation to locate open vias Depending on the interpretation of the floating linevoltage, one of the following equations must be satisfied:

in-VFL.P / D C1.P /

CTOT VDDC VQo> Vth.P /

VFL.P / D C1.P /

CTOT VDDC VQo< Vth.P / (1.13)where C1.P/ is defined as in Eq.1.9 Considering that C1.P/ is pattern dependent,

it is possible to rearrange the previous inequalities in the following way:

Ca1.P /VDDC k  Vth.P /Ctot> 0

Ca1.P /VDDC k  Vth.P /Ctot< 0 (1.14)

Ca1.P/ is the part of C1.P/ referring to the neighboring coupling capacitances tied

to logic 1 for pattern P, and k is a pattern independent variable depending on Qoandother known variables These inequalities are linear Hence, for every applied testpattern, an inequality like those in Eq.1.14is obtained Then, given n test patterns,

n inequalities are reported A solver can be used to determine if these inequalitieshave a solution If not, the suspected via is removed from the list

Little research has addressed the diagnosis of resistive open defects since these

are intrinsically included in methodologies for delay fault diagnosis However,

James and McCluskey(2005) proposed a methodology focused on the diagnosis

of resistive opens, in particular based on the transition fault model Transition faults

are timing failures large enough to make the path delay through which the fault ispropagated exceed the clock interval Figure1.26shows the fourteen possible re- sistive open locations in a NAND gate The eleven intra-gate resistive open defects

.R1–R11/ can be modeled as single-transition faults The inter-gate resistive open

defects.R12–R14/ cannot be modeled as any single-transition fault They must be

28 J Figueras et al.

Fig 1.26 Resistive open

faults in a NAND gate

are built for every gate and resistive open to find the fault gate input sequence.

1.4.2 Diagnosis of Intra-gate Open Defects

Stuck-open fault diagnosis has also been investigated In the work by Li and

McCluskey (2002), two tables were built for every type of gate The first containedthe gate input pair to excite stuck-open faults The second listed input values of thegates for every test pattern applied on the tester With this information, the possiblesequence behavior of stuck-open defects was considered during diagnosis

In the proposal by Fan et al.(2005), a transformation method was developedwhere transistors were replaced by a gate-level equivalent so that a stuck-open faultwas represented with a stuck-at fault, as described in Fig.1.27 For n-transistors(p-transistors), the idea was to propagate the 0 (1) voltage from the source to the

drain when the transistor was on This transformation method was the basis for

a stuck-at fault diagnosis tool to be directly applied to the diagnosis of intra-gatestuck-open faults

1.5 Summary

Open defects are very common and have been studied over a wide range of CMOStechnologies The first works were limited to stuck-open faults, which representonly a small part of the open defects that may affect CMOS devices For this reason,extensive work was subsequently dedicated to the study of other classes of opendefects, such as single-floating transistors and interconnect open defects The latterare currently the most likely open defects to occur since interconnection structuresoccupy a significant part of the total area of VLSI chips

Process variations and partial opens have an increasing impact on nanometer

technologies, consequently resistive opens have dominated most research during

the last years The continuous CMOS scaling trend causes new failure mechanisms.Among these, the influence of leakage currents on the behavior of open defects hasopened a new field of research, which is expected to contribute new techniques fortest and diagnosis of these defects

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informa-Chapter 2

Models for Bridging Defects

Test and Diagnosis

Michel Renovell, Florence Azais, Joan Figueras, Rosa Rodr´ıguez-Monta ˜n´es, and Daniel Arum´ı

Abstract Bridging defects are responsible for a large percentage of failures in

CMOS technologies and their impact in nanometer technologies with highly denseinterconnect structures is expected to increase In this chapter, a survey of the keydevelopments in modeling bridging defects and their implications in test and diag-nosis are presented An overview of the historical developments of these modelsfrom the “wired AND/OR” and “voting” models to more realistic proposals takinginto consideration the resistance values of the bridge are presented The logic de-tectability of bridging defects considering the resistance of the bridge assuring itsdetectability is explored The concept of Analogue Detectability Interval (ADI) aswell as its applicability to increase the quality of the vectors detecting these de-fect classes is introduced Quality of electronic circuits and systems requires theavailability of effective diagnosis techniques The basic concepts of logic as well ascurrent-based (IDDQ) diagnostic strategies are included in this chapter

Keywords VLSI  Test  Diagnosis  Defect  Short  Bridging defect  CMOS

 Realistic model  Analogue detectability interval

2.1 Introduction

Traditionally, test generation relies on fault models to produce tests that are expected

to identify defects such as unintended bridges and opens Test generation does notdirectly target defects for two main reasons Firstly, many defects are not easy toanalyze and no model exists to completely describe their behaviour Secondly, there

is a variety of possible defects in a circuit Since available resources (like memory)

M Renovell ( ) and F Azais

LIRMM-CNRS, 161 rue ada, 34392 Montpellier, France

e-mail: renovell@lirmm.fr , azais@lirmm.fr

J Figueras, R Rodr´ıguez-Monta˜n´es, and D Arum´ı

Universitat Polit`ecnica de Catalunya (UPC), Electronic Engineering Dpt ETSEIB,

Diagonal 647, 08028 Barcelona, Spain

e-mail: figueras@eel.upc.es , rosa@eel.upc.edu , arumi@eel.upc.edu

H.-J Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum

in Honor of Christian Landrault, Frontiers in Electronic Testing 43,

DOI 10.1007/978-90-481-3282-9 2, c  Springer Science+Business Media B.V 2010

33