ECAD and VLSI lab manual

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ECAD & VLSI LAB

MANUAL FOR B.TECH –ECE IV-1 SEMESTER

BY

SATHISH DADI M.TECH DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

IV Year B.Tech ECE - I Sem L T/P/D C 0 -/3/- 2

E-CAD AND VLSI LAB

List of Experiments

Design and implementation of the following CMOS digital/analog circuits using Cadence /

Mentor Graphics / Synopsys / Equivalent CAD tools The design shall include Gate-level

design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS)

E-CAD programs:

Programming can be done using any complier Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools

1 HDL code to realize all the logic gates

2 Design of 2-to-4 decoder

3 Design of 8-to-3 encoder (without and with parity)

4 Design of 8-to-1 multiplexer

5 Design of 4 bit binary to gray converter

6 Design of Multiplexer/ Demultiplexer, comparator

7 Design of Full adder using 3 modeling styles

8 Design of flip flops: SR, D, JK, T

9 Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter

10 Finite State Machine Design

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VLSI programs:

1 Introduction to layout design rules

2 Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:

 Basic logic gates

CMOS inverter

CMOS NOR/ NAND gates

CMOS XOR and MUX gates

CMOS 1-bit full adder

Static / Dynamic logic circuit (register cell)

Latch

Pass transistor

3 Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths

4 Introduction to SPICE simulation and coding of NMOS/CMOS circuit

5 SPICE simulation of basic analog circuits: Inverter / Differential amplifier

6 Analog Circuit simulation (AC analysis) – CS & CD amplifier

7 System level design using PLL

Note: Any SIX of the above experiments from each part are to be conducted (Total 12)

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EXPERIMENT -1 Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL -

Electronics Design Automation Tools used:

i) Xilinx Spartan 3E FPGA +CPLD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow

fromSimulation to Implementation to download onto FPGA)

v) JTAG cable vi) Adator 5v/4A

Boolean equations:

And Gate:Y = (A.B)

Or Gate: Y = (A + B) Nand Gate: Y = (A.B)’

Nor Gate: Y = (A+B)’

Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’

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Block diagram:

Verilog program for AND gate:

// And Gate (In Dataflow, behavioral Modeling):

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c = 1’b1;

endendmodule

Verilog program for OR gate:

//Or gate(Dataflow, behavioral modeling):

Module org (a,b,c);

input a,b;

output c;

assign c = a | b;

endmodule

Verilog program for nand gate:

// Nand Gate (In Dataflow modeling):

Module nandg (a,b,c);

input a,b;

output c;

assign c = ~(a & b);

endmodule

Verilog program for NOR gate:

// Nor Gate (In Dataflow modeling):

Module norg (a,b,c);

input a,b;

output c;

assign c = ~(a | b);

endmodule

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Verilog program for XOR gate:

Xor gate(In Dataflow modeling):

Module xorg (a,b,c);

Verilog program for XNOR gate:

//Xnor Gate (In Dataflow modeling):

Module xnorg (a,b,c);

input a,b;

output c;

assign c = ~(a ^ b);

endmodule

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VHDL PROGRAM FOR ALL LOGIC GATES:

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Test Bench: programmable digital gates library ieee;

use ieee.std_logic_1164.all;

entity tb_digital_gates is end tb_digital_gates;

architecture behav1 of tb_digital_gates is

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EXPERIMENT -2 Design of decoder usingVerilog HDL -

Aim:

1 Perform Zero Delay Simulation of decodere in Verilog using a Test bench

2 Synthesize each one of them on two different EDA tools

Apparatus required:

i) Xilinx Spartan 3E FPGA +CPLD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow

v) JTAG cable vi) Adator 5v/4A Block diagram:

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****************************************************

module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en);

output Y3, Y2, Y1, Y0;

input A, B;

input en;

reg Y3, Y2, Y1, Y0;

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always @(A or B or en) begin

// Instantiate the Decoder (named DUT {device under test})

decoder_2to4 DUT(Y3, Y2, Y1, Y0, A, B, en);

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#1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B,"

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3’b110: Y = 4’b0010;

3’b111: Y = 4’b0001;

default: Y = 4’b0000;

endcase endmodule

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// Setup the monitoring for the signal values

initial

begin

$monitor($time,"C=%b, =%b,A=%b ,Q=%b%b%b%b%b%b%b%b\n",C,B,A,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7);

end // Stimulate inputs

**********************************************************

module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en);

output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;

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( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 : ( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 : 8'b1111_1111;

Endmodule //TESTBENCH

module Test_decoder_3to8;

wire Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;

reg A, B, C;

reg en;

// Instantiate the Decoder (named DUT {device under test})

decoder_3to8 DUT(Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0, A, B, C, en);

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$display("t=%t en=%b ABC=%b%b%b Y=%b%b%b%b%b%b%b%b",

endmodule

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//USING FOR LOOP

module Decode3To8For(yOut, aIn, enable);

for(k=0;k<8;k=k+1)

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begin if(aIn == k)

yOut[k] = 0;

else

yOut[k] = 1;

end end

end

endmodule BCD decoder

This circuit has four binary inputs and ten binary outputs The ith output is asserted if the binary inputs are the binary number i, where 0 ≤ i ≤ 9 The inputs will never be a number greater

than 9 (or if they are, we don’t care what the output is)

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8: Y[8] = 1;

9: Y[9] = 1;

default: Y = ’bx;

endcase end

endmodule

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EXPERIMENT -3 Design of 8-to-3 encoder (without and with parity) usingVerilog HDL -

i) Xilinx Spartan 3E FPGA +CPLD Board ii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST iii) Synthesis tool or LeonardoSpectrum Synthesis Tool

iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow

v) JTAG cable vi) Adator 5v/4A THEORY:

An encoder is a digital circuit which performs the inverse of decoder.An encoder has 2^N input lines and N output lines.In encoder the output lines genrate the binary code corresponding to input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output lines

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Y2 = w7 + w6 + w5 + w4 Y1 = w7 + w6 + w3 + w2 Y0 = w7 + w5 + w3 + w1

Verilog program for 8x3 encoder:

module encoder (din, dout);

else if (din==8'b00000010) dout=3'b001;

else if (din ==8'b00100000) dout=3'b101;

else dout=3'bX;

end endmodule

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Priority Encoders

 A priority encoder has n inputs and ⎡log2n⎤ outputs

The output signals are a binary number such that its valueis the highest index value of all the inputs that are 1

� Example: 4-to-2 priority encoder:

y1 = w3’•w2 + w3 y2 = w3’•w2’•w1 + w3

z = w0 + w1 + w2 + w3 Priority encoder is a special type of encoder in which multiple bits at the input can be asserted

The response at the output is however defined by the priority rule, defined previously Priority encoders have vast application in different client-server systems In client-server systems decision is made to grant a service based on the priority of any specific client

Here is a verilog code for an 8:3 priority encoder It grants the highest priority to the "most left sided bit in the input word" For example in data word "00010101" the highest priority is carried

by the most left sided one, appearing at the fourth (counting from left side) So all the other bits that come next to it will be discarded or in other words will not be taken into account Verilog implementation has been done using "casex" statement

an 8-bit priority encoder This circuit basically converts a one-hot encoding into a binary

representation If input n is active, all lower inputs (n-1 0) are ignored Please read the description of the 4:2 encoder for an explanation

x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0 -

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always @ (data) begin

casex (data) 8'b1xxxxxxx : code=7;

8'b01xxxxxx : code=6;

8'b001xxxxx : code=5 8'b0001xxxx : code=4;

Verilog program for 4 x2 priority encoder module priority (W, Y, z);

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end endmodule

Verilog code for a 3-bit 1-of-9 Priority Encoder

module priority (sel, code);

input [7:0] sel;

output [2:0] code;

reg [2:0] code;

always @(sel) begin

if (sel[0]) code = 3’b000;

else if (sel[1]) code = 3’b001;

else code = 3’bxxx;

end endmodule

Pri-Encoder - Using if-else Statement

-

module pri_encoder_using_if ( binary_out , // 4 bit binary output encoder_in , // 16-bit input

enable // Enable for the encoder );

output [3:0] binary_out ; input enable ;

input [15:0] encoder_in ;

reg [3:0] binary_out ;

always @ (enable or encoder_in) begin

binary_out = 0;

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if (enable) begin

if (encoder_in[0] == 1) begin binary_out = 1;

end else if (encoder_in[1] == 1) begin binary_out = 2;

end end end endmodule

Encoder - Using assign Statement

module pri_encoder_using_assign ( binary_out , // 4 bit binary output encoder_in , // 16-bit input

enable // Enable for the encoder );

output [3:0] binary_out ; input enable ;

input [15:0] encoder_in ;

wire [3:0] binary_out ;

assign binary_out = ( ! enable) ? 0 : ( (encoder_in[0]) ? 0 :

(encoder_in[1]) ? 1 : (encoder_in[2]) ? 2 : (encoder_in[3]) ? 3 :

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(encoder_in[4]) ? 4 : (encoder_in[5]) ? 5 : (encoder_in[6]) ? 6 : (encoder_in[7]) ? 7 : (encoder_in[8]) ? 8 : (encoder_in[9]) ? 9 : (encoder_in[10]) ? 10 : (encoder_in[11]) ? 11 : (encoder_in[12]) ? 12 : (encoder_in[13]) ? 13 : (encoder_in[14]) ? 14 : 15);

endmodule

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EXPERIMENT -4 Design of multiplexer usingVerilog HDL

-

Aim:

3 Perform Zero Delay Simulation of multiplexerin Verilog using a Test bench

4 Synthesize each one of them on two different EDA tools

Apparatus required:

vii) Xilinx Spartan 3E FPGA +CPLD Board viii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST ix) Synthesis tool or LeonardoSpectrum Synthesis Tool

x) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow

xi) JTAG cable xii) Adator 5v/4A Block Diagram:

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module mux21(q, sel, a, b);

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module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

not (s0n, s0);

and (y0, i0, s1n, s0n);

and (y1, i1, s1n, s0);

and (y2, i2, s1, s0n);

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and (y3, i3, s1, s0);

or (out, y0, y1, y2, y3);

endmodule /////TEST BENCH module stimulus;

// Declare variables to be connected to inputs reg IN0, IN1, IN2, IN3;

#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);

****************************************

module mux41(q, sel, a, b, c, d);

parameter WID=16;

input[1:0] sel;

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mux21n #(WID) M0(tmp1, sel[0], a, b);

mux21n #(WID) M1(tmp2, sel[0], c, d);

mux21n #(WID) M2(q, sel[1], tmp1, tmp2);

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mux_4to1 DUT(MuxOut, A, B, C, D, sel);

//This block generates a clock pulse with a 20 ns period always

#10 clk = ~clk;

//This initial block will provide values for the inputs // of the mux so that both inputs/outputs can be displayed initial begin

@(negedge clk) //will wait for next negative edge of the clock (t=120)

$finish; // to shut down the simulation end //initial

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// this block is sensitive to changes on ANY of the inputs and will // then display both the inputs and corresponding output

always @(A or B or C or D or sel)

#1 $display("At t=%t / sel=%b A=%h B=%h C=%h D=%h / MuxOut=%h",

$time, sel, A, B, C, D, MuxOut);

wire lo8, hi8, out1;

// Instantiate the 8-to-1 muxes and the 2-to-1 mux mux_8to1 mux_lo (lo8, In[7:0], sel[2:0]);

mux_8to1 mux_hi (hi8, In[15:8], sel[2:0]);

mux_2to1 mux_out (out1, lo8, hi8, sel[3]);

// equate the wire out of the 2-to-1 with

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// the actual output (Y) of the 16-to-1 mux assign Y = out1;

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In = 16'b1100_0011_1111_1111; // time = 80 sel = 4'b1000;

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Demultiplexor

A demultiplexor is the converse of a multiplexor It takes one input and directs it to any of N inputs, based on the number specified in the select lines It could be captured either using procedural code or continuous assignment Both of the following statements describe identical behavior

out2 = 14’h0; /* default = 00 */

for (I=0; I<=7; I=I+1)

if (I == sel) begin out2[I] = in1[0];

out2[I+1] = in1[1];

end end

Tiêu đề	ECAD and VLSI Lab Manual
Tác giả	Sathish Dadi M.TECH
Trường học	Jawaharlal Nehru Technological University Hyderabad
Chuyên ngành	Electronics & Communication Engineering
Thể loại	lab manual
Thành phố	Hyderabad

Định dạng
Số trang	125
Dung lượng	2,44 MB