Latch and flip flop

Le Dung Faculty of Electronics and Telecommunications Hanoi University of Science and Technology Content • Memory element • Latches • Flip-Flops... Le Dung 11 Hanoi University of Sc

Latches and Flip-Flops

Dr Le Dung

Faculty of Electronics and Telecommunications Hanoi University of Science and Technology

Content

•  Memory element

•  Latches

•  Flip-Flops

A device with exactly two stable states

Bistable multivibrator circuit

Q1 on  Q2 off

Q1 off  Q2 on

2 stable states

as

a memory element can store one bit

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Memory element

1-state

or

0-state

Q

Q

Excitation

inputs

1-state (set):

Q=1, Q=0 0-state (reset):

Q=0, Q=1 Inhibited-state:

Q = Q

Set

Reset

Set Reset Clock

Excitation inputs

Latches

•  SR latch (Set-Reset latch)

+ with NOR structure

+ with NAND structure

•  Gated SR latch

•  D latch (Delay or Data latch = transparent latch)

•  Some applications of the latches (1) (2) (3)

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S R Q’ (next)

0 0 Q (latch)*

0 1 0 (reset)

1 0 1 (set)

1 1 Q’=Q’=0

(Inhibited)

* Latch = No change

SR latch

S, R active “High”

NOR structure

Set

Q=1,Q=0

Reset

Q=0,Q=1

X

Q=Q

SR=10 SR=01 SR=00

SR=10

SR=00

SR=01

State diagram

Set-Reset Latch with NAND structure

S R Q’ (next)

0 0 Q’=Q’=1

(Inhibited)

0 1 1 (set)

1 0 0 (reset)

1 1 Q (latch)*

* Latch = No change

SR latch

S, R active “Low”

NAND structure

Set

Q=1,Q=0

Reset

Q=0,Q=1

X

Q=Q

SR=01 SR=10 SR=11

SR=01

SR=11

SR=10

Inhibited

State diagram

(Moore)

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NOR SR Latch

S, R active “High”

Q’=Q’=0

(Inhibited)

1

1

1 (set)

0

1

0 (reset)

1

0

Q (latch)*

0

0

Q’ (next)

R

S

(Illegal)

Q’ = S + RQ

Gated SR Latch

* Hold = No action

Gated SR latch E S R Q’ (next)

0 x x Q (hold)*

1 0 0 Q (latch)

1 0 1 0 (reset)

1 1 0 1 (set)

1 1 1 Inhibited

E,S,R active “High”

Set

Q=1,Q=0

Reset

Q=0,Q=1

X

Q=Q

ESR=110 ESR=101 0xx,

110

Inhibited

State diagram

(Moore)

0xx,

101

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D Latch

E D Q’ (next)

0 x Q (hold)*

1 0 0 (reset=store 0)

1 1 1 (set=store 1)

Set

Q=1,Q=0

Reset

Q=0,Q=1

ED=11

ED=10

0x,

11

0x,

10

Store 1 Store 0

Data or Delay latch

= transparent latch

Some applications of the latches (1)

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(App 1) Debounce a mechanical switch

Some applications of the latches (2)

(App 2) LED detect alarm system

Some applications of the latches (3)

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(App 3) 74LS75 Quad D latch module with enable

Flip-Flops

•  Clock signals

•  Clocked flip-flops

+ Master-Slave Flip-Flop (Pulse-triggered FF)

+ Edge-triggered Flip-Flop

•  SR Flip-Flop

•  JK Flip-Flop

•  D Flip-Flop

•  T Flip-Flop

•  Some applications of the flip-flops(1) (2) (3)

Clock signals

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Clocked Flip-Flops

Master-Slave Flip-Flops

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Edge-triggered Flip-Flops

SR Flip-Flop (active with PGT)

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JK Flip-Flop

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JK Flip-Flop (active with NGT)

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Internal Circuitry of JK Flip-Flop

Feedback

Feedback

Pulse-triggered JK Flip-Flop

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D Flip-Flop

Make D Flip-Flop from JK Flip-Flop

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Clocked T Flip-Flop

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Asynchronous set and reset (2)

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JK-FF with Preset and Clear inputs

Asynchronous set and reset (4)

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T-FF with Preset and Clear inputs

+ Thiết kế các bộ đếm (Counter)

+ Thiết kế thanh ghi dịch (Shift register)

+ Thiết kế mạch dãy

+ Các ứng dụng khác

Some applications of the Flip-Flop (1)

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3 bits Up-Counter

Some applications of the Flip-Flop (2)

Serial shift register