VHDL and verilog user manual

Ngôn ngữ mô tả phần cứng VHDL Lập trình VHDL

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VHDL and Verilog

Simulation User ManualVersion 7.2

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Table of Contents

Preface 9

What Is In This Manual 10

Where to Look for Information 10

Documentation Conventions 12

Related Documentation 13

Lattice Semiconductor 13

Cadence 13

Mentor 13

Viewlogic 13

Synopsys 13

IEEE 13

OVI 14

Model Technology Inc 14

Frontline PureSpeed 14

Part I: VHDL Simulation 15

Chapter 1 Introduction to VHDL Simulation 16

VHDL Directory Structure 17

The VHDL Simulation Library Directory Structure on the UNIX Platform 17

Examples Directory 18

Library Directory 18

The VHDL Simulation Library Directory Structure on the PC Platform 20

Examples Directory 20

Library Directory 21

VHDL Simulation Libraries 22

VHDL Functional Simulation Library 22

VHDL Timing Simulation Library 23

VHDL Module Simulation Library 23

VHDL Functional Simulation Overview 24

Functional Simulation Steps 25

Functional Simulation Process Flow 26

VHDL Timing Simulation Overview 27

VHDL Timing Simulation Steps 27

Chapter 2 VHDL Simulation with Cadence Leapfrog 29

Cadence Leapfrog Simulation Library Environment 30

Prerequisites 30

Environment Setup 30

Files for Schematic Capture 30

Files for Schematic to VHDL Conversion 31

Files for Simulations and Library Compilation 32

Library Compilation 33

VHDL Functional Library Compilation 33

VHDL VITAL Timing Library Compilation 33

VHDL Module Simulation Library Compilation 34

VHDL Functional Simulation with Cadence LeapFrog 35

Functional Simulation Steps 35

Command-Line Quick Reference List 36

Schematic to VHDL Design Conversion Command 36

Design Compilation Command 36

Functional Simulation Command 36

VHDL Timing Simulation with Cadence LeapFrog 37

Timing Simulation Steps 37

Command-Line Quick Reference List 38

VHDL Netlist Generation Command 38

Design Elaboration Command 38

Device-Specific Notes for Timing Simulation 40

GXRESET 40

XTEST_OE 40

Chapter 3 VHDL Simulation with Mentor Graphics QuickVHDL 41

Mentor Graphics QuickVHDL Simulation Library Environment 42

Prerequisites 42

Environment Setup 42

Files for Schematic Capture 42

Files for Schematic to VHDL Conversion 42

Files for Simulation and Library Compilation 43

Library Compilation 44

VHDL Functional Library Compilation 44

VHDL VITAL Timing Library Compilation 44

VHDL Module Simulation Library Compilation 45

VHDL Functional Simulation with Mentor Graphics QuickVHDL 46

Functional Simulation Steps 46

Command-Line Quick Reference List 47

Schematic to VHDL Design Conversion Command 47

Work Library Creation Command 47

Design Compilation Command 47

Functional Simulation Command 47

VHDL Timing Simulation with Mentor Graphics QuickVHDL 48

Timing Simulation Steps 48

Command-Line Quick Reference List 49

Design Compilation Command 49

Timing Simulation Command 49

Device-Specific Notes for Timing Simulation 51

GXRESET 51

XTEST_OE 51

Chapter 4 VHDL Simulation with Synopsys VSS 52

Synopsys VSS Simulation Library Environment 53

Prerequisites 53

Environment Setup 53

Files for Simulation and Library Compilation 53

Library Compilation 54

VHDL Functional Library Compilation 54

VHDL VITAL Timing Library Compilation 55

VHDL Module Simulation Library Compilation 56

VHDL Functional Simulation with Synopsys VSS 57

Functional Simulation Steps 57

VHDL Timing Simulation with Synopsys VSS 58

Timing Simulation Steps 58

Command-Line Quick Reference List 59

Design Compilation Command 59

Timing Simulation Command 59

Device-Specific Notes for Timing Simulation 61

GXRESET 61

XTEST_OE 61

Chapter 5 VHDL Simulation with Viewlogic Vantage 62

Viewlogic Vantage Simulation Library Environment 63

Prerequisites 63

Environment Setup 63

Library Compilation 65

VHDL Functional Library Compilation 65

VHDL Functional Simulation with Viewlogic Vantage 66

Functional Simulation Steps 66

Command-Line Quick Reference List 67

Schematic to VHDL Design Conversion Command 67

Work Library Creation Command 67

Design Compilation Command 67

Functional Simulation Command 67

VHDL Timing Simulation with Viewlogic Vantage 68

Timing Simulation Steps 68

Command-Line Quick Reference List 69

Work Library Creation Command 69

Design Compilation Command 69

Functional Simulation Command 69

Device-Specific Notes for Timing Simulation 70

Chapter 6 VHDL Simulation with Model Technology V-System/VHDL 71

Model Technology V-System Simulation Library Compilation 72

VHDL Functional Library Compilation Steps: 72

VHDL Timing Library Compilation Steps 72

VHDL Module Simulation Library Compilation Steps 73

VHDL Functional Simulation Using Model Technology 74

Functional Simulation Steps 75

VHDL Timing Simulation using Model Technology V-System 76

Timing Simulation Steps 77

Command-Line Quick Reference List 79

Timing Simulation Command 79

Device-Specific Notes for Timing Simulation 79

GXRESET 79

XTEST_OE 79

Chapter 7 VHDL Simulation with Viewlogic Speedwave 80

Viewlogic Speedwave Simulation Library Environment 81

Prerequisites 81

Library Compilation 82

VHDL Functional Library Compilation Steps 82

VHDL Timing Library Compilation Steps 82

VHDL Module Simulation Library Compilation Steps 83

VHDL Functional Simulation Using Viewlogic Speedwave 84

Functional Simulation Steps 84

VHDL Timing Simulation using Viewlogic Speedwave 85

Timing Simulation Steps 85

Device-Specific Notes for Timing Simulation 87

GXRESET 87

XTEST_OE 87

Part II: Verilog Simulation 88

Chapter 8 Introduction to Verilog Simulation 89

Verilog Directory Structure 90

Examples Directory 90

Library Directory 90

Verilog Simulation Libraries 91

Verilog Functional Simulation Library 91

Verilog Timing Simulation Library 91

Verilog Module Simulation Library 91

Verilog Functional Simulation Overview 92

Verilog Timing Simulation Overview 93

Chapter 9 Verilog Simulation with Cadence Verilog-XL 94

Verilog Functional Simulation with Cadence Verilog-XL 95

Functional Simulation Steps 95

Test Fixture File 95

Verilog Netlist Creation 95

Command-Line Quick Reference List 95

Functional Simulation Command 95

Verilog Timing Simulation with Cadence Verilog-XL 96

Timing Simulation Steps 96

Command Line Quick-Reference List 97

Create Simulation Input Files Command 97

Timing Simulation Command 97

System Task 98

Device-Specific Notes for Timing Simulation 99

GXRESET 99

XTEST_OE 99

Chapter 10 Verilog Simulation with Frontline PureSpeed 100

Verilog Functional Simulation with Frontline PureSpeed 101

Functional Simulation Steps 101

Test Fixture File 101

Verilog Timing Simulation with Frontline PureSpeed 102

Timing Simulation Steps 102

Test Fixture File 102

Back-Annotation 103

SDF File 103

Header Entries 103

Cell Entries 103

System Task 104

Device-Specific Notes for Timing Simulation 105

GXRESET 105

XTEST_OE 105

Appendix A Bus/Vector Reconstruction 106

Bus/Vector Reconstruction Design Flow 107

EDIF Constructs Interpretation 108

EDIF Rename Syntax 108

EDIF Array Syntax 108

EDIF Member Syntax 109

User-Controlled Options for EDIF Array Interpretation 110

Specifying Index Ordering 110

Specifying Least Significant Bit (LSB) 112

Array Definition File Syntax 114

Examples 116

The LSC HDL Simulation Library Package from Lattice™ Semiconductor Corporation(LSC, Lattice) contains VHDL and Verilog-compatible libraries for functional andtiming simulation It also includes the Module Simulation library to support the 6000family of devices

This manual describes how to use the VHDL and Verilog Simulation Libraries fromLattice to perform functional and timing simulation using one of the following

simulators: Cadence LeapFrog™, Mentor QuickVHDL®, Viewlogic Vantage®,

Synopsys® VSS™, Cadence Verilog XL, Frontline PureSpeed™, or any

OVI-compliant Verilog™ simulator Simulation can be performed on schematic designsthat have been created in Cadence Concept™, Mentor’s Design Architect®, andViewlogic’s Viewdraw® environment and then converted to VHDL or Verilog

Simulation can also be performed on VHDL or Verilog designs created using LatticeSemiconductor macros

The VHDL libraries are designed for use with:

■ Cadence Leapfrog VHDL simulator

■ Mentor QuickVHDL simulator

■ Viewlogic Vantage VHDL simulator

■ Synopsys VSS (VHDL System Simulator)

■ Model Technology V-System/VHDL simulator

■ Any IEEE 1076-87 compliant VHDL simulator

The Verilog libraries are designed for use with:

■ Cadence Verilog-XL

■ Frontline PureSpeed

■ Any OVI-compliant simulator

This manual is intended for use by engineers who are knowledgeable in VHDL andVerilog system design and architecture It also assumes that you are familiar with theispEXPERT™ software and a VHDL or Verilog simulator For additional information

on VHDL and Verilog, refer to the appropriate reference material listed under

“Related Documentation.”

What Is In This Manual

What Is In This Manual

This user manual contains information on the following topics for each supportedsimulator:

■ Environment Setup

■ Prerequisite Files

■ Required Files and Libraries

■ Compiling the Lattice VHDL and Simulation Libraries

■ Design Flows for Functional and Timing Simulation

Where to Look for Information

Part I, VHDL Simulation

Chapter 1, Introduction to VHDL Simulation – Describes the VHDL functional and

timing simulation flow It also identifies the directory structure of the files in the VHDLSimulation Libraries

Chapter 2, VHDL Simulation with Cadence Leapfrog – Provides information on the

environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Cadence Leapfrog simulator

Chapter 3, VHDL Simulation with Mentor Graphics QuickVHDL – Provides

information on the environment setup, prerequisite files, and compiling the simulationlibraries

Chapter 4, VHDL Simulation with Synopsys VSS – Provides information on the

environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Synopsys VSS simulator

Chapter 5, VHDL Simulation with Viewlogic Vantage – Provides information on the

environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Viewlogic Vantage simulator

Chapter 6, VHDL Simulation with Model Technology V-Tech – Provides

information on the environment setup, prerequisite files, compiling the simulationlibraries, and simulation steps for the Model Technology V-Tech simulator

Chapter 7, VHDL Simulation with Viewlogic Speedwave – Provides information on

the environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Viewlogic Speedwave simulator

Where to Look for Information

Part II, Verilog Simulation

Chapter 8, Introduction to Verilog Simulation – Describes the Verilog functional

and timing simulation flow It also identifies the directory structure of the files in theVerilog Simulation Libraries

Chapter 9, Verilog Simulation with Cadence Verilog-XL – Provides information on

the environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Cadence Verilog-XL simulator

Chapter 10, Verilog Simulation with Frontline PureSpeed – Provides information

on the environment setup, prerequisite files, compiling the simulation libraries, andsimulation steps for the Frontline PureSpeed simulator

Appendix A, Bus/Vector Reconstruction – Describes reconstructing buses and

vectors for Verilog and VHDL outputs using an array definition file

Documentation Conventions

Documentation Conventions

The software manuals use the following conventions

Italics Italicized text represents variable input For example:

design.1This means you must replacedesign with the file name you haveused for all the files relevant to your design

Valuable information may be italicized for emphasis

Book titles also appear in italics

The beginning of a procedure appears in italics For example:

To open a design:

Bold Valuable information may be boldfaced for emphasis Commands

are shown in boldface Buttons on dialog box are also boldfaced

| | Vertical bars indicate options that are mutually exclusive; you can

select only one For example:

REGTYPE GLB|IOC

“Quotes” Titles of chapters or sections in chapters in this manual are shown

in quotation marks and bold, blue, underscored type to indicatejumps to the specified chapter, section, or page For example:

SeeChapter 1, “Introduction to VHDL Simulation.”

✍NOTE Indicates a special note

▲CAUTION Indicates a situation that could cause loss of data or other

problems.

❖TIP Indicates a special hint that makes using the software easier.

⇒ Indicates a menu option leading to a submenu option For

example:

■ ispEXPERT Compiler User Manual

■ ispEXPERT Compiler and Cadence Design Manual

■ ispEXPERT Compiler and Mentor Graphics Design Manual

■ ispEXPERT Compiler and Synopsys Design Manual

■ ispEXPERT Compiler and Viewlogic Design Manual

■ Macro Library Reference Manual

■ 5K/8K Macro Library Supplement

Cadence

■ HDL Desktop Reference Manual

■ LeapFrog VHDL User Guide

■ LeapFrog VHDL Simulator Reference Manual

■ VHDLLink User Guide

Mentor

■ QuickSim II User’s and Reference Manual

■ QuickVHDL User’s and Reference Manual

■ VHDLwrite User’s and Reference Manual

Viewlogic

■ Viewsim/VHDL User Guide

Synopsys

■ VHDL System Simulator Tutorial

■ VHDL System Simulator Command Reference Manual

■ VHDL System Simulator User’s Manual

■ Library Compiler Reference Manual

IEEE

■ IEEE Standard VHDL Language Reference Manual 1076-87, 1076-93

Related Documentation

OVI

■ Standard Delay Format Specification (Version 2.1)

■ Verilog HDL Reference (version 1.0)

Model Technology Inc.

■ V-System/VHDL Windows User’s Manual

Frontline PureSpeed

■ PureSpeed User’s Manual

Part I: VHDL Simulation

Chapter 1 Introduction to VHDL Simulation

The VHDL Simulation library from Lattice Semiconductor Corporation (LSC) containsVHDL libraries for functional and timing simulation The VHDL libraries are designedfor use with:

■ Cadence Leapfrog VHDL simulator *

■ Mentor Graphics QuickVHDL simulator *

■ Viewlogic Vantage VHDL simulator

■ Synopsys VSS (VHDL System Simulator) *

■ Model Technology V-System/VHDL simulator *

■ Viewlogic Speedwave simulator*

* These simulators also support the module devices (6000 family) from LatticeSemiconductor Corporation Refer to theISP Encyclopedia for details on the moduledevices

The functional simulation library conforms to IEEE 1076-87 standards The VITALtiming library conforms to VITAL 3.0 standards

This chapter describes the VHDL Simulation library directory structure It alsoprovides an overview of functional and timing simulation

VHDL Directory Structure

VHDL Directory Structure

The VHDL Simulation library contains source files and examples for functional andtiming (with or without VITAL acceleration) simulation It also provides other vendor-dependent option files required to compile and use the libraries

The VHDL Simulation Library Directory Structure on the UNIX Platform

The simulators supported on the UNIX platform are: Cadence Leapfrog, MentorQuickVHDL, Viewlogic Vantage VHDL, and Synopsys VSS (VHDL SystemSimulator) Figure 1-1 shows the directory structure for the UNIX platform

Figure 1-1 VHDL Simulation Library Directory Structure on UNIX Platforms

lsc_mod

VHDL Directory Structure

Examples Directory

The examples directory contains examples for each design environment:

■ leapfrog – contains files for Cadence Leapfrog

■ qvhdl – contains files for Mentor QuickVHDL

■ vantage – contains files for Viewlogic Vantage

■ vss – contains files for Synopsys VSS

Each of the vendor subdirectories contains the following examples:

■ jkff – a JK flip-flop

■ traffic – a traffic light controller

■ multfifo – a module (FIFO-multiplier)

A step-by-step description is given for both functional and timing simulation usingeither the “jkff” schematic design example or the “multfifo” example in Verilog orVHDL design format

Library Directory

The library directory contains five subdirectories Many of the files are libraries thatneed to be compiled into directories prior to running simulation Please refer to theappropriate simulator chapter for instructions on compiling the libraries for the

simulator you are using

■ src – contains the following:

• Functional simulation library source file,func_src.vhd

• Timing simulation library source file,vital30.vhd

• Module simulation library source file,lscmod.vhd, for the 6000 family ofdevices

■ leapfrog – contains the following:

• func_lib – functional simulation library lat_vhd needs to be compiled into this

VHDL Directory Structure

■ qvhdl – contains the following:

• func_lib – functional simulation library lat_vhd needs to be compiled into this

• options – options files required for functional and timing simulation.

■ vss – contains the following:

• func_lib – functional simulation library lat_vhd needs to be compiled into this

• options – options files required for functional and timing simulation.

■ vantage – contains the following:

• func_lib – functional simulation library lat_vhd needs to be compiled into this

directory

• options – options files required for functional and timing simulation.

VHDL Directory Structure

The VHDL Simulation Library Directory Structure on the PC Platform

The VHDL Simulation package contains source files and examples for functional andtiming (with or without VITAL acceleration) simulation It also provides other vendor-dependent option files required to compile and use the libraries

The simulators supported on the PC platform are Model Technology V-System/VHDLsimulator and Viewlogic Speedwave Figure 1-2 shows the directory structure for the

PC platform

Figure 1-2 VHDL Simulation Library Directory Structure on PC Platforms

Examples Directory

The examples directory contains examples for each design environment:

■ modtech – contains files for Model Technology V-System

■ speedwav – contains files for Viewlogic SpeedWave

Each of the vendor subdirectories contains the following examples:

■ jkff – a JK flip-flop

■ traffic – a traffic light controller

■ multfifo – a module (FIFO-multiplier)

A step-by-step description is given for both functional and timing simulation usingeither the “jkff” schematic design example or the “multfifo” example in Verilog orVHDL design format

<ispcomp_vhdl>

examples library

modtech

src speedwav

VHDL Directory Structure

Library Directory

The library directory contains five subdirectories Many of the files are libraries thatneed to be compiled into directories prior to running simulation Please refer to theappropriate simulator chapter for instructions on compiling the libraries for the

simulator you are using

■ src – contains the following:

• Functional simulation library source file,func_src.vhd

• Timing simulation library source file,vital30.vhd

• Module simulation library source file,lscmod.vhd, for the ispLSI 6000 family

of devices

VHDL Simulation Libraries

VHDL Simulation Libraries

The VHDL simulation libraries are:

■ VHDL functional simulation library to support all devices It consists of all the

primitives and macros for HDL design entry and pre-route functional simulation.The source file isfunc_src.vhd.

■ VHDL timing simulation library to support all devices It consists of all the timing

primitives for post-compilation timing simulation The source file isvital30.vhd

for VITAL 3.0 compatibility

■ VHDL module simulation library to support the 6000 family of devices It

consists of the macros for both functional and timing simulation The source file is

lscmod.vhd

Before a library can be used for simulation, certain environment variables need to beset up for each of the design environments Once the variables are set, the librariescan be compiled using the appropriate source file located in the

<ispcomp_path>/vhdl/library/src directory Changes in the standard IEEE VHDLpackages also require recompilation of the VHDL simulation libraries

A detailed explanation on setting up the environment and the steps for compiling ineach environment is described in each simulator-specific chapter

VHDL Functional Simulation Library

The VHDL functional simulation library must be compiled using thefunc_src.vhd

file in the <ispcomp_path>/vhdl/library/src directory

The VHDL functional simulation library contains behavioral and structuraldescriptions of LSC primitives and macros The library allows you to perform apre-route, unit-delay, functional simulation on VHDL designs In the LSC design flow,functional simulation is performed after your schematic or VHDL design is completeand before it is compiled with the ispEXPERT Compiler software

Although there are several ways to create the structural VHDL description, thismanual illustrates the method of converting a schematic design that uses LSCmacros into structural VHDL in the supported environments Additionally, the LSCVHDL libraries can be used with VHDL design files that make use of LSC macros

VHDL Simulation Libraries

VHDL Timing Simulation Library

The VHDL timing simulation library must be compiled using thevital30.vhd file inthe <ispcomp_path>/vhdl/library/src directory

Timing simulation can be performed on VHDL designs using VITAL (VHDL InitiativeTowards ASIC Libraries) and non-VITAL VHDL While non-VITAL timing simulation issupported on all environments, VITAL timing simulation is supported on all VITAL-compliant VHDL simulators

In the LSC design flow, timing simulation is performed after the design has beencompiled by the ispEXPERT Compiler software

VHDL Module Simulation Library

The VHDL module simulation library must be compiled using thelscmod.vhdfile inthe <ispcomp_path>/vhdl/library/src directory

The VHDL module simulation library is required for both functional and timing

simulation of designs that use the 6000 family devices The library allows you toperform a pre-route, functional simulation on a module VHDL design It also supportspost-route, timing simulation on the design after it is compiled with the ispEXPERTCompiler

In order to use an ispLSI 6000 family device, one or two of the VHDL module macroconfigurations should be included in your design The 25 macro configurations haveprogrammable features to be customized to your design For details, refer to theappropriateispEXPERT Compiler and “Third Party” Design Manual

In most cases, this library should not be used by itself When running functionalsimulation, both the VHDL module simulation library and the VHDL functional

simulation library should be used When running timing simulation, the VHDL modulesimulation library and the VHDL timing simulation library should be used

VHDL Functional Simulation Overview

VHDL Functional Simulation Overview

Although there are several ways to create a design in VHDL, this manual uses twoapproaches:

■ creating a design in Schematic Capture using the Lattice Schematic Library andconverting it into a VHDL structural netlist

<ispcomp_path>/vhdl/library/<vendor>/options directory The result of the conversion

is thedesign.vhd file Besides converting a schematic, you can create a VHDLdesign file using LSC macros for Synopsys VSS, Cadence Leapfrog, and ModelTechnology V-System

Create your test bench/vectors for functional simulation You can choose any method

to create a functional simulation test bench and observe your simulation outputs

Compile yourdesign.vhd file using the VHDL functional simulation library and thetest bench with your VHDL compiler Once your design is compiled, perform thefunctional simulation using the VHDL functional simulation library

For designs using ispLSI 6000 family devices, the Lattice VHDL module simulationlibrary should also be used in design compilation and functional simulation

VHDL Functional Simulation Overview

Functional Simulation Steps

The basic steps for functional simulation for a schematic design are:

1 Ensure that your environment is set up correctly Refer to the chapter for yoursimulator for information on environment setup

2 Create a design in schematic capture using the LSC schematic library If a design

is created in VHDL entry, skip steps 3 and 4

3 Generate a symbol of your top-level schematic

4 Convert your schematic design into a VHDL design file

5 Create a work library for your VHDL design

6 Compile your design

7 Create a test bench and test vectors for your design

8 Compile your simulation test bench/vectors

9 Perform functional simulation

The basic steps for functional simulation for a structural/behavioral design are:

1 Ensure that your environment is set up correctly Refer to the chapter for yoursimulator for information on environment setup

2 Create a structural/behavioral VHDL design

3 Create a work library for your VHDL design

4 Compile your design

5 Create a test bench and test vectors for your design

6 Compile your simulation test bench/vectors

7 Perform functional simulation

The basic flow for functional simulation is shown in Figure 1-3

VHDL Functional Simulation Overview

Functional Simulation Process Flow

Figure 1-3 VHDL Functional Simulation Process Flow

Test Bench

based Design

Schematic-Option

Files

VHDL Simulator

LSC Schematic

Library

VHDL Compiler VHDL files Schematic to VHDL

vendor supplied

Module Simulation Library

Functional LIbrary Simulation VHDL

VHDL

VHDL Structural/

Behavioral Design

LSC Macros

VHDL Timing Simulation Overview

VHDL Timing Simulation Overview

Timing simulation is performed on a design after the design has been verified for itsfunctionality and fit into the target device by the ispEXPERT Compiler The input tothe compiler can be any of the formats it accepts (EDIF, LAF, or PLA) By choosingthe output format as “VHDL,” the compiler compiles a given design and produces thefollowing files:

back-annotation

timing behavior of the fitted design You do not need any libraries to perform timingsimulation using one of these two files

for timing simulation

During the compilation process, option files are required to ensure that VHDL designsuse the LSC VHDL libraries These option files are available in the

<ispcomp_path>/vhdl/library/<vendor>/options directory

Once the VHDL design is obtained, it can be compiled and simulated by the variousVHDL simulators Create your test bench/vectors for timing simulation You canchoose any method to create a functional simulation test bench and observe yoursimulation outputs

VHDL Timing Simulation Steps

The basic steps for timing simulation are summarized below The basic flow for timingsimulation is shown in Figure 1-4

1 Create a schematic (if required)

2 Convert the design into one of the formats that the ispEXPERT Compiler accepts

3 Compile the design using the ispEXPERT Compiler to generate a post-routeVHDL netlist

4 Compile the VHDL netlist file with your vendor-specific VHDL compiler

5 Create and compile a suitable test bench for your design

6 Perform timing simulation

VHDL Timing Simulation Overview

VHDL Timing Simulation Process Flow

Figure 1-4 VHDL Timing Simulation Process Flow

✍ NOTE Whenever a reference is made to using thedpm command, you

can use the ispEXPERT Compiler Design Manager Click EDIF reader settings from the Create New Project dialog box to enter the Vendor-specific EDIF file Click Interfaces on the Compiler

Settings dialog box to specify VHDL as the netlist to be

generated Select Tools⇒Compile to compile the design and

generate the netlists Refer to theispEXPERT Compiler User

Compilation

Simulation

Bench design.vhn

VHDL

Module Simulation Library

VHDL

Test VHDL

VHDL VITAL Timing Simulation Library

Chapter 2 VHDL Simulation with Cadence

Cadence Leapfrog Simulation Library Environment

Cadence Leapfrog Simulation Library Environment

To use the VHDL Simulation Libraries with your design environment you need to besure certain files are available This section describes the files needed by theCadence Leapfrog VHDL simulator

Prerequisites

Before installing and compiling the VHDL Simulation Library, the following softwarepackages must already be installed:

■ Cadence Concept software

■ Cadence Leapfrog VHDL Simulator

■ Cadence Interface Kit from Lattice Semiconductor

Environment Setup

Specific files are required to perform the schematic capture, convert the schematic toVHDL, and perform the simulations These files must be created and saved or copiedinto your design directory For reference, copies of the files are located in the

/<ispcomp_path>/vhdl/library/leapfrog/options directory

Files for Schematic Capture

Refer to theispEXPERT Compiler and Cadence Design Manual for details on

schematic capture The following file modifications, shown highlighted, are required

for schematic capture:

a master_library “master.local”;

library “lsc”;

b Add the VHDL module simulation library to theglobal.cmd file if an ispLSI

6000 family device is used:

b Add the VHDL module simulation library to themaster.localfile if an ispLSI

6000 family device is used

‘lsc_mod’

‘/<ispcomp_path>/cadence/concept/lsc_mod/lsc_mod.lib’;

Cadence Leapfrog Simulation Library Environment

Files for Schematic to VHDL Conversion

In addition toglobal.cmd andmaster.local, the following file modifications,

shown highlighted, are required for conversion from a Concept schematic to a

structural VHDL file:

vhdllink command to convert a Cadence Concept schematic to a structural VHDL

file The following is an example of avhdllink.cmd file:

structural VHDL file Copy this file from the <ispcomp_path>/vhdl/library

/leapfrog/options directory to your design directory

Cadence Leapfrog Simulation Library Environment

Files for Simulations and Library Compilation

The following files are required to perform the functional and timing simulations aswell as library compilation:

Create thecds.lib file using any text editor Place this file in your design

directory for functional and timing simulations Add the library name and path asshown below Change the path names shown initalics to your actual directorypaths An example of acds.lib file is:

DEFINE LAT_VHD <ispcomp_path>/vhdl/library/leapfrog

Create thehdl.var file using any text editor Place the following line in this file:

DEFINE WORK <work_library_name>

VHDL Functional Library Compilation

The source file for the functional library for Leapfrog is <ispcomp_path>/vhdl/library/src/func_src.vhd

1 Enter the following at the prompt:

cd <ispcomp_path>/vhdl/library/leapfrog/func_lib

2 Create a directory called “lat_vhd” to compile the functional library

mkdir lat_vhd

3 Include the lat_vhd directory in thecds.lib file as follows:

DEFINE LAT_VHD <ispcomp_path>/vhdl/library/leapfrog /func_lib/lat_vhd

4 Include the lat_vhd directory in thehdl.var file as follows:

DEFINE WORK lat_vhd

5 Compile the library from the HDL desktop using the following command:

cv -m -w LAT_VHD -f <ispcomp_path>/vhdl/library/src/func_src.vhd

Once the library has been successfully compiled, it is ready for use in simulation

VHDL VITAL Timing Library Compilation

The source file for the VHDL VITAL timing library for Leapfrog is

3 Include the lat_vitl directory in thecds.lib file as follows:

DEFINE LAT_VITL <ispcomp_path>/vhdl/library/leapfrog /func_lib/lat_vitl

4 Include the lat_vitl directory in thehdl.var file as follows:

DEFINE WORK lat_vitl

5 Compile the library from the HDL desktop using the following command:

cv -m -w LAT_VITL -f <ispcomp_path>/vhdl/library/src/vital30.vhd

Once the library has been successfully compiled, it is ready for use in simulation

Library Compilation

VHDL Module Simulation Library Compilation

The source file for the VHDL module simulation library for Leapfrog is

3 Include the lsc_mod directory in thecds.lib file as follows:

DEFINE LSC_MOD <ispcomp_path>/vhdl/library/leapfrog /func_lib/lsc_mod

4 Include the lsc_mod directory in thehdl.var file as follows:

DEFINE WORK lsc_mod

5 Compile the library from the HDL desktop using the following command:

cv -m -w LSC_MOD -f <ispcomp_path>/vhdl/library/src/lscmod.vhd

Once the library has been successfully compiled, it is ready for use in simulation

VHDL Functional Simulation with Cadence LeapFrog

VHDL Functional Simulation with Cadence LeapFrog

The steps for performing functional simulation using the VHDL simulation library andVHDL module simulation library are described in this section Examples to use withthese steps can be found in <ispcomp_path>/vhdl/examples/leapfrog

Functional Simulation Steps

1 Ensure that your environment is set up correctly; refer to“Environment Setup”

on page 30

2 Create the schematic in the Cadence Concept environment

3 Create a body/symbol for the top-level schematic using “genview” in the CadenceConcept environment, giving it the same name as the schematic Save the

schematic

4 Convert the schematic to a structural VHDL design file by performing these steps:

a Ensure that thevhdllink.cmd file is present in the current directory andcontains the necessary options; refer to“Environment Setup” on page 30

b Enter the following from the command line:

Replace <design> with the name of your design

d Add the VHDL module simulation library in your VHDL design file if the designuses an ispLSI 6000 family device:

library lsc_mod;

use lsc_mod.mod_pkg.all;

e Delete any other “library” or “use” statements in your structural VHDL file

5 Create a work library to compile the VHDL file

a Enter the following command from the UNIX prompt:

mkdir <work_library_name>

b Include the work library in thecds.lib file as follows:

DEFINE <work_library_name> <path>

c Include the following line in thehdl.var file:

DEFINE WORK <work_library_name>

6 Compile the VHDL file by entering the following command:

cv -m -w work -f design.vhd

VHDL Functional Simulation with Cadence LeapFrog

7 Elaborate the design by entering the following command:

ev -m work.<entity>:<architecture>

8 Simulate the design by entering the following command:

sv work.<entity>:<architecture>

Command-Line Quick Reference List

Schematic to VHDL Design Conversion Command

vhdllink <design>

■ vhdllink – This command, followed by the design name, is used to convert aschematic into a structural VHDL design

Design Compilation Command

cv -m -w <work_library_name> -f design.vhd

■ cv – This command is used to compile the structural VHDL file

• -m – This option is used if you wish informative messages to be displayedduring compilation

• -w – This option specifies the work library used for compilation

compilation

ev -m work.<entity>:<architecture>

■ ev – This command is used to elaborate the compiled design

• -m– This option is used if you wish informative messages to be displayedduring compilation

bench architecture

Functional Simulation Command

sv work.<entity>:<architecture>

■ sv – This command invokes the LeapFrog simulator

✍ NOTE The commands for steps 6, 7, and 8 can be entered either from

the system prompt or the HDL desktop prompt

VHDL Timing Simulation with Cadence LeapFrog

VHDL Timing Simulation with Cadence LeapFrog

The steps for performing timing simulation using the VHDL simulation library andVHDL module simulation library are described in this section Examples to use withthese steps can be found in <ispcomp_path>/vhdl/examples/leapfrog

Timing Simulation Steps

Although there are several ways to generate the design file for input to theispEXPERT Compiler, in the following steps the design format is EDIF The schematiccreated for functional simulation in Concept can be converted to EDIF Refer to theispEXPERT Compiler and Cadence Design Manual

1 Use the following command to generate a structural VHDL netlist file for timingsimulation:

dpm -if edif -i design.edif -of vhdl

This command generates structural VHDL netlist files nameddesign.vho and

which can be compiled using the Leapfrog VHDL compiler and an SDF

back-annotate the timing values during VITAL timing simulation

2 Create a work library to compile the VHDL netlist file

mkdir <work_library_name>

a Include the work library in thecds.libfile (refer to“Environment Setup” on page 30) as follows:

DEFINE <work_library_name> <path>

b Include the following line in thehdl.var file:

DEFINE WORK <work_library_name>

3 Compile the structural VHDL file using the following command:

cv -m -w work -f <design>

You can also compile any test bench files using this command

4 Elaborate the compiled design using the following command for VITAL designs:

ev -m -BSDF <sdf_file_name> -bscope <scope_level>

✍ NOTE The commands for steps 3, 4, and 5 can be entered either from

the system prompt or the HDL desktop prompt

VHDL Timing Simulation with Cadence LeapFrog

Command-Line Quick Reference List

VHDL Netlist Generation Command

From the UNIX prompt:

dpm -if edif -i <design.edif> -of vhdl

■ dpm – This command invokes the ispEXPERT Compiler

Compiler is EDIF

compiled Replacedesign with the name of your design

ispEXPERT Compiler

Design Elaboration Command

For VITAL VHDL timing simulation, use the following command:

■ ev – This command elaborates the design

• -m – This option is used if you wish informative messages to be displayedduring compilation

to be used for annotating timing values

specify inscope_level (the instantiation of the top-level design unit); refer tothe example on the next page

either MIN or MAX but not TYPICAL, since the typical value is zero

name

bench entity

your test bench architecture

VHDL Timing Simulation with Cadence LeapFrog

An example of how to use the design elaboration (ev) command is shown here.

Assume you have a design FOO The test bench entity is TBENCH and the

architecture A The test bench instantiates the component FOO with thescope_level

To back-annotate the delays into FOO from the SDF file, specify TOP as the

scope_level, TBENCH as the entity, and A as the architecture in the ev command.

The elaboration command would be:

ev -m -BSDF sdf_file_name -bscope TOP TBENCH:A

Refer to theLeapfrog VHDL Simulator Reference Manual for further help on

elaboration and simulation commands

VHDL Timing Simulation with Cadence LeapFrog

Device-Specific Notes for Timing Simulation

XTEST_OE

If you use an ispLSI 3000, ispLSI 6000, ispLSI 5000, or ispLSI 8000 device, set theXTEST_OE pin to high For the ispLSI 5000 device, if XTEST_AS_IO is set to on, thispin does not need to be set to high