Bài tập lập trình VLSI Lab programs

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EX.NO:1(a) Design and Simulation of Half Adder using VHDL

port (a,b:in bit;

sum,carry: out bit);

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1 Open new file in VHDL source editor

2 Type the VHDL coding for Half Adder in the new file

3 Save the file with the extension of vhd

4 Compile and Simulate the Program

5 Add the selected signal to the wave form window

6 Force the input signals values and verify the output signal values

RESULT:

Thus the Half adder is designed and verified using VHDL

EX.NO:1(b) Design and Simulation of Full Adder using VHDL

To construct a full adder circuit, we'll need three inputs and two

outputs Since we'll have both an input carry and an output carry, we'll designate them as CIN and COUT At the same time, we'll use S to

designate the final Sum output The resulting truth table is shown to the right

VHDL CODING:

library ieee;

use ieee.std_logic_1164.all;

entity fulladder is

port (x, y, Cin: in bit;

Cout,S :out bit);

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end fulladder;

architecture arch_fulladder of fulladder is

begin

S<= (x xor y) xor Cin;

Cout<= (x and y) or (y and Cin) or (Cin and x);

end arch_fulladder;

PROCEDURE

2 Type the VHDL coding for Full Adder in the new file

RESULT:

Thus the Full adder is designed and verified using VHDL

EX.NO:2(a) Design and Simulation of 4:2 Encoder using VHDL

The encoder is a combinational circuit that performs the reverse operation

of the decoder The encoder has a maximum of 2n inputs and n outputs An encoder performs the opposite function of a decoder An encoder takes a input on one of its 2n input lines and converts it to a coded output with n lines

VHDL CODING:

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library ieee;

entity encoder is

port (a,b,c,d:in bit;

y:out bit_vector(1 downto 0));

2 Type the VHDL coding for 4:2 Encoder in the new file

RESULT:

Thus the 4:2 Encoder is designed and verified using VHDL

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EX.NO:2(b) Design and Simulation of 2:4 Decoder using VHDL

n input lines requires 2n output lines to decode every possible combination

of bits BCD to decimal conversion, looked at in part3 of this lab, is accomplished using a decoder which has 4 input lines and 10 output lines (the 10 output lines correspond to the decimal numbers 0-9) This device is used to convert between binary numbers and decimal numbers

VHDL CODING:

library ieee;

entity decoder is

port (a,b:in bit;

y:out bit_vector(3 downto 0));

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elsif (a='1' and b='1' )then

2 Type the VHDL coding for 2:4 Decoders in the new file

RESULT:

Thus the 2:4 Decoder is designed and verified using VHDL

EX.NO:3(a) Design and Simulation of 8:1 Multiplexer using VHDL

or control signals and one output signal The input that gets selected to pass to the output is determined by the control signals

VHDL CODING:

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2 Type the VHDL coding for 8:1 Multiplexer in the new file

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Thus the 8:1 Multiplexer is designed and verified using VHDL

EX.NO:3(b) Design and Simulation of 1:8 Demultiplexer using VHDL

VHDL CODING:

library ieee;

use ieee.std_logic_unsigned.all;

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2 Type the VHDL coding for 1:8 Demultiplexers in the new file

RESULT:

Thus the 1:8 Demultiplixer is designed and verified using VHDL

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EX.NO:4 Design and Simulation of 4x4 Multiplier using VHDL

of the lengths of the serial input and parallel input to avoid overflow,

which means this multiplier takes more clocks to complete than the scaling accumulator version

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port(a,b:in std_logic_vector(3 downto 0);

p:out std_logic_vector(7 downto 0));

signal c :std_logic_vector(15 downto 0);

signal s:std_logic_vector(15 downto 0);

signal q :std_logic_vector(15 downto 0);

signal z : std_logic := '0';

begin

a0: a1 port map(a(0),b(0),p(0));

a2: a1 port map(a(1),b(0),c(1));

a3: a1 port map(a(2),b(0),c(2));

a4: a1 port map(a(3),b(0),c(3));

a5: a1 port map(a(0),b(1),c(4));

a6: a1 port map(a(1),b(1),c(5));

a7: a1 port map(a(2),b(1),c(6));

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a8: a1 port map(a(3),b(1),c(7));

a9: a1 port map(a(0),b(2),c(8));

a10: a1 port map(a(1),b(2),c(9));

a11: a1 port map(a(2),b(2),c(10));

a12: a1 port map(a(3),b(2),c(11));

a13: a1 port map(a(0),b(3),c(12));

a14: a1 port map(a(1),b(3),c(13));

a15: a1 port map(a(2),b(3),c(14));

a16: a1 port map(a(3),b(3),c(15));

f0:fa port map(c(1),c(4),z,p(1),q(0));

f1:fa port map(q(0),c(2),c(5),s(1),q(1));

f2:fa port map(q(1),c(3),c(6),s(2),q(2));

f3:fa port map(q(2),z,c(7),s(3),q(3));

f4:fa port map(s(1),z,c(8),p(2),q(4));

f5:fa port map(q(4),s(2),c(9),s(4),q(5));

f6:fa port map(q(5),s(3),c(10),s(5),q(6));

f7:fa port map(q(6),q(3),c(11),s(6),q(7));

f8:fa port map(s(4),z,c(12),p(3),q(8));

f9:fa port map(q(8),s(5),c(13),p(4),q(9));

f10:fa port map(q(9),s(6),c(14),p(5),q(10));

f11:fa port map(q(10),q(7),c(15),p(6),p(7));

end multiplier;

PROCEDURE

2 Type the VHDL coding for multiplier in the new file

RESULT:

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Thus the 4X4 Array Multiplier Half adder is designed and verified using VHDL.

EX.NO:5(a) Design and Simulation of JK Flip Flop using VHDL

The JK flip-flop behaves just like the RS flip-flop The Q and Q'

outputs will only change state on the falling edge of the CLK signal, and the J and K inputs will control the future output state pretty much as

before However, there are some important differences

If both the J and K inputs are held at logic 1 and the CLK signal continues

to change, the Q and Q' outputs will simply change state with each falling edge of the CLK signal (The master latch circuit will change state with

each rising edge of CLK.) We can use this characteristic to advantage in a

number of ways A flip-flop built specifically to operate this way is

typically designated as a T (for Toggle) flip-flop The lone T input is in fact

the CLK input for other types of flip-flops

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2 Type the VHDL coding for JK Flip Flop in the new file

RESULT:

Thus the JK flip-flop is designed and verified using VHDL

EX.NO:5(b) Design and Simulation of D Flip Flop using VHDL AIM:

To design and verify the D Flipflop using VHDL

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One essential point about the D flip-flop is that when the clock input falls

to logic 0 and the outputs can change state, the Q output always takes on the state of the D input at the moment of the clock edge This was not true

of the RS and JK flip-flops The RS master section would repeatedly

change states to match the input signals while the clock line is logic 1, and the Q output would reflect whichever input most recently received an

active signal The JK master section would receive and hold an input to tell

it to change state, and never change that state until the next cycle of the clock This behavior is not possible with a D flip-flop

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end arch_dff;

PROCEDURE

2 Type the VHDL coding for D Flip Flop in the new file

RESULT:

Thus the D flip-flop is designed and verified using VHDL

EX.NO:6(a) Design and Simulation of 4 bit UP Counter using VHDL

AIM:

To design and verify the Up counter using VHDL

Since the first (LSB) flip-flop needs to toggle at every clock pulse, its

J and K inputs are connected to Vcc or Vdd, where they will be "high" all the time The next flip-flop need only "recognize" that the first flip-flop's Q output is high to be made ready to toggle, so no AND gate is needed However, the remaining flip-flops should be made ready to toggle only when all lower-order output bits are "high," thus the need for AND gates

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entity counter is port(clk, rst : in std_logic;

Q : out std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);

2 Type the VHDL coding for Up Counter in the new file

RESULT:

Thus the 4 bit up counter is designed and verified using VHDL

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EX.NO:6(b) Design and Simulation of 4 bit DOWN Counter using VHDL

To make a synchronous "down" counter, we need to build the circuit

to recognize the appropriate bit patterns predicting each toggle state while counting down Not surprisingly, when we examine the four-bit binary count sequence, we see that all preceding bits are "low" prior to

a toggle (following the sequence from bottom to top

entity counter is port(clk, rst : in std_logic;

Q : out std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);

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end archi;

PROCEDURE

2 Type the VHDL coding for Down Counter in the new file

RESULT:

Thus the 4 bit down counter is designed and verified using VHDL

EX.NO:7(a) Design and Simulation of SISO Shift Register using VHDL

in a circuit board to improve the reliability of a digital logic circuit

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2 Type the VHDL coding for Serial In Serial Out shift Register in the new file

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5 Add the selected signal to the wave form window.

serial-It is different in that it makes all the internal stages available as outputs Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs QA to QD after the fourth clock pulse

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2 Type the VHDL coding for Serial In Parallel Out Shift Register in the new file

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4 Compile and Simulate the Program.

A frequency divider is an electronic circuit that takes an input signal with a

frequency, fin, and generates an output signal with a frequency:

where n is an integer Phase-locked loop frequency synthesizers make use

of frequency dividers to generate a frequency that is a multiple of a

reference frequency Frequency dividers can be implemented for both

analog and digital applications

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clkby2,clkby4,clkby8,clkby16:out std_logic);

end freqdiv;

architecture archi of freqdiv is

signal Q: std_logic_vector(3 downto 0);

2 Type the VHDL coding for Frequency Divider in the new file

RESULT:

Thus the Frequency Divider is designed and verified using VHDL

EX.NO:9 CMOS INVERTER

AIM:

To design and verify the CMOS inverter using SPICE

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TOOLS REQUIRED:

1 WinSpice3

2 Computer

PROCEDURE:

1 Open a notepad file

2 Write a program for CMOS inverter

3 Specify the input and output

4 Save the file with the extension of cir

5 Open the Winspice software

6 Click the file and open the Program file

7 Verify the input and output plots

Thus CMOS Inverter is designed and verified using SPICE

EX.NO:10(A) CMOS NAND GATE

AIM:

To design and verify the CMOS NAND gate using SPICE

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TOOLS REQUIRED:

1.WinSpice3

2.Computer

PROCEDURE:

2 Write a program for CMOS NAND gate

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EX.NO:10(B) CMOS NOR GATE

2 Write a program for CMOS NOR gate

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Thus CMOS NOR is designed and verified using SPICE

EX.NO:11 CMOS D LATCH

2 Write a program for CMOS D Latch

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Thus CMOS D LATCH is designed and verified using SPICE

EX.NO:12 FPGA Implementation of 4 Bit Adder

2 XILINX ISE 9.2i

3 Spartan IIIE FPGA Kit

THEORY:

It is possible to create a logical circuit using multiple full adders to add bit numbers Each full adder inputs a Cin, which is the Cout of the previous adder This kind of adder is a ripple carry adder, since each carry bit

N-"ripples" to the next full adder Note that the first (and only the first) full adder may be replaced by a half adder

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full

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