Điện tử số part 5

Bộ môn Điện tử số do Thầy Nam phó viện trưởng trường ĐHBKHN biên soạn đem lại cho các bạn 1 cách tiếp cận đơn giản dễ hiểu với môn này

• Combinatorial circuits: without status

• Sequential circuits: with status

• FSMD design: hardwired processors

 Language based HW design: VHDL

• Sequential construction statements

• Higher performance, less portability: e.g synthesis issues for Xilinx

• Sequential construction statements

• Higher performance, less portability: e.g synthesis issues for Xilinx

 VHDL = VHSIC Hardware Description Language

 VHSIC = Very High Speed Integrated Circuit

• What is VHDL?

 A programming language for describing the behavior

of digital systems

 Design entry language, used for

 Unambiguous specification at behavioral and RTL level

 Simulation (executable specification…)

 VHDL has a difficult syntax (Language sensitive editors with templates for all language

constructs)

 VHDL is very ‘wordy’: lots of code to type for just

a few simple things

 A list of instructions is less intuitive to understand than a block diagram for a human being

 VHDL is designed to make simulation efficient: contains aspects that have hardly anything to do with hardware behavior, but is useful to speed-up event driven simulation

 Easier to capture complex circuits: higher level

of abstraction with automated synthesis

down a specific type of adder: the synthesis tool will instantiate the best type of adder under timing, area

& power constraints

length, queue depth)

components

 Portable across many tools for simulation, synthesis, analysis, verification, … of different

 you can specify the same behavior (e.g MUX) in

an almost unlimited number of ways

 each leading to a completely different implementation (e.g Multiplexor or tri-state bus)

 which is synthesis tool dependent.

 You should do lots of experimentation with tool combinations to be able to predict how the hardware will look like that will be synthesised Is prediction necessary? You also do not predict the ASM generated by C; C is less efficient than ASM but faster to write Currently, it is hard to tolerate the inefficiency caused by the higher level

style-specification for hardware.

 Note: for DSP processors programmed in C, we do predict ASM and have to experiment with style- compiler combinations for efficiency reasons!!

 Only digital; special extension (not yet widely adopted) for analog: VHDL-AMS (acronym for VHDL Analog and Mixed Signal)

1076-1993 standard for digital design

function work correctly

used for high level executable specification in top-down design and manual synthesis into RTL

 Interconnected registers and combinatorial units

 Info on function (what) and architecture (how)

 Interconnected gates and flip-flops

 Info on function and architecture

 Info on technology dependent timing (gate delays)

 Layout

 Info on layout on silicon

 Continuous timing

level ASIC sign-off

better

 PLD languages like ABEL, PALASM, …

capturing also technology dependent features (e.g detailed timing)

integers, bit vectors, fixed point numbers

• Sequential construction statements

• Higher performance, less portability: e.g synthesis issues for Xilinx

Example 1 task description

• Design a circuit named ‘Test’ with 3 8-bit inputs (In1, In2, In3) and two boolean

outputs (Out1, Out2) The first output equals ‘1’ when the first and second input are equal; the second output equals ‘1’

when the first and third input are equal.

• Let’s first make a schematic design:

EQ

CompareA

B

EQ

AND

Entity and Architecture

• Declaration of the ‘Compare’ design entity:

Eight bit comparator

entity Compare isport( A,B: in bit_vector(0 to 7);

EQ: out bit);

end entity Compare;

architecture Behav1 of Compare isbegin

EQ <= ‘1’ when (A=B) else ‘0’;

end architecture Behav1;

‘Entity’ specifiesthe interface

to the circuit, theblack box of aschematicInput and outputsignals are called

‘ports’

‘Architecture’ describesthe behavior and structure

of the entity,the internals of the box

Notes:

- Multiple architectures per entity are possible: different ways

of implementing same behavior

- This architecture specifies behavior at RTL level and notthe actual structure of gates; synthesis tool will automaticallytranslate this RTL behavioral description into gate level

- Ports have an explicit direction and are (vectors of) bits

Component and Instantiation

• Specification of the next higher level in the circuit hierarchy: ‘Test’

Dual comparator Test component

entity Test isport( In1,In2,In3: in bit_vector(0 to 7);

Out1,Out2: out bit);

end entity Test;

architecture Struct1 of Test iscomponent Comparator is

port( X,Y: in bit_vector(0 to 7);

of the same component

‘Comparator’ with itssignal binding

Notes:

- The two ‘comparator’ components work concurrently!!!

Virtual device: allowsfor concurrentdevelopment of bothhierarchical levels,

by different persons

‘Comparator’ will bebound to ‘Compare’

later

return (A == B);

}

Interface to the function

Behavior of the function

Notes:

- Only one behavior per function possible

- Behavior is specified at rather high level and will beautomatically translated by the compiler into ASM instructions

- Function arguments do not have a direction and are of type int

Inputs and outputs arecalled ‘arguments’

int In1, In2, In3;

int Out1, Out2;

Out1 = Compare(In1, In2);

Out2 = Compare(In1, In3);

}

Two calls to the function

‘Compare’ with itsargument binding

Notes:

- The two ‘compare’ function calls are executed sequentially

- This main program is executed once and stops In VHDL, allcomponents describe relations that are valid continuously and

• How do you bind ‘Components’ to

end configuration Build1;

Note: ‘configuration’ corresponds in SW to ‘linking’

Both ‘use entity’s could

be combined in one:for All: Comparator

Signal_name: out Signal_type);

end entity Entity_name;

Signal_name: out Signal_type);

end component Component_name;

COMPONENT INSTANTIATION:

component instantiationInstance_name: component Component_name

port map (Signal_list);

or direct instantiationInstance_name: entity Entity_name(Architecture_name)

port map (Signal_list);

3-input AND gate

entity AND3 isport ( A,B,C: in bit;

Y: out bit);

end entity AND3;

architecture RTL of AND3 isbegin

Y <= ‘1’ when ((A=‘1’) and (B=‘1’) and (C=‘1’)) else ‘0’;

end architecture RTL;

3-input OR gate

entity OR3 isport ( A,B,C: in bit;

Y: out bit);

end entity OR3;

architecture RTL of OR3 isbegin

Y <= ‘0’ when ((A=‘0’) and (B=‘0’) and (C=‘0’)) else ‘1’;

end architecture RTL;

Y: out bit);

end entity INV;

architecture RTL of INV isbegin

Y <= ‘1’ when (A=‘0’) else ‘0’;

end architecture RTL;

S

entity MUX21 isport ( A,B,S: in bit;

Y: out bit);

end entity MUX21;

The black boxinterface

architecture Behav of MUX21 isbegin

Y <= A when (S=‘1’) else B;

end architecture Behav;

Behavioral description

Z: out bit);

end component AND2;

component OR2 isport ( X,Y: in bit;

Z: out bit);

end component OR2;

component INV isport ( X: in bit;

Z: out bit);

end component INV;

begin

Gate1: component INV port map (X=>S,Z=>U);

Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);

Gate3: component AND2 port map (X=>U,Y=>B,Z=>V);

Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);

end architecture Struct;

A First look at VHDL:

Example 3

• Build a 2-to-1 MUX using both a behav as

S

Structural description

ASB

Y

W

configuration Use3InputGates of MUX21 isfor Behav

end for;

for Struct

for Gate1:INV use entity INV(RTL)

port map (A=>X,Y=>Z);

end for;

for All:AND2 use entity AND3(RTL)

port map (A=>X,B=>Y,C=>’1’,Y=>Z);

end for;

for Gate4:OR2 use entity OR3(RTL)

port map (A=>X,B=>Y,C=>’0’,Y=>Z);

end for;

end for;

end configuration Use3InputGates;

EntitiesA

BC

Y

ComponentsX

Y

ZZ

 and check whether the outputs are correct

• A VHDL ‘test bench’ can be considered to

be the top level of a design

 It instantiates the Design Under Test (DUT)

In1<=‘0’;In2<=‘1’;Select<=‘0’; wait for 20 ns;

Select<=‘1’; wait for 20 ns;

In1<=‘1’;In2<=‘0’; wait for 20 ns;

end process Stimulus;

end architecture BehavTest;

• VHDL encourages this by the concept of

‘Packages’

• A ‘Package’ contains definitions of constant values, component declarations, user data types, and sub-programs of

VHDL code

• But first the concept ‘Library’: a library is

code resulting from analysis/compilation

is stored Default: WORK

end package Package_name;

How to use a package?

use Library_name.Package_name.all;

…U1: entity Package_name.Entity_name(Architecture_name);

• Sequential construction statements

• Higher performance, less portability: e.g synthesis issues for Xilinx

Signals and Data Types:

Predefined signal types

package Standard istype Bit is (‘0’,’1’);

type Boolean is (False, True);

type Character is ( ASCII set);

type Integer is range implementation_defined;

type Real is range implementation_defined;

type Bit_vector is ( array of bits);

type String is ( array of characters);

type Time is range implementation_defined;

end package Standard;

Bit, Boolean and Character are enumeration typesAll standard types are ‘unresolved’ (see later for the meaning

of this)

Signals and Data Types:

Predefined signal types

Examples of integer declarations:

type Year is range 0 to 99;

type Memory_address is range 65535 downto 0;

Examples of real declarations:

type Probability is range 0.0 to 1.0;

type Input_level is range -5.0 to 5.0;

A Bit_vector is a collection of bits; a value is specified betweendouble quotes:

constant State1: bit_vector(4 downto 0) := “00100”;

A String is a collection of characters; a value is specifiedbetween double quotes:

constant Error_message: string

:= “Unknown error: ask your poor sysop for help”;

Checked by simulator

MSB, bit 4 LSB

Time is a physical type:

type Time is range implementation_defined

Examples of use:

wait for 20 ns;

constant Sample_period: time := 2 ms;

constant Clock_period: time := 50 ns;

Signals and Data Types:

User defined physical types

The user may define his/her own physical types:

type Length is range 0 to 1E9

Imperial secondary units

Signals and Data Types:

User defined enumeration types

The user may define his/her own enumeration types:

type FSM_states is (reset, wait, input, calculate, output);

Not all synthesis tools support enumerated types

When they do support them, the default encoding is often

straightforward encoding using the minimum number of bits

Often, the default encoding may be over-written by somewherespecifying something like “encoding_style is gray_code” or byexplicitly specifying the encoding for each possible value:

constant reset: bit_vector := “10000”;

constant wait: bit_vector := “01000”;

constant input: bit_vector := “00100”;

constant calculate: bit_vector := “00010”;

constant output: bit_vector := “00001”;

The user may define arrays of types:

type 1D_array is array (1 to 10) of integer;

type 2D_array is array (5 downto 0, 1 to 10) of real;

Keep in mind that a vector of bits has NO numerical meaningand that hence arithmetic operations on vectors of bits make

no sense:

signal Bus,Address : bit_vector (0 to 3);

Bus <= Address + 1; This makes no sense!!!

Solution: via operator overloading (cf C++):

- two functions ‘+’ will exist, one working on integers andone working on vectors of bits

- the latter is defined in a vendor specific ‘vectorarithmetic package’ that should be use’d at the beginning

of your VHDL

• Therefore the IEEE defined in standard number 1164 9-valued logic signals and operations on them: use always those

instead of ‘bit’!!

• Exists in unresolved form (std_ulogic) and resolved form (std_logic) again: see

later for meaning

• Exists in single bit and array form:

‘U’, uninitialized e.g after power-up

‘X’, strongly driven unknown e.g after setup violation

‘0’, strongly driven logic zero

‘1’, strongly driven logic one

‘Z’, high impedance e.g not driven at all

‘W’, weakly driven unknown

‘L’, weakly driven logic zero

‘H’, weakly driven logic one

‘-’); don’t care

Is the following code valid?

signal Z,A,B: std_ulogic;

• For resolved data types (std_logic &

std_logic_vector), the resolver circuit is inferred by the synthesis tool

A

R

Resolvercircuitsignal Z,A,B: std_logic;

Z <= A;

Z <= B;

• Assignment is by position, not by index!!!

signal Down: std_logic_vector (3 downto 0);

signal Up: std_logic_vector (0 to 3);

Up <= Down;

Which of the two following interpretations is correct?

Up(0)Up(1)Up(2)Up(3)

Down(3)Down(2)Down(1)Down(0)

OR

Up(0)Up(1)Up(2)Up(3)

Down(0)Down(1)Down(2)Down(3)

downto ) is the same as in the declaration

signal Bus: std_logic_vector (7 downto 0);

Bus(5 downto 4) <= A(0 to 1);

Bus(5 downto 4) <= A(0 to 1);

Bus(4 downto 3) <= A(2 to 3);

Direction of Bus differs from declarationArray sizes do not match

OK! Bus(3) is driven by A(0)OK! Bus(5) is driven by A(0)

OK! Bus(4) is driven by A(1)and by A(2): resolved datatype… use with care!!

signal Byte_bus: std_logic_vector(7 downto 0);

signal Nibble_busA, Nibble_busB: std_logic_vector(3 downto 0);Byte_bus <= Nibble_busA & Nibble_busB;

Byte_bus(7)Byte_bus(6)Byte_bus(5)Byte_bus(4)Byte_bus(3)Byte_bus(2)Byte_bus(1)Byte_bus(0)

Nibble_busA(3)Nibble_busA(2)Nibble_busA(1)Nibble_busA(0)

Nibble_busB(3)Nibble_busB(2)Nibble_busB(1)Nibble_busB(0)

• Not supported by all synthesis tools!!

signal X,Y,Z,T: std_logic_vector(3 downto 0);

signal A,B,C: std_logic;

X <= (A,B,C,C); correspondence by position

Y <= (3 => A, 1 downto 0 => C, 2 => B);

Z <= (3 => A, 2 => B, others => C);

T <= (others => ‘0’); initialization irrespective of width of T

• Allows to parameterize behavior

• Enables re-use of entities in slightly changing environments

• Makes VHDL much more powerful than schematic entry

• Generic constants need to have a value at synthesis time!

entity General_mux isgeneric (width : integer);

port ( Input : in std_logic_vector (width - 1 downto 0);

Select : in integer range 0 to width - 1;

Output : out std_logic);

end entity General_mux;

generic (width : integer);

port ( Input : in std_logic_vector (width - 1 downto 0);

Select : in integer range 0 to width - 1;

Output : out std_logic);

end entity General_mux;

architecture Behav of General_mux isbegin

Output <= Input(Select);

end architecture Behav;

entity Testbench isend entity Testbench;

architecture Build1 of Testbench isconstant Input_size : integer := 8;

signal A : std_logic_vector (Input_size-1 downto 0);

signal S : integer range 0 to Input_size - 1;

signal B : std_logic;

begin

DUT: entity General_mux(Behav)

generic map (width => Input_size)

port map (Input => A, Select => S, Output => B);

end architecture Build1;

This is not valid VHDL:index is not known atdesign time! We willreplace this by valid

code later!

• Sequential construction statements

• Higher performance, less portability: e.g synthesis issues for Xilinx

 ‘not’ has highest precedence

 all others have equal precedence, lower than

‘not’

• Logical operators are predefined for following data types: bit, bit_vector, boolean, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector

• A logical operator may work on an array:

 arrays should have same size

 elements are matched by position