Điện tử số part 2

Bộ môn Điện tử số do Thầy Nam phó viện trưởng trường ĐHBKHN biên soạn đem lại cho các bạn 1 cách tiếp cận đơn giản dễ hiểu với môn này

Trang 1

• Sequential circuits: with status

• FSMD design: hardwired processors

• Language based HW design: VHDL

Trang 2

Design of Combinatorial Circuits

• Minimization of Boolean functions

• Technology mapping

• Correct timing behavior

• Basic RTL building blocks (Adder, ALU, MUX, …)

Trang 3

 Karnaugh map

 Minimization with the Karnaugh map

 Don’t care conditions

 Quine-McCluskey

Trang 4

 Karnaugh map

 Quine-McCluskey

Trang 5

NOR or NOT = 0.6 + fan-in * 0.4

(1.8+1) + (1.4+1) = 6.2

x y z

F=xy’z+xy’z’

Trang 6

The value of z hence does not matter

 Cost = Σ (fan-in)complete circuit = (1+2) = 3 i.o 10

 Delay

NOR or NOT = 0.6 + fan-in * 0.4

(1.4+1) = 3.4 i.o 6.2

x y z

F

Trang 7

We however see this easily only for z, since only for z the lines

Trang 8

x 0 1

y

x’y’z’ x’y’z xy’z’ xy’z

x 0 1

x’z (y does not matter)

x’y’z x’yz xy’z’ xyz’ xz’ (y does not matter) xy’z’ xy’z

xy’ (z does not matter)

Trang 10

Fill out from truth table

Trang 11

Minimize F=x’y’z’w’+x’yz’w+x’yzw+xy’z’w’+xy’zw’+xyz’w+xyzw

F= yw

+xy’w’ +y’z’w’

Trang 12

x y z w

F

Cost = 4*(1) + 7*(4) + 1*(7)

= 39 Delay = 1 + (2.2+1) + (3.4+1)

= 8.6

Trang 13

x y z w

Cost = 3*(1) + {1*(2)+2*(3)} + 1*(3)

= 14 i.p.v 39 Delay = 1 + (1.8+1) + (1.8+1)

= 6.6 i.p.v 8.6

F

Trang 14

10 11 01 00

00 01 11 10 x

y

z w

x

z

w v

y

Differs from course book

F(v,x,y,z,w)

Trang 15

10 11 01 00

00 01 11 10 x

y

z w

x

z

w v

x y

10

11 x

y u F=(u,v,x,y,z,w)

Differs from course book

Trang 16

 Karnaugh map

 Minimization with the Karnaugh map

 Quine-McCluskey

Trang 17

Determine all prime implicants

Determine all essential prime implicants

Create the Karnaugh map

Truth table or canonical form

Trang 18

y z

1

F=x’y’z’+wz+xyz+w’y F= x’y’z’ +wz+xyz+w’y F=x’y’z’+ wz +xyz+w’y

1

1 1

F=x’y’z’+wz+ xyz +w’y

1 1

F=x’y’z’+wz+xyz+ w’y

1 1

Rule:

- Take product term per product term and indicate where in the Karnaugh map it equals 1

Trang 19

y z

wz

1 1 1

wx’y’

1 1 1

Rule:

- Analyze each 1-minterm

- Determine the largest sub-cube(s) that contain(s) the minterm and

Trang 20

1 1

wz w’y

Trang 21

y z

- Take all essential prime implicants as initial list

- Repeatedly add a prime implicant to the list that contains the largest number of not yet covered 1-minterms When there are two that contain the same number of not yet

Trang 22

+(.6+4*.4+1)=7 Delay =(1)+(.6+3*.4+1) +(.6+3*.4+1)=6.6

=6% faster

Trang 24

Cost=(5*1)+(12*(5+1))+(1*(12+1))=90 Delay=(.6+1*.4)+(.6+5*.4+1)+(.6+12*.4+1)=11

Trang 25

y

Trang 26

y

Trang 27

1 1

Minimization with the Karnaugh

map

• Minimisation Step 3: Determine all essential prime implicants

Trang 28

Cost=1+(4*(3+1))+(1*(4+1))=22 (76% cheaper) Delay=(.6+1*.4)+(.6+3*.4+1)+(.6+4*.4+1)=7 (34% faster)

Trang 29

Cost =(1*1)+(5*(2+1))=16

(82% cheaper) Delay =(.6+1*.4)+(.6+2*.4+1)

+(.6+2*.4+1)+(.6+2*.4+1)

=8.2 (25% faster)

Trang 30

y

Trang 31

y

Trang 32

0 0 0

0 0

Is already the minimum coverage

F0min2=(v+y)(w+x)(v’+z)

Trang 33

Cost=(1*1)+(3*(2+1))+(1*(3+1))=14 (84% cheaper) Delay=(.6+1*.4)+(.6+2*.4+1)+(.6+3*.4+1)=6.2 (44% faster)

Trang 34

We’ll see that, depending on the technology mapping,

we will eventually obtain for an ASIC realisation:

OR-AND-INV

Cost = 11 (Rel cost=12%) Delay = 4 (Rel delay=36%) NOR

Cost = 10 (Rel cost=11%) Delay = 4.2 (Rel delay=38%)

Trang 35

 Karnaugh map

 Don’t care conditions

 Quine-McCluskey

Trang 36

Don’t care conditions

• Incompletely specified Boolean function

BCD → 7-segment

a

b c d

Trang 37

• Step 1: Create Karnaugh maps

Trang 38

• Step 2: determine all prime implicants

Trang 39

• Step 3: Determine all essential prime implicants

1 0 1 1

0 1 1 1

x x x x

1 1 x x x

y

z

w a

Complete coverage

1 0 0 1

0 0 0 1

x x x x y

Complete coverage

Trang 40

• Step 4: Determine minimum coverage

0 0 1 1

1 1 0 1

x x x x

1 1 x x

g Selection of the cube that realises

the remaining minterm:

- Select all cubes that realise the minterm and are already essential for another function;

in this case, both are already essential

- Select that cube that appears

in the smallest number of other functions to keep the fan-out as low as possible

Trang 41

• Note down the standard form

1 0 1 1

0 1 1 1

x x x x

1 1 x x x

y

z

w a

y’w’

z yw x

a=y’w’+z+yw+x

Trang 42

y’w’

z yw x

Trang 43

y’w’

z yw x

c=z’+w+y

Trang 44

y’w’

z yw x

c=z’+w+y

y’w’

y’z yz’w zw’

x

d=y’w’+y’z+yz’w+zw’+x

Trang 45

e

z yw x

c=z’+w+y

y’z yz’w zw’

d=y’w’+y’z+yz’w+zw’+x

y’w’

zw’

Trang 46

z yw x

c=z’+w+y

y’z yz’w zw’

d=y’w’+y’z+yz’w+zw’+x e=y’w’+zw’

Trang 47

z yw x

c=z’+w+y

y’z yz’w zw’

Trang 49

• Cost when realising as Σ (1-minterms):

Trang 50

• Delay when realising as Σ (1-minterms):

 Critical path=c (9-input OR)

 c: (1)+(.6+4*.4+1)+(.6+9*.4+1)=9.4 (100%)

• Delay for minimal 2-layer-implementation

 Critical path=d (3-input AND & 5-input OR)

 d: (1)+(.6+3*.4+1)+(.6+5*.4+1)=7.4 (79%)

Trang 51

 Karnaugh map

 Quine-McCluskey

Trang 52

• Method with Karnaugh map

 OK for human minimisation : visually oriented

 no guarantee for optimum solution

• Computer method

 Quine-McCluskey

 table oriented

 leads to optimum solution

 is the basis of all CAD circuit design tools

 hardly doable by hand

Trang 53

 Gate arrays: NAND, NOR

 Custom library: AOI, OAI, …

 PLA

 FPGA

Trang 54

 Gate arrays: NAND, NOR

 PLA

 FPGA

Trang 55

• Properties of the methodology followed:

 When minimizing 1-minterms: INV-AND-OR

 When minimizing 0-maxterms: INV-OR-AND

 Any function can be realized in two layers of logic with this methodology

 The fan-in of the gates can become arbitrary large

• Properties of gate arrays:

 They only contain m -input NAND or m -input NOR gates

• Technology mapping is:

 Translating a circuit consisting of INV-AND-OR

to one with only m -input NAND

Trang 56

Conversion Replace each AND and OR by NAND or NOR

Optimisation Eliminate double inversions

Replace each n-input AND (OR) by a few m-input

ANDs (ORs), with m<n Decomposition

Retiming Try to make all input-output delays equal

Trang 58

• Conversion rules in practice:

The realisation with only NAND or only NOR is faster:

we save an invertor per gate!

Trang 64

 Custom library: AOI, OAI, …

 PLA

 FPGA

Trang 65

• ASICs have AOI en OAI: small and fast!

• For small functions ( not in course book ): Realise the inverse function with AND-OR

Trang 66

xy z

F’

F

w xy z

F Cost=(5*1)+6=11 (12%)

Delay=1+(.6+6*.4)=4 (36%)

Trang 67

• For large functions:

Transform to NAND or NOR Realise as AND-OR or OR-AND

Determine critical path Replace repeatedly 2 layers of gates on critical path by AOI/OAI

Trang 68

Transform to NAND and NOR

Determine the critical path

y

z

Cost=11 (79%) Delay=5.2 (72%)

Replace 2 gates on critical path by AOI

Replace 2 gates on critical path by AOI (2e possibility)

Analyze the other path

y

z

Cost=10 (71%) Delay=3.8 (53%)

Analyze the other path

y

z

Cost=9 (64%) Delay=3.8 (53%)

Trang 69

 PLA

 FPGA

Trang 70

• Technology mapping: realisation as

AND-OR, without the necessity for decomposition

Trang 71

 PLA

 FPGA

Trang 72

• Technology mapping is similar as for custom design but i.o AOI/OAI we search for sub-circuits of 4 or 5 variables, first on the critical path, next on the other paths

• For FPGAs technology mapping is done by automatic tools (see next slide); when

prototype: no hand optimalisation, when final product: hand optimalisation

beneficial Also for ASICs automatic tools exist, hand optimalisation is beneficial

• BCD → 7-segment: create 7 truth tables i.f.o 4 variables: the rest is done by the tools

Trang 74

Trang 75

z

x y z

b

F

x y y’

z a

1

x y z

b

F

x y z

b

F

x y z

b

F

x y z

b

F

x y z

b

F

x y z

b

F

Trang 76

• Cause: different delay in two paths

• Solution: see next slide

Trang 77

y z

z

a b

x y z

c

x y z

c 1

1

x y z

c

x y z

c

x y z

c

Trang 78

• Cause: different delay in multiple paths

• Example: see next slide

Trang 79

Correct timing behavior:

Hazard-free design

x’’

x x’

a F

Trang 80

• Are hazards a problem?

 For synchronous circuits, they are not

 Unless they control the clock of a memory element

 For asynchronous circuits, they always are a problem

 This is why asynchronous design is heavily demotivated for FPGAs (the delay of the different paths is only known after APR- Automatic Placement and Routing)

Trang 81

• Basic RTL building blocks

Trang 82

Trang 85

xi yi

c c

Trang 86

x1 y1

c2

s1FA

x2 y2

c3

s2FA

x3 y3

c4

s3Critical path: x0 or y0 to c4: 1 XOR + 4 AND + 4 OR

In principal 1 CLB per bit Because of special circuitry (dedicated carry chain):

1 CLB per 2 bits

Trang 87

Trang 88

• Ripple-carry adder is slow because the

• Speed-up is possible by computing for

Trang 89

Trang 90

x1 y1

c2

f1FA

x2 y2

c3

f2FA

Trang 91

Trang 93

c1

c2

c3

Trang 95

Trang 96

• Goal: implement a unit that can realise all

16 Boolean functions of 2 bits

• The unit has two inputs X and Y and 4 select bits S 3 S 2 S 1 S 0 that select the

wanted function

• The coding of the select bits is identical

to the function number in the table of possible Boolean functions

Trang 99

Trang 100

• Realisation principle: use an adder in front of which we place a modifier circuit (Arithmetic-Logic Extender)

• This principle has already been applied for the 2-complement adder/subtractor: this was an adder in front of which we placed an exor circuit to allow for

subtraction

Trang 101

FA FA

Trang 102

M selects the type of operation: 0=logic, 1=arithmetic

S0 and S1 select the operation

FA

a0 b0

f0

ALE FA

a1 b1

f1

ALE FA

a2 b2

f2

ALE FA

a3 b3

f3

ALE FA

Trang 103

M S1 S0 Function F X Y C0

0 0 0 Complement A’ A’ 0 0

0 0 1 AND A AND B A AND B 0 0

0 1 1 OR A OR B A OR B 0 0

Trang 104

S1

S0

c0

Trang 105

Trang 106

Y

Trang 107

a1 b1

f1

ALE FA

a2 b2

f2

ALE FA

a3 b3

f3

ALE FA

Trang 108

Trang 110

A1 0

E Decoder

C11 8

A1 0

E Decoder

C15 12

A1 0E

Decoder

A3 2E

Trang 111

Trang 114

4-to-1 selector

D7 4

S1 04-to-1

selector

D11 8

S1 04-to-1

selector

D15 12

S1 0

4-to-1 selector

D3 0

S1 0

Y

Trang 115

Trang 116

• Problem with high fan-in MUX:

 fan-in OR gate too big

 all inputs have to be routed to 1 central location: substantial routing delay and difficult routing

• Solution: bus with tristate drivers

Trang 117

• In an FPGA (lab session) a limited number

of tristate buffers is foreseen, connected

to horizontal long lines It is possible to indicate for a certain signal that we prefer

to map it to a long line.

• Note that a Boolean signal already can have 4 different values:

 0: the logical signal “0”

 1: the logical signal “1”

 x: don’t care

 Z: high-impedant

• Simulations will allow to visualize each of the 4 different values

Trang 118

Trang 120

A1 0Any

1 1/2 CLB

Trang 121

Priority encoder

D7 4

Priority encoder

D11 8

Priority encoder

D15 12

Priority encoder

MUX 4-to-1 MUX

Trang 122

Trang 123

1 1 1 1 1

y1

x1

x0

y0L

Trang 124

1 1 1 1 1

y1

x1

x0

y0L

Trang 125

x2 y2Comp

x3 y3Comp

x4 y4Comp

x5 y5Comp

x6 y6Comp

G L

Comp

x1 y1

x2 y2Comp

x3 y3

x4 y4Comp

x5 y5

x6 y6Comp

Trang 126

y=1 when X<192

x7 x6

y y=1 when X is even

x0y

x7 x6

y

X is

8 bits

Trang 127

Trang 128

 m bits disappear at one side

 m bits are created at the other side

 For an arithmetic shift (word = 2-complement)

 For a left shift m zeros are shifted in from the right

 For a right shift m times the MSB is shifted in from the left (for 2-

complement)

 For a logic shift

 It is possible to indicate which value is shifted in

 m bit left shift is multiplication with 2m

 m bit right shift is division by 2m

Tiêu đề	Điện tử số Part 2
Trường học	Imec
Chuyên ngành	Digital Design
Thể loại	Giáo trình
Năm xuất bản	2001

Định dạng
Số trang	131
Dung lượng	2,49 MB