Điện tử số part 3

Bộ môn Điện tử số do Thầy Nam phó viên trưởng trường ĐHBKHN biên soạn đem lại cho các bạn 1 cách tiếp cận đơn giản dễ hiểu với môn này

• Combinatorial circuits: without status

 Sequential circuits: with status

• FSMD design: hardwired processors

• Language based HW design: VHDL

clock , gets a certain value

 Clock period: duration between two consecutive 1 → 0 transitions of the clock

 Clock frequency: 1 / (clock period)

 Duty cycle: (duration that the clock equals 1) / (clock period)

 Rising edge: 0 → 1 transition of the clock

 Falling edge: 1 → 0 transition of the clock

 0: the logical signal “0”

 1: the logical signal “1”

 x: don’t care

 Z: high impedant

 U: undefined

• The oscillation is called critical race

• The oscillation only happens when the delay of both gates is exactly equal

• When the delays are not equal, the fastest gates determines the end result:

implementation and run-time dependent ⇒

undefined

Q’

QClock

H-to-L delay: 1+2.4+1.4=4.8

D must not change “immediately before” H-to-L of theclock (during the setup time); reason: clock changesbetween the switching of D and of D’ hence Set and

(setup time = H-to-L of invertor)

R

DCSD’

transition, S and R will not switch from H to L at the

come high following the D input)

R

DCSD’

R

Analogously, D may not switch “immediately after” H-to-L

of the clock (during the hold time)

R

5.2/3.8

DC

QQ’

Symbol

Given values:

5.2=C to QL→H3.8=C to QH→L

 Transparent when clock is high

 Remembering the last value when clock is low

• Level sensitive latches give problems for shift registers for example

 The input signal may ripple through multiple stages during one clock-high phase

 making it very hard to meet setup/hold time requirements

 See next slide

Q2

Q3

Clk

ClkX

QQ’

ClkDBARS

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

• Basic RTL building blocks

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

Triangle next to clockmeans positiveedge-triggeredNegative edge-triggered

Negative level triggered

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

Circuits that use

JK flip-flops are cheaperthan those using SR flip-flops:

more don’t cares

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

(for design of D flip-flop)

D Q(next)

Excitation table(for design with D flip-flop)

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

(for design of T flip-flop)

T Q(next)

1 Q’

Excitation table(for design with T flip-flop)

QQ’

T

 Asynchronous set and reset

• Design of synchronous sequential circuits

• Design of asynchronous sequential circuits

QQ’

Clear

DClk

PRS Q

Q’CLR

Asynchronous set and reset are

useful to put the flip-flopinitially in a known state(see lab sessions)

 If they were only connected to the second layer, the first layer would not know in what state the second layer was put and could give a conflicting command to the second layer at the next rising clock edge, e.g reset since D=0 and

at the same time an asynchronous preset

clear active low ?

 Because ‘wired-or’ of ‘open drain’ circuits is used to avoid short circuits when there are multiple sources driving them:

Nopreset

preset

Nopreset

preset

R

Open drain

Implements an AND function (hence

‘wired-or’ ) with unlimited number of

inputs:

The bus is only ‘1’ when all inputs to the bus are equal to

‘1’

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

• Basic RTL building blocks

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

Count=2

CE=1

Count=3

CE=1CE=1

should be specified in each of the states.

1 We are in state “Count=0”

2 CE input equals 0: we are waiting at the tip of the edge

3 CE=1: wait at tip of other edge, but do not count yet!

4 Rising clock edge: go to “Count=1”, still with CE=1

5 CE input becomes 0: wait at tip of other edge

Count=0

CE=0CE=0

Count=1CE=1

Count=1CE=1

Count=2

CE=1

Count=3

CE=1CE=1

Q1Q0=10

CE=1

Q1Q0=11

CE=1CE=1

It is already the minimum number.

• Step 3: Encode the states:

the D type for its simplicity.

• Step 5: Realise the circuit See next slides:

Q1Q0=10

CE=1

Q1Q0=11

CE=1CE=1

Present state Next state

⇒ D to be applied

0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

D0 Q0Q’

D0 Q0Q’

ClkCE

D0 Q0Q’

CE Q1 Q0

Q1n

Q0n

D1 Q1Q’

D0 Q0Q’

CE Q1 Q0

Q1n

Q0n

D1 Q1Q’

D0 Q0Q’

CE Q1 Q0

Q1n

Q0n

D1 Q1Q’

D0 Q0Q’

CE Q1 Q0

Q1n

Q0n

D1 Q1Q’

D0 Q0Q’

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

• Basic RTL building blocks

becomes 1, immediately causing the adder/subtractor to switch to “subtract” mode, but NOT causing the register to load a new value!!!

The loading will only occur at the next state transition (i.e the next clock edge)

CounterCE

Add/Subtract

RegisterLE

A/S’

Combinatorial

 the output is indicated for each state

 the output is only function of the current state, not of the inputs applied

 Hence, the output value is indicated in the circle representing the state

Q1Q0=01Y=0CE=1

Q1Q0=10Y=0

CE=1

Q1Q0=11Y=1

CE=1CE=1

is already the minimum number

• Step 3: Encode the states:

the D type for its simplicity.

• Step 5: Realise the circuit See next slides:

Q1Q0=01 Y=0

CE=1

Q1Q0=10 Y=0

CE=1

Q1Q0=11 Y=1

CE=1CE=1

on thecurrentstate,not onthe inputs

⇒ D to be applied

0 1 1 0

1 0 0 1CE

D0 Q0Q’

D0 Q0Q’

Y

ClkCE

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

Y

Danger for Glitch!

unintentionally clock: harmful

when probe is connected due to increased capacitance and hence also increased delay

 When the output with the glitch is connected to

a combinatorial circuit that eventually is the input of a register:

at its input only at the clock edge

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

the “CE” input equals 1 and stops counting when

“CE” equals 0 The “Y” output value equals 1 when the count=3 while the input “CE” equals 1.

1 We are in state “Count=2”

2 CE input equals 1: wait at tip of edge with Y=0

3 Rising clock edge: go to “Count=3”, still with CE=1: Y=1

4 C input becomes 0: wait at tip of other edge with Y=0;combinatorial circuit driven by Y reacts, clocked don’t

Count=0

CE=0/Y=0CE=0/Y=0

adder/subtractor switches to “add”, and LE=0

When the next clock edge comes while CE=0, register will not load

CounterCE

Add/Subtract

RegisterLE

A/S’

Combinatorial

 the output is function of the current state, and

of the applied inputs

 Hence the output is specified next to each transition

Q1Q0=10

CE=1/Y=0

Q1Q0=11

CE=1/Y=0CE=1/Y=1

is already the minimum number.

• Step 3: Encode the states:

the D type for its simplicity.

• Step 5: Realise the circuit See next slides:

Present state Next state/Outputs

on thecurrentstate,but also onthe inputs

⇒ D to be applied

0 1 1 0

1 0 0 1CE

Q0

Q1

D0 Q0Q’

0 0 0 0

0 0 1 0CE

Y

Q0

Q1

Y

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

Y

Danger for Glitch!

CE Q1 Q0

Q1n

Q0n

D1 Q1Q’

D0 Q0Q’

D0 Q0Q’

D0 Q0Q’

Y

S*=F(S,I)

NextStateCombi-nato-rialLogic

O=H(S)

OutputCombi-nato-rialLogic

DClk

Q

DClk

Q

Outputs O

S*=F(S,I)

NextStateCombi-nato-rialLogic

O=H(S,I)

OutputCombi-nato-rialLogic

DClk

Q

DClk

Q

Outputs O

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

• Basic RTL building blocks

 What is the meaning of “We count up”?

 Do we have to “count” (C=1) and “up” (D=0)

 or is it sufficient that the direction is “up” (C=X and D=0)?

of inputs from each state

 See next slide

 Note: when an output needs to remain high during several consecutive states, it should be assigned a ‘high’ value in each of these states!!

Each output should be assigned a value in each

state!

CD=11 Y=0

CD=11

d2

CD=11 Y= 1

CD=10 Y= 1

CD=11 Y=0

d0

CD=11 Y=0

u1

CD=10 Y=0

CD=10 Y=0

d1

CD=11 Y=0 CD=10

Y=0

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

• Basic RTL building blocks

• Formally: states sj and sk are equivalent (sj≡ sk) if and only if

 ∀ i ∈ I: h(sj,i)=h(sk,i): both states produce the same output for each combination of inputs and

 ∀ i ∈ I: f(sj,i) ≡ f(sk,i): the next states are equivalent for each input combination

of the state diagram first

NEXT STATE / OUTPUT

PRESENT STATE CD=0X CD=10 CD=11

per combination of 2 states

NEXT STATE / OUTPUT

PRESENT STATE CD=0X CD=10 CD=11

different outputs for the same inputs

NEXT STATE / OUTPUT

PRESENT STATE CD=0X CD=10 CD=11

equivalent to make the current states equivalent

NEXT STATE / OUTPUT

PRESENT STATE CD=0X CD=10 CD=11

OKOK

Minimum number

of states: 3 ie.{u0,d0}=s0{u1,d1}=s1{u2,d2}=s2

NEXT STATE / OUTPUT

PRESENT STATE CD=0X CD=10 CD=11

s0 s0/0 s1/0 s2/1

s 1 s 1 /0 s 2 /0 s 0 /0

s 2 s 2 /0 s 0 /1 s 1 /0

CD=10 Y=0

CD=11 Y=0

CD=0X Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=0X Y=0

CD=10 Y=1

CD=11

-ning, but better 1 state too much than too little

manipulate the implication table

• Hence an imaginary example showing all problems:

NEXT STATE / OUTPUT

per combination of 2 states

NEXT STATE / OUTPUT

outputs for same inputs

NEXT STATE / OUTPUT

equivalent to make the current states equivalent

NEXT STATE / OUTPUT

1-4 1-3

OK

1-4 1-3

0-2 OK

1-4 1-3

4-5 2-4 0-2 OK

1-4 1-3

4-5 2-4 0-2 0-21-4OK

1-4 1-3

4-5 2-4 4-52-4 0-2 0-21-4OK

1-4 1-3

4-5 2-4 4-52-4 0-2, 4-51-2 0-2 0-21-4

OK

4-5 2-4 4-52-4 0-2, 4-51-2 0-2 0-21-4

OK

equivalent next states would have been equivalent

NEXT STATE / OUTPUT

4-5 2-4 4-52-4 0-2, 4-51-2 0-2 0-21-4

OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2 0-2: ? 0-21-4

OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2 0-2: ? 0-21-4

OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2 0-2: ? 0-2: ?1-4: ?

OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2 0-2: ? 0-2: ?1-4: ?

OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2

0-2: ? 0-2: ?1-4: ?OK

4-5 2-4 4-52-4 0-2, 4-51-2

0-2: ? 0-2: ?1-4: ?OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2

0-2: ? 0-2: ?1-4: ?OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2

0-2: ? 0-2: ?1-4: ?OK

1-4: ? 1-3:OK

4-5 2-4 4-52-4 0-2, 4-51-2

0-2: ? 0-2: ?1-4: ?

of states: 3 ie

{s0,s2}=u0{s1,s3,s4}=u1{s5}=u2

NEXT STATE / OUTPUT

PRESENT STATE AB=00 AB=01 AB=10

u0 u1/1 u0/0 u1/1

u 1 u 0 /0 u 2 /1 u 1 /1

u2 u0/0 u1/1 u0/1

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

• Basic RTL building blocks

• There are n! possible encodings ( n

choices for the first state, n -1 for the second, etc.)

• Often chosen encodings:

 Straightforward

 Minimum-bit-change

 One-hot

 E.g a counter whose count value is sent to a display

• Straightforward encoding is dangerous for glitches and leads to non-minimal area

and power consumption: multiple bits have to change at each state transition

(multiple bit-changes seldomly happen concurrently; each bit-change requires some logic

to implement it; each bit-change consumes power)

• Minimum-bit-change encoding is mostly used when area and power need to be minimized (CMOS)

1011

1

1

22

1110

1

1

11

Gray codecounter

two of the three pairs

Possibleencoding:

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0 Y=0

Q0D

Q1D

Q2D

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

CD=11 Y=0

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

CD=11 Y=0

Y=0

s2

CD=10 Y=0

CD=11 Y=0

Y=0

CD=11 Y=1

 Each departing transition to another state

requires an AND gate at the R input

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

 Most expensive flip-flop

 Most difficult design

 Largest number of don’t cares: probably cheapest (and fastest) combinatorial control logic

 Used when a different signal sets resp resets the flip-flop

 Most easy design

 No don’t cares: probably most expensive (and slowest) combinatorial control logic

 Used when the same signal sets resp resets the flip-flop, i.e when the value of a signal has

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

Q1D

Q0D

C

1.5 CLB

Q1T

Q0T

C

Q0

Q1

CD

NEXT STATE / OUTPUT

xx

NEXT STATE / OUTPUT

Q0

Q1

CD

NEXT STATE / OUTPUT

CC

D

Q0

Q1

CD

NEXT STATE / OUTPUT

xx

Q0

Q1

CD

NEXT STATE / OUTPUT

D

D

 Step 1: State diagram

 Step 2: State minimization

 Step 3: State encoding

 Step 4: Choice of the flip-flop type

 Step 5: Realization of the combinatorial logic

 Step 6: Timing analysis

• Design of asynchronous sequential circuits

 Max clock frequency = 1/(delay of critical path)

 Critical path is the path with the longest combinatorial delay between two clock edges

 Example:

Q1D

Q0D

CD

Y

 Asynchronous sequential circuits: outputs and state change as soon as an input changes

• Fundamental mode restriction:

 only one input may change at a time; the next input change may only occur when all effects

to the previous input change died out

• Goal: design of small asynchronous circuits, e.g interfaces between two synchronous islands with not-correlated clocks or clocks with unpredictable clock skew

and one output Q.

 If E is high, a rising edge on I causes Q to go high.

 Q stays high until E goes low.

 While E is low, Q is low.

Avoidance of input skew

State transition diagram

Primitive flow tableMinimized flow tableState assignmentElimination of critical racesHazard free combinatorial design

Avoidance of input skew