Ky thuat so

The omitted variable is the variable that have different number - Or we will have the sum function that omits one variable.. The omitted variables are the variable that have different nu

Digital system design

Digital signal status

Wave form

Decimal base 10

Binary base 2

Hexadecimal base 16

From decimal to binary

Surplus Surplus Surplus Surplus

Surplus Surplus Surplus

Decimal to hexadecimal

Binary to Hexadecimal

Hexadecimal to Binary

Binary characteristics

Transform

-1

2 Signed Binary Arithmetic:

- The calculation and result must have similar number of

bits

- If result are not in the bit range, should increase the

number of bits of the calculation)

- Like signed decimal Arithmetic

- 6

+ 3

: 1 0 1 0 : 0 0 1 1

+

1 0 0 1

- 7 : + 4

+ 5

: 0 1 0 0 : 0 1 0 1

16

- 7

+ 5

: 1 0 0 1 : 0 1 0 1

-

0 1 0 0 + 4 : (Kq sai)

-

0 1 1 1 + 7 :

20

d Mã ký tự ASCII:

Seven Segment Displays

Retro LED Watch (Circa 1970s)

This presentation will demonstrate how

 A seven-segment display can be used to display the decimal

numbers 0-9 and some alpha characters

 A common anode seven-segment display works

 A common cathode seven-segment display works

 To select the resistor value for a seven-segment display

21

Truth Tables for logic operators

Truth table: tabular form that uniguely represents the relationship

between the input variables of a function and its output

Truth Tables (cont.)

 Q: Let a function F() depend on n variables

How many rows are there in the truth table of F() ?

 A: 2n rows, since there are 2n possible binary

patterns/combinations for the n variables

Boolean Function

 Function formed from binary variable and binary equation: NOT, AND, OR

 EX:

 Simplify the following Boolean expression:

 Simplify the following Boolean expression:

 Simplify the expression

Các tích chuẩn (minterm) và tổng chuẩn (Maxterm):

- Minterm : In a Boolean function, a product term in which all the variables appear is called a minterm of the function

- Maxterm: A sum term that contains all the variables in

complemented or un-complemented form is called a

Minterms and Maxterms for n

42

Canonical Forms (Unique)

 Any Boolean function F( ) can be expressed as a

unique sum of minterms and a unique product of

maxterms (under a fixed variable ordering)

 In other words, every function F() has two

canonical forms:

 Canonical Sum-Of-Products (sum of minterms)

 Canonical Product-Of-Sums (product of maxterms)

Canonical Forms (cont.)

The minterms included are those mj such that

F( ) = 1 in row j of the truth table for F( )

The maxterms included are those Mj such that

F( ) = 0 in row j of the truth table for F( )

* Don’t care value (X):

Don’t care value can be 0 or 1

Circuit Implementation of a Logic Expression with Gates

X = (A + B)C

Logic Function A

B C

A+B B

 Determine the final output waveform X for the circuit, with input waveforms A, B, and C as shown

 Reduce the combinational logic circuit

- Write down the output expression

- Simplify the equation

 In a certain chemical-processing plant, a liquid chemical is used in

a manufacturing process The chemical is stored in three different tanks

 A level sensor in each tank produces a HIGH voltage when the level of chemical in the tank drops below a specified point

 - Design a circuit that monitors the chemical level in each tank

and indicates when the level in any two of the tanks drops below the specified point

IC 74LS138

2-to-4 Line Decoder with Enable Input

Logic Symbol Truth Table

Logic Expressions Logic Circuit

0 0 0

0 0 0

0

0 0 0

0 0

1 1

1 1 1

A 0

E 0

1 1 1

0 0 0

0 0 0

0

0 0 0

0 0

1 1

1 1 1

2-to-4 Line Decoder

Logic Symbol Truth Table

Logic Expressions

Logic Circuit

Karnaugh Maps (K maps)

What are Karnaugh 1 maps?

logic circuits

you can transfer logic values from a Boolean statement or

a truth table into a Karnaugh map

visualize the logic relationships between the variables and leads directly to a simplified Boolean statement

1 Named for the American electrical engineer Maurice Karnaugh

 The Karnaugh map is completed by entering a ‘1‘(or ‘0’)

in each of the appropriate cells

 Within the map, adjacent cells containing 1 (or 0) are

grouped together in twos, fours, or eights

Karnaugh maps

2016/3/14 Boolean Algebra PJF - 69

The types of structures

that are either minterms or

are generated by repeated

- Liên kết đôi: Khi liên kết (OR) hai ô có giá trị 1 (Ô_1) kề cận với nhau trên bìa K, ta sẽ được 1 số hạng tích mất đi 1 biến so với tích chuẩn (biến mất đi là biến khác nhau giữa 2 ô) Hoặc khi liên kết (AND) hai ô có giá trị 0 (Ô_0) kề cận với nhau trên bìa K, ta sẽ được 1 số hạng tổng mất đi 1 biến so với tổng chuẩn (biến mất đi là biến khác nhau giữa 2 ô)

Double connection (2 nearby blocks are 1 or 0):

- we will have the multiply function that omits one variable The omitted variable is the variable that have different number

- Or we will have the sum function that omits one variable The omitted variable is the variable that have different number

- Liên kết 4: Tương tự như liên kết đôi khi liên kết 4

Ô_1 hoặc 4 Ô_ 0 kề cận với nhau, ta sẽ loại đi được 2 biến (2 biến khác nhau giữa 4 ô)

Four-connection (4 nearby blocks are 1 or 0):

- we will have the multiply function that omits 2 variables The omitted variables are the variable that have different number

- Or we will have the sum function that omits 2 variables The omitted variables are the variable that have different number

Eight-connection (8 nearby blocks are 1 or 0):

- we will have the multiply function that omits 3 variables The omitted variables are the variable that have different number

- Or we will have the sum function that omits 3 variables The omitted variables are the variable that have different number

DA

DB

Four nearby blocks

DB

CB

Four nearby blocks

Eight nearby blocks

79

* Steps to simplify S.O.P:

- Write number 1 into Karnaugh blocks

- Connect block have number 1 Make sure two nearby blocks are connected at least one time One connection produce one multiply result

- The final result is the sum of multiply result above

80

, ,

( A B C D

Rút gọn hàm sau



 ( 0 , 1 , 4 , 5 , 6 , 7 , 14 , 15 ) )

D , C , B , A

F A C  B C

C A

Don't Care Conditions

• There may be a combination of input values which

– will never occur

– if they do occur, the output is of no concern

• The function value for such combinations is called a

don't care

• They are denoted with x or – Each x may be

arbitrarily assigned the value 0 or 1 in an

implementation

• Don’t cares can be used to further simplify a

function

Minimization using Don’t Cares

• Treat don't cares as if they are 1s to

Don’t care term

Example

• Simplify the function f(a,b,c,d)

whose K-map is shown at the

96

Internal structure of a 2-to-1

multiplexer

 The design of a 2-to-1 multiplexer is shown below

 If S=0 then the output “Y” has the same value as the input “I0”

 If S=1 then the output “Y” has the same value as the input “I1”

0 1

1 1 1 1

I 1 I 0

00 0

01 1

11 10 S

0 1 1 0

0 0 1 1 S

 7400 Series TTL Logic Chips

 The 7400 NAND Chip: pin layout

 7400 Series Implementation

 Implementing f = x1x2 + x2'x3 using 7400 series ICs

Movie Chips

 Design the control circuit using three variables: PWM, Direction, Brake

a) Logic Algebra

 Design the control circuit for a gaming using 4 inputs

 Circuit works only reset switch is 1 When reset switch is 0 all led will be OFF

 One led is ON if input to resistor is 1

 Just One led is ON when all player push button

R1

Reset

1 2

R3 R1

D2 Play er3

Sequential Logic Circuits

output is purely a function of the inputs

the values of past and present inputs

Sequential circuit concepts

the output to be fed back into the input:

circuit

memory

R=0 and S=0 will hold value

Application of the SR Latch

 An important application of SR latches is for

recording short lived events

 e.g pressing an alarm bell in a hospital

RS Latch

R

S

Q

RS Latch

R

S

Q

bed1 light

bed2 light

warning bell

bed1 button

bed2 button

master reset

1

11

 Sequential counter have 1 clock (CK) input and many outputs

The Output are the Flipflop output

 When feeding one pulse clock, the status (number)

of the counter will change

COUNTER

Status diagram of the counter

 Counter is constructed from

two connected FlipFlop

There are two type of counters

 Asynchronous counter (Bộ điếm nối tiếp): output of previous FF is the pulse

input of the current FF

 Count Up: counter increase 1 when have one pulse input

 Count Down: counter decrease 1 when have one pulse input

 Synchronous (Bộ đếm song song) : the input pulse (CK) of all FF are

connected to each other When pulse occurs all status of FF will change

 Using to design an arbitrary counter loop (counter do not have order)

• Count Down

• Count Up

Design a counter (m 2 n ):

- Identify the undesired status of the loop (the stopping number)

- Using this status to activate the preset and clear input to reset the status of the counter to the initial value

EX: Using T-FF pulse down edge and one preset input, to design the counter up m = 5, and initial value is 0

EX: Using JK-FF Pulse down edge and one

Preset, Clear active low; to design counter

down m = 5 and initial value is 2

Bộ đếm song song (Synchronous Counter): :

 The input pulse (CK) of all FF are connected to each other When pulse occurs all status of FF will change

 Do not need to consider the activated condition of Pulse (up or down) Consider the current status and next status

 Design a arbitrary counter loop

Step to design

 - Calculate number of FF need to be used

 - Draw the table to illustrate the relation between current and next status

Current status

Q n-1 … Q 1 Q 0

Next status

Q + n-1 … Q +

1 Q +

0

0 … 0 0

EX: Using T-FF active up edge, design the counter: Q 2 Q 1 Q 0 : 010, 101, 110, 001, 000, 111, 100, 011, 010, …

 There are two method to solve the undesired value in the loop

 Method 1: undesired value will be assign a value Needing to start the initial value for the counter The initial value is one of the desired value

EX: Design counter D-FF active up

edge, Pr and Cl active up edge

Method 2: assign an undesired value one value in the loop

Current FF input Next value

Serial-in to Parallel-out (SIPO) Shift Register 4-bit Serial-in to Parallel-out Shift Register

Count Up

Count down

4-bit Serial-in to Serial-out Shift Register

this type of Shift Register also acts as a temporary storage device or as a

time delay device for the data, with the amount of time delay being controlled

by the number of stages in the register, 4, 8, 16 etc or by varying the

application of the clock pulses Commonly available IC’s include the

74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line Commonly

available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift

Registers

4-bit Parallel-in to Serial-out Shift Register

Parallel-in to Parallel-out (PIPO) Shift Register

This type of shift register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above

Digital Design Process

 Design Loop for Digital Hardware

 The basic design loop:

 Initial design takes

creativity and

experience

 CAD tools are used

for simulation and to

work out details

 The Entire Development Process

 Design is only one part

 Verification and testing

are also important – this

is called design verification

 Errors may not be uncovered until after the prototype is made

 Errors may not be uncovered until after “release”!

 Pentium bug

 Test the circuit to determine if it meets the timing requirements

 Correct functionality does not necessarily lead to fast speed

 The physical design / layout will affect the timing

 Inherent gate delays

 Physical wiring leaves metal traces that have resistance

 CAD Tools

 There are a number of commonly used industry standard CAD tools

 CAD = Computer Aided Design

 Altera, Cadence, Mentor Graphics, Synopsys, Synplicity, Xilinx

 Tools are used for multiple purposes

 Synthesis, timing simulation, functional simulation, layout

 Can even download the design onto a PCB

Analog Signal

Continuous—represented analogously as a value of a continuously variable parameter

i) position of a needle on a meter

ii) rotational angle of a gear

iii) amount of water in a vessel

iv) electric charge on a capacitor

Analog-to-Digital Conversion

Terminology

analog-to-digital converter: ADC, A/D, A2D; converts an analog signal to a digital signal

digital-to-analog converter: DAC, D/A, D2A

An embedded system’s surroundings typically involve many analog signals

analog change resulting

from changing one bit

ADC using successive

approximation

 Given an analog input signal whose voltage should

range from 0 to 15 volts, and an 8-bit digital encoding, calculate the correct encoding for 5 volts Then trace the successive-approximation approach to find the

ADC Converter 5V

ADC converter using reference

source

Digital To Analog (DAC)