VHDL tổng hợp

VHDL tổng hợp

–}} End of automatically maintained sectionarchitecture RSFF of RSFF is

sel : in STD_LOGIC_VECTOR(2 downto 0);

y : out STD_LOGIC_VECTOR(7 downto 0)

);

end DEMUX1_8;

–}} End of automatically maintained section

architecture DEMUX1_8 of DEMUX1_8 is

–}} End of automatically maintained section

architecture GiaiMa7Doan of GiaiMa7Doan is

}} End of automatically maintained section

architecture NhiPhan_Gray of NhiPhan_Gray is

begin

with A select

G<= "0000" when "0000",

end sosanh4bit;

–}} End of automatically maintained section

architecture sosanh4bit of sosanh4bit is

begin

x1<=’1′ when a>b else ’0′;

x2<=’1′ when a=b else ’0′;

x3<=’1′ when a — enter your statements here –

a : in STD_LOGIC_VECTOR(3 downto 0);

b : in STD_LOGIC_VECTOR(3 downto 0);sel : in STD_LOGIC_VECTOR(1 downto 0);

q : out STD_LOGIC_VECTOR(3 downto 0));

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–}} End of automatically maintained section

architecture dem16 of dem16 is

end process;

– enter your statements here –end dem16;

Hình mô phỏng :

–}} End of automatically maintained section

architecture demJonhson of demJonhson is

begin

end process;

– enter your statements here –

architecture ghidich8bitVntRnt of ghidich8bitVntRnt isbegin

Thiết kế bộ ghi dịch 8 bit vào nối tiếp ra song song

architecture ghidich8bit_vnt_rss of ghidich8bit_vnt_rss is

signal temp:std_logic_vector (n-1 downto 0);

elsif(clk’event and clk=’1′) then

temp<=temp((n-2) downto 0)&d;

Thiết kế bộ đếm mã Gray 4 bit

–}} End of automatically maintained section

architecture demgray4bit of demgray4bit is

type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);

signal s: state;

begin

nest_state:process(RST,CLK)begin

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if D=’0′ then

s <= s0;else

s <= s1;end if ;when S1 =>

if D=’0′ then

s <= s2;else

s <= s3;end if ;when S2 =>

if D=’0′ then

s <= s4;else

s <= s5;end if ;

when S3 =>

if D=’0′ then

s <= s6;else

s <= s7;end if ;when S4 =>

if D=’0′ then

s <= s0;else

s <= s1;end if ;when S5 =>

if D=’0′ then

s <= s2;else

s <= s3;