Tài liệu Real - PCI docx

Features • Fully 2.2 PCI compliant 64-bit, 0-66 MHz PCI Initiator/ Target Interface • Zero wait-state burst operation • Programmable single-chip solution with customizable back-end funct

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, XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Archindry, NeoCAD, NeoCAD EPIC, NeoCADPRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc , all XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, Alli-anceCORE, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire,LCA, Logic Cell, LogiCORE, LogiBLOX, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM,SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, and ZERO+ are trademarks of Xilinx, Inc The Program-mable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc.

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Xilinx PCI Solutions (www) www.xilinx.com/pci

Xilinx Home Page www.xilinx.com

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Dear PCI customer,

On behalf of the PCI Team at Xilinx, and our CORE partners, welcome to our March 1999 PCI Data Book, and thank you foryour interest in Xilinx PCI Solutions

As the inventor and leading provider of Field Programmable Gate Array Technology, we want to pledge our continuing mitment to support your great ideas in logic design and PCI applications

com-Since the last version of this databook we have added the Real 64/66 PCITM, the industry's first general-purpose 64-Bit, 66MHz PCI Solution, and the PCI32 Spartan XL, a single-chip PCI solution at half the cost of standard PCI bridge chips.Our mission is to provide you with a high-quality PCI solution that offers better flexibility, higher performance, and lower costthan any other available solution Xilinx PCI allows you to integrate a PCI interface with your unique logic, into one flexibleprogrammable device Since the first PCI product introduction in February 1996, we have developed a complete solution forPCI including super-fast FPGAs, easy-to-use predictable LogiCORE modules with guaranteed timing, as well as PCIboards, drivers, and design examples We believe you will find Xilinx PCI Solution interesting and we hope that you will con-sider us for future designs

Together we can bring the great ideas to life!

Sincerely

Per Holmberg

LogiCORE Product ManagerCORE Solutions Group

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1 Introduction

10 Sales Offices, Sales Representatives, and Distributors

Section Titles

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Introduction 1 - 1Using an FPGA for PCI 1 - 1Using Xilinx for PCI 1 - 1Highest-Performance PCI 1 - 1Lowest-cost PCI 1 - 1The Real-PCI from Xilinx 1 - 1Real Compliance 1 - 1Real Flexibility 1 - 2Real Performance 1 - 2Real Availability 1 - 3Xilinx PCI Design Kits 1 - 3PCI over the Internet 1 - 4About this Databook 1 - 4

PCI Products

PCI64 Virtex Interface Version 3.0

Introduction 2 - 1Features 2 - 1Applications 2 - 2General Description 2 - 2Smart-IP Technology - guaranteed timing 2 - 3Functional Description 2 - 3PCI Configuration Space 2 - 3PCI I/O Interface Block 2 - 4Parity Generator/Checker 2 - 4Target State Machine 2 - 4Initiator State Machine 2 - 4User Application with Optional Burst FIFOs 2 - 4Interface Configuration 2 - 4Supported PCI Commands 2 - 4Burst Transfer 2 - 4Bandwidth 2 - 4Timing Specification 2 - 5Verification Methods 2 - 5Ping Reference Design 2 - 5Device Utilization 2 - 6Recommended Design Experience 2 - 6

PCI32 Virtex Version 3.0

Introduction 2 - 7Features 2 - 7Applications 2 - 8General Description 2 - 8Smart-IP Technology - guaranteed timing 2 - 9Functional Description 2 - 9PCI Configuration Space 2 - 9PCI I/O Interface Block 2 - 10Parity Generator/Checker 2 - 10Target State Machine 2 - 10Initiator State Machine 2 - 10User Application with Optional Burst FIFOs 2 - 10Interface Configuration 2 - 10Supported PCI Commands 2 - 10Burst Transfer 2 - 10Bandwidth 2 - 11

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Timing Specification 2 - 11Verification Methods 2 - 11Ping Reference Design 2 - 11Device Utilization 2 - 12Recommended Design Experience 2 - 12

PCI32 4000 XLA Interface Version 3.0

Introduction 2 - 13Features 2 - 13Applications 2 - 14General Description 2 - 14Smart-IP Technology - guaranteed timing 2 - 15Functional Description 2 - 15PCI I/O Interface Block 2 - 15Parity Generator/Checker 2 - 15Target State Machine 2 - 15Initiator State Machine 2 - 15PCI Configuration Space 2 - 15User Application with Optional Burst FIFOs 2 - 16Interface Configuration 2 - 16Supported PCI Commands 2 - 16Burst Transfer 2 - 16Bandwidth 2 - 17Timing Specification 2 - 17Verification Methods 2 - 18Ping Reference Design 2 - 18Synthesizable PCI Bridge Design Example 2 - 18Device Utilization 2 - 18Recommended Design Experience 2 - 18

PCI32 SpartanXL Interface Version 3.0

Introduction 2 - 19Features 2 - 19Applications 2 - 20General Description 2 - 20Smart-IP Technology - guaranteed timing 2 - 21Functional Description 2 - 21PCI I/O Interface Block 2 - 21Parity Generator/Checker 2 - 21Target State Machine 2 - 21Initiator State Machine 2 - 21PCI Configuration Space 2 - 21User Application with Optional Burst FIFOs 2 - 22Interface Configuration 2 - 22Supported PCI Commands 2 - 22Burst Transfer 2 - 22Bandwidth 2 - 23Timing Specification 2 - 23Verification Methods 2 - 23Ping Reference Design 2 - 24Synthesizable PCI Bridge Design Example 2 - 24Device Utilization 2 - 24Recommended Design Experience 2 - 24

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PCI32 Spartan Master & Slave Interface

Introduction 2 - 25Features 2 - 25Applications 2 - 26General Description 2 - 26Smart-IP Technology 2 - 27Functional Description 2 - 27PCI I/O Interface Block 2 - 27Parity Generator/Checker 2 - 27Target State Machine 2 - 27Initiator State Machine 2 - 27PCI Configuration Space 2 - 27User Application with Optional Burst FIFOs 2 - 27Interface Configuration 2 - 28Supported PCI Commands 2 - 28Burst Transfer 2 - 28Bandwidth 2 - 28Timing Specification 2 - 29Verification Methods 2 - 29Ping Reference Design 2 - 30Synthesizable PCI Bridge Design Example 2 - 30Device Utilization 2 - 30Recommended Design Experience 2 - 30

Synthesizable PCI Bridge Design Examples

Introduction 2 - 31General Description 2 - 31Functional Description 2 - 33BAR0 Configuration 2 - 33BAR1 Configuration 2 - 34Register File Interface 2 - 34Target FIFO Interface 2 - 34Initiator FIFO Interface 2 - 34Pinout 2 - 35Core Modifications 2 - 35Verification Methods 2 - 35Recommended Design Experience 2 - 35Reference Design License 2 - 35

PCI64 PCI Prototyping Board

Nallatech Limited 2 - 37Introduction 2 - 37Features 2 - 37Options 2 - 38General Description 2 - 38Configuration 2 - 38Software 2 - 39

HotPCI Spartan Prototyping Board

Virtual Computer Corporation 2 - 41Introduction 2 - 41Features 2 - 41Options 2 - 41General Description 2 - 42Software 2 - 42Functional Description 2 - 42Configuration with the CCM 2 - 42Configuration with an Xchecker cable 2 - 43

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DriverWorks Windows Device Driver Development Kit Version 2.0

Compuware NuMega 2 - 45Introduction 2 - 45Support 2 - 45Features 2 - 45Description 2 - 45Licensing 2 - 47

VtoolsD Windows Device Driver Development Kit Version 3.0

Compuware NuMega 2 - 49Introduction 2 - 49Support 2 - 49Features 2 - 49Description 2 - 50Licensing 2 - 50

Synthesizable PCI Power Management Design Example

Features 2 - 51General Description 2 - 52Functional Description 2 - 52Capabilities Linked List 2 - 52Power Management Register Block 2 - 53User-defined Configuration Space 2 - 54PME Generation 2 - 54Pinout 2 - 54Core Modifications 2 - 54The cfg file 2 - 54The pcim_top/pcis_top file 2 - 54Web download 2 - 54Editing the cfg file 2 - 55Verification Methods 2 - 55Recommended Design Experience 2 - 55

FPGA Products

LogiCORE PCI Supported Virtex FPGAs

Features 3 - 1Description 3 - 1

LogiCORE PCI32 Supported Spartan and SpartanXL FPGAs

Introduction 3 - 3Spartan Series Features 3 - 3Additional SpartanXL Features 3 - 4Universal PCI Interfaces 3 - 4

Design Methodology

LogiCORE PCI Configuration 4 - 1Core Configuration in VHDL and Verilog 4 - 2Selectable Options 4 - 2Enable 66 MHz (Virtex PCI64 only) 4 - 2Latency Timer 4 - 2Base Address Register Enable 4 - 2External Subsystem 4 - 2Cap List Enable 4 - 2INTA# Enable 4 - 2User Config Space 4 - 2Core Features 4 - 2Base Address Registers 4 - 2

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PCI Compliance Checklists

Virtex PCI Compliance Checklist

Component Product Information 5 - 1Component Electrical Checklist 5 - 1

5 V Signaling 5 - 23.3 V Signaling 5 - 4Loading and Device Protection 5 - 6Timing Specification 5 - 764-bit Components 5 - 8

XC4000XLA PCI Compliance Checklist

Spartan-XLPCI Compliance Checklist

LogiCORE PCI V3.0 Cores PCI Compliance Checklist

Component Product Information 5 - 25Component Configuration Checklist 5 - 26Organization 5 - 26Device Control 5 - 28Device Status 5 - 28Base Addresses 5 - 29VGA Devices 5 - 30General Component Protocol Checklist (Master) 5 - 31General Component Protocol Checklist (Target) 5 - 33Component Protocol Checklist for a Master Device 5 - 35Test Scenario: 1.1 PCI Device Speed Tests 5 - 35Test Scenario: 1.2 PCI Bus Target Abort Cycles 5 - 36Test Scenario: 1.3 PCI Bus Target Retry Cycles 5 - 38Test Scenario: 1.4 PCI Bus Single Data Phase Disconnect Cycles 5 - 39Test Scenario: 1.5 PCI Bus Multi-Data Phase Target Abort Cycles 5 - 40Test Scenario: 1.6 PCI Bus Multi-Data Phase Retry Cycles 5 - 43Test Scenario: 1.7 PCI Bus Multi-Data Phase Disconnect Cycles 5 - 44Test Scenario: 1.8 Multi-Data Phase and TRDY# Cycles 5 - 45Test Scenario: 1.9 Bus Data Parity Error Single Cycles 5 - 48Test Scenario: 1.10 Bus Data Parity Error Multi-Data Phase Cycles 5 - 49Test Scenario: 1.11 Bus Master Timeout 5 - 50Test Scenario: 1.12 Target Lock 5 - 50Test Scenario: 1.13 PCI Bus Master Parking 5 - 51Test Scenario: 1.14 PCI Bus Master Arbitration 5 - 51Test Scenario 1.x Explanations 5 - 51Component Protocol Checklist for a Target Device 5 - 52Test Scenario: 2.1 Target Reception of an Interrupt Cycle 5 - 52Test Scenario: 2.2 Target Reception of a Special Cycle 5 - 52

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Test Scenario: 2.3 Target Detection of Address and Data Parity Error for Special Cycle 5 - 52Test Scenario: 2.4 Target Reception of I/O Cycles with Legal and Illegal Byte Enables 5 - 52Test Scenario: 2.5 Target Ignores Reserved Commands 5 - 52Test Scenario: 2.6 Target Receives Configuration Cycles 5 - 53Test Scenario: 2.7 Target Receives I/O Cycles with Address and Data Parity Errors 5 - 53Test Scenario: 2.8 Target Configuration Cycles with Address and Data Parity Errors 5 - 53Test Scenario: 2.9 Target Receives Memory Cycles 5 - 53Test Scenario: 2.10 Target Gets Memory Cycles with Address and Data Parity Errors 5 - 54Test Scenario: 2.11 Target Gets Fast Back to Back Cycles 5 - 54Test Scenario: 2.12 Target Performs Exclusive Access Cycles 5 - 54Test Scenario: 2.13 Target Gets Cycles with IRDY# Used for Data Stepping 5 - 54Test Scenario 2.x Explanations 5 - 55

Pinout and Configuration

Pinout and Configuration 6 - 1Layout Considerations 6 - 1Compatibility Considerations 6 - 1Pinout Tables 6 - 1Configuration Mode 6 - 1Pinout for the XC4013XLA PQ208 6 - 2Pinout for the XC4013XLA PQ240 6 - 5Pinout for the XC4028XLA HQ240 6 - 8Pinout for the XC4062XLA HQ240 6 - 11Pinout for the XC4062XLA BG432 6 - 14Pinout for the XCS20 TQ144 6 - 18Pinout for the XCS30 PQ208 6 - 20Pinout for the XCS30 PQ240 6 - 23Pinout for the XCS40 PQ208 6 - 26Pinout for the XCS40 PQ240 6 - 29Pinout for the XCV300 BG432 6 - 32

Resources

Resources 7 - 1PCI Special Interest Group (PCI-SIG) Publications 7 - 1PCI and FPGA XPERT Partners 7 - 1Supporting PCI Tools 7 - 2PCI Reference Books 7 - 3Xilinx Documents 7 - 3LogiCORE User's Lounge 7 - 3

Waveforms

Waveforms 8 - 1Target Configuration Read 8 - 2Target Configuration Write 8 - 4Initiator 32-bit Single Memory Read 8 - 6Initiator 32-bit Single Memory Write 8 - 8Initiator 32-bit Burst Memory Read Multiple 8 - 10Initiator 32-bit Burst Memory Write 8 - 12Initiator 32-bit Burst Memory Write with Disconnect 8 - 14Target 32-bit Single Memory Read 8 - 16Target 32-bit Single Memory Write 8 - 18Target 32-bit Burst Memory Read Multiple 8 - 20Target 32-bit Burst Memory Write 8 - 22Target 32-bit Burst Memory Write with Disconnect 8 - 24Target 32-bit Retry 8 - 26Target 32-bit Abort 8 - 28

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Initiator 64-bit Burst Memory Read Multiple 8 - 30Initiator 64-bit Burst Memory Write 8 - 32Initiator 64-bit Burst Memory Write with Disconnect 8 - 34Initiator 64-bit Memory Read of a 32-bit Target 8 - 36Initiator 64-bit Memory Write of a 32-bit Target 8 - 38Target 64-bit Burst Memory Read Multiple 8 - 40Target 64-bit Burst Memory Write 8 - 42Target 64-bit Burst Memory Write with Disconnect 8 - 44Target 64-bit Retry 8 - 46Target 64-bit Abort 8 - 48

Ordering Information and License Agreement

Xilinx PCI64 Design Kit 9 - 1Xilinx PCI64 Virtex 9 - 2Xilinx PCI32 Design Kit 9 - 2LogiCORE PCI32 Spartan 9 - 2Support, Updates, and Licensing 9 - 3Product Upgrades 9 - 3Additional PCI Products 9 - 4Obsolete products 9 - 4

Sales Offices, Sales Representatives, and Distributors

Headquarters 10 - 1Xilinx Sales Offices 10 - 1North American Distributors 10 - 2U.S Sales Representatives 10 - 2International Sales Representatives 10 - 4

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1 Introduction

Introduction



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Introduction

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PCI (Peripheral Component Interconnect) has become one

of the most popular bus standards, not only for personal

computers, but also for industrial computers,

communica-tion switches, routers, and instrumentacommunica-tion

PCI is also a significant design challenge; the stringent

electrical, functional, and timing specifications are difficult

to meet in any technology and the standard keeps evolving

to meet the dynamic needs of our industry

This is why you need a flexible PCI solution that will meet

both your current and future requirements, while

guaran-teeing full PCI compliance with no limitations on

perfor-mance or functionality

Using an FPGA for PCI

By integrating a fully-compliant PCI interface with an

appli-cation-specific back-end design into one FPGA, you can

achieve higher integration, higher performance and lower

cost than other PCI solutions

Further, the Xilinx PCI solution can be customized for a

specific application and, as a result, the highest possible

performance is achieved

The flexibility of an FPGA makes it possible to update the

PCI board, through software alone, in development or in the

field This significantly reduces your design risk and cuts

development time

Using Xilinx for PCI

We provide the most cost-effective and high-performance

PCI solution in the market by leveraging the flexibility of

Xil-inx Field Programmable Gate Arrays (FPGAs) We make

PCI easy to design by providing a complete solution of

proven cores, intuitive development tools, and world-class

technical support

Highest-Performance PCI

When we introduced the Real 64/66 PCI, we were first out

with a fully compliant, general-purpose 64-bit 66MHz PCI

solution By using our LogiCORE PCI64 for Virtex, you can

achieve the highest possible PCI performance, 528 MB/s

Lowest-cost PCI

With our low-cost FPGA family, Spartan and SpartanXL,

you can design your own unique PCI bridge with integrated

FIFOs, DMA, and custom logic, at a cost only half of other

available standard PCI bridge chips

The Real-PCI from Xilinx

The Real-PCI from Xilinx is engineered to address all yourrequirements on a fully compliant PCI system It providesyou with

We also characterize our PCI cores together with ourFPGAs to verify not only maximum timing, but also mini-mum and hold timing Then, when we know that the timingconstraints are met, we apply our unique Smart-IP technol-ogy to ensure that you achieve the same timing and func-tionality every time you implement the core Thanks to ourregular FPGA architecture with segmented routing, andbecause we use a modular core architecture where theFIFOs, DMA channels, and your unique back-end logic arede-coupled from the core, your own design will not affectthe PCI interface timing

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Real Flexibility

Our PCI cores are targeted to our standard off-the-shelf

FPGAs, which were designed to be PCI compliant This

gives you a range of device sizes and packages to choose

from, allowing you to integrate a fully-compliant Initiator/

Target PCI interface, scalable dual-port FIFOs,

customiz-able DMA channels, and 7,000 to 1,000,000 system gates

of your own unique logic, all on a single device, for the

low-est possible cost

Because the FPGA is programmable, you can adapt to

future needs and changes in the PCI standard by

reconfig-uring the FPGA device on your board

Real Performance

All Xilinx PCI cores operate at maximum throughput, with 0

wait-state bursts For example, the Xilinx Real-PCI 64/66

solution allows you to create 64-bit PCI systems that

oper-ate at up to 66MHz, delivering a sustained throughput of up

to 528 Mbytes per second - the maximum performance you

can get from PCI Our PCI 32/33 cores supports up to 132

Mbytes per second

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Real Availability

Real-PCI is here today It includes a complete family of

Log-iCORE designs that are fully characterized for our

XC4000XLA, Spartan, SpartanXL, and Virtex FPGAs By

using our standard, off-the-shelf manufacturing capability,

leading edge silicon processes, excellent quality and

test-ability, and lower manufacturing costs Plus Real-PCI is not

just cores and devices, it’s also a complete system of

devel-opment tools, support, services, and third-party

Xilinx-authorized XPERTS to help you every step of the way

Xilinx PCI Design Kits

To help you reduce your development time even further,

Xil-inx has teamed with Nallatech LTD and Virtual Computer

Corp., both providing PCI prototyping boards, NuMega

Software providing SW driver development tools, and

Memec Design Services providing PCI expertise and

design services With our partners, we offer two complete

PCI Design Kits, PCI64-DK for 64-bit 66MHz PCI, and

PCI32-DK for 32-bit 33MHz PCI The kits include

prototyp-ing boards, reference software drivers for Windows 95/98/

NT, full-featured SW driver development tools, and

synthe-sizable PCI bridge design examples in VHDL and Verilog

Xilinx PCI64 Design Kit

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PCI over the Internet

As a part of our Silicon Xpresso initiative, we provide the

LogiCORE products with all design files you need over the

Internet You will instantly have access to new versions of

the core, new features, new application notes, and

refer-ence designs As a Xilinx PCI customer, you select your

own unique user name and password to access the core

product To help you configure the PCI core we have an

intuitive graphical user interface (GUI) where you easily

select the settings and features that you need The process

is simple:

1 Enter your configuration data into the GUI

2 Click “Download,” and our Web tool builds your unique

PCI interface with guaranteed timing, which you then

download to your local computer

The design files include the PCI design netlist,

VHDL/Ver-ilog simulation model and instantiation wrapper, and

imple-mentation constraints files

About this Databook

The information in this databook is also available on the inx web-site, WebLINX at

Xil-www.xilinx.com/pciXilinx will use the web as primary means of delivering andupdating this information since it is so dynamic by nature

We strongly recommend that customers consult the web forthe latest information on new product availability anddatasheet revisions

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1 Introduction

PCI Products

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PCI Products

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With Xilinx LogiCORE PCI64 Virtex interface, a designer

can build a customized, 64-bit, 0-66 MHz fully PCI

compli-ant system with the highest possible sustained

perfor-mance, 528 Mbytes/sec, and up to 1 Million System Gates

in the Virtex family FPGA

Features

• Fully 2.2 PCI compliant 64-bit, 0-66 MHz PCI Initiator/

Target Interface

• Zero wait-state burst operation

• Programmable single-chip solution with customizable

back-end functionality

• Pre-defined implementation for predictable timing in

Xilinx Virtex Series FPGAs

• Incorporates Xilinx Smart-IP Technology

• 3.3 V Operation at 33-66 MHz

• 3.3 V and 5 V Operation at 0-33 MHz

• Master automatically handles 64-bit or 32-bit PCI

transactions without knowing the bus width of the target

• Fully verified design tested with Xilinx testbench and

hardware

• Configurable on-chip dual-port FIFOs can be added for

maximum burst speed

• Supported Initiator functions (PCI Master only)

- Memory Read, Memory Write, Memory Read

Multiple (MRM), Memory Read Line (MRL)

commands

- I/O Read, I/O Write commands

- Configuration Read, Configuration Write commands

- Bus Parking

- Special Cycles, Interrupt Acknowledge

- Basic Host Bridging

Device Features Used Bi-directional data buses

SelectIOBlock SelectRAM+™(optional user FIFO)Boundary scan (optional)

Supported Devices2/Percent Resources Used

Provided with Core

PCI Implementation Guide

PCI Data BookDesign File Formats Verilog/VHDL Simulation Model

Verilog/VHDL Instantiation Code

NGO NetlistConstraint Files M1 User Constraint File (UCF)

M1 Guide filesVerification Tools Verilog/VHDL TestbenchReference designs &

application notes

Example designs:PING64 Reference DesignSynthesizable PCI64 Bridge(SB07)

Design Tool Requirements

Tested tion Tools4

Entry/Verifica-For CORE instantiation:Synopsys FPGA ExpressSynopsys FPGA CompilerSynplicity SynplifyFor CORE verification:Cadence Verilog XLMTI ModelSim PE/Plus V4.7g

Xilinx provides technical support for this LogiCORE™ product when used as described in the User’s Guide and in the Application Notes Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed above, or if customized beyond that referenced in the product documentation, or if any changes are made in sections of design marked as “DO NOT MODIFY”

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Features (cont.)

• Supported Target functions (PCI Master and Slave)

- Type 0 Configuration Space Header

- Up to 3 Base Address Registers (memory or I/O with

adjustable block size from 16 Bytes to 2 GBytes,

medium decode speed)

- Parity Generation (PAR), Parity Error Detection

(PERR# and SERR#)

Multiple (MRM), Memory Read Line (MRL), Memory

Write Invalidate (MWI) commands

- 64-bit data transfers and 32-bit data transfers, burst

transfers with linear address ordering

- Target Abort, Target Retry, Target Disconnect

- Full Command/Status Registers

• Available for configuration and download on the web

- Web-based configuration tool

- Generation of proven design files

- Instant access to new releases

• Hot Swap CompactPCI boards

• Other applications that need PCI

General Description

The LogiCORE™ PCI64 Interfaces are pre-implementedand fully tested modules for the Xilinx Virtex Series FPGAs.The pinout for the device and the relative placement of theinternal Configurable Logic Blocks (CLBs) are pre-defined.Critical paths are controlled by TimeSpecs and guide files

to ensure predictable timing This significantly reducesengineering time required to implement the PCI portion ofyour design Resources can instead be focused on theunique back-end logic in the FPGA and on the system leveldesign As a result, LogiCORE™ PCI products can mini-mize your product development time

Xilinx Virtex Series FPGAs enable designs of fully compliant systems The devices meet all required electricaland timing parameters including AC output drive character-istics, input capacitance specifications (10pF), 3 ns setupand 0 ns hold to system clock, and 6 ns system clock to out-put These devices meet all specifications for both 3.3 V (0-

PCI-66 MHz) and 5 V PCI (0-33 MHz)

The PCI Compliance Checklist has detailed informationabout electrical compliance Other features that enable effi-cient implementation of a complete PCI system in the Vir-tex Series includes:

1 The exact number of CLBs depends on user configuration of the

core and level of resource sharing with adjacent logic For

exam-ple, a factor that can affect the size of the design are the number

and size of the BARs

2 Re-targeting the PCI core to an unlisted device or package will

void the guarantee of timing See “Smart-IP Technology -

guar-anteed timing” on page 3 for details

3 Use -6 for 0-66 MHz operation and -5 for 0-33 MHz operation

4 See Xilinx Web Site for update on tested design tools

Parity Generator/

Checker

P C I C o n f i g u r a t i o n S p a c e

Initiator State Machine

Interrupt Pin and Line Register

Latency Timer Register

Vendor ID, Rev ID, Other User Data

LC003

Target State Machine

PERR- IRDY- REQ-

FRAME- DEVSEL- STOP-

TRDY-Base Address Register 0

Base Address Register 1

Command/

Status Register

Base Address Register 2

REQ64- PAR64

ACK64-Figure 1: LogiCORE ™ PCI64 Interface Block Diagram

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• Block SelectRAM+™ memory: Blocks of on-chip

ultra-fast RAM with synchronous write and dual-port RAM

capabilities Used in PCI Interfaces to implement FIFO

• Select-RAM™ memory: on-chip ultra-fast RAM with

synchronous write option and dual-port RAM option

Used in PCI Interfaces to implement FIFO

• Individual output enable for each I/O

• Internal 3-state bus capability

• 8 global low-skew clock or signal distribution networks

• IEEE 1149.1-compatible boundary scan logic support

The Master and Slave Interface module is carefully

opti-mized for best possible performance and utilization in the

Virtex FPGA architecture When implemented in a

XCV300, 12% of the FPGA’s slices are used

Smart-IP Technology - guaranteed

timing

Drawing on the architectural advantages of Xilinx FPGAs,

new Xilinx Smart-IP technology ensures highest

perfor-mance, predictability, repeatability, and flexibility in PCI

designs The Smart-IP technology is incorporated in every

LogiCORE PCI Core

Xilinx Smart-IP technology leverages the Xilinx

architec-tural advantages, such as look-up tables (LUTs),

distrib-uted RAM, and segmented routing, as well as floorplanning

information, such as logic mapping and relative location

constraints This technology provides the best physical

lay-out, predictability, and performance Additionally, these

pre-determined features allow for significantly reduced compile

times over competing architectures

PCI Cores made with Smart-IP technology are unique by

maintaining their performance and predictability regardless

of the device size

To guarantee the critical setup, hold, and min and max

clock-to-out timing, the PCI core is delivered with Smart-IP

constraint files that are unique for a device and package

combination These constraint files guide the

implementa-tion tools so that the critical paths always are within PCI

specification Retargeting the PCI core to an unsupported

device will void the guarantee of timing Contact one of the

Xilinx XPERTs partners for support of unlisted devices and

packages See the XPERTs section in chapter 7 of the

Xil-inx PCI Data Book for contact information

Functional Description

The LogiCORE PCI64 Master and Slave Interface is

parti-tioned into five major blocks and an user application as

shown in Figure 1 Each block is described below

PCI Configuration Space

This block provides the first 64 Bytes of Type 0, version 2.1

Configuration Space Header (CSH) (see Table 1) to

sup-port software-driven “Plug-and Play” initialization and

con-figuration This includes information for Command, Status,and three Base Address Registers (BARs) These BARsillustrate how to implement memory- or I/O-mappedaddress spaces

Table 1: PCI Configuration Space Header

Each BAR sets the base address for the interface andallows the system software to determine the addressablerange required by the interface Each BAR designated as amemory space can be made to represent a 32-bit or a 64-bit space

Using a combination of Configurable Logic Block (CLB) flops for the read/write registers and CLB look-up tables forthe read-only registers results in optimized logic mappingand placement

flip-The capability for extending configuration space has beenbuilt into the backend interface This capability, includingthe ability to implement a CapPtr in configuration space,allows the user to implement functions such as AdvancedConfiguration and Power Interface (ACPI) in the backend

Cache Line Size

0Ch

Base Address Register 0 (BAR0) 10hBase Address Register 1 (BAR1) 14hBase Address Register 2 (BAR2) 18hBase Address Register 3 (BAR3) 1ChBase Address Register 4 (BAR5) 20hBase Address Register 5 (BAR5) 24hCardbus CIS Pointer 28hSubsystem ID Subsystem Vendor ID 2ChExpansion ROM Base Address 30h

Note:

Italicized address areas are not implemented in the LogiCOREPCI64 Virtex Interface default configuration These locations returnzero during configuration read accesses

Trang 26

PCI I/O Interface Block

The I/O interface block handles the physical connection to

the PCI bus including all signaling, input and output

syn-chronization, output three-state controls, and all

request-grant handshaking for bus mastering

Parity Generator/Checker

This block generates/checks even parity across the AD

bus, the CBE lines, PAR and the PAR64 signal It also

reports data parity errors via PERR- and address parity

errors via SERR-

This block controls the PCI interface for Target functions

The states implemented are a subset of equations defined

in “Appendix B” of the PCI Local Bus Specification The

controller is a high-performance state machine using

one-hot (state-per-bit) encoding for maximum performance

State-per-bit encoding of the next-state logic functions

facil-itates a high performance implementation in the Xilinx

FPGA architecture

This block controls the PCI interface for Initiator functions

Ini-tiator Control Logic also uses state-per-bit encoding for

maximum performance

User Application with Optional Burst FIFOs

The LogiCORE PCI64 Interface provides a simple,

general-purpose interface with a 64-bit data path and latched

address for de-multiplexing the PCI address/data bus The

general-purpose user interface allows the rest of the device

to be used in a wide range of 64-bit and 32-bit applications

Typically, the user application contains burst FIFOs to

increase PCI system performance An on-chip read/write

FIFO, built from the on-chip synchronous dual-port RAM

(Block SelectRAM+™) available in Virtex Series FPGAs,

supports data transfers in excess of 66 MHz

Several synthesizable re-usable bridge designs including

commonly used backend functions, such as doorbells and

mailboxes, are provided with the core

Interface Configuration

The LogiCORE PCI64 Interface can easily be configured to

fit unique system requirements by using Xilinx web-based

PCI configuration tool or by changing the Verilog, VHDL, or

VIEWlogic configuration file The following customization

options are supported by the LogiCORE product and

described in product documentation

• Initiator or target functionality (PCI Master only)

• Base Address Register configuration (1 - 3 Registers,

size and mode)

• Configuration Space Header ROM

• Initiator and target state machine (e.g., terminationconditions, transaction types and request/transactionarbitration)

• Burst functionality

• User Application including FIFO (back-end design)

Supported PCI Commands

Table 2 illustrates the PCI bus commands supported by theLogiCORE™ PCI64 Interface The PCI Compliance Check-list has more details on supported and unsupported com-mands

Table 2: PCI Bus Commands

Burst Transfer

The PCI bus derives its performance from its ability to port burst transfers The performance of any PCI applica-tion depends largely on the size of the burst transfer AFIFO to support PCI burst transfer can efficiently be imple-mented using the Virtex on-chip RAM features, both Dis-tributed and Block SelectRAM+™

sup-Each Virtex CLB supports four 16x1 RAM blocks Thiscorresponds to 64 bits of single-ported RAM or 32 bits ofdual-ported RAM, with simultaneous read/write capability.The Block SelectRAM+ can be used to create deep FIFOs

1111 Memory Write Invalidate No1 Yes

Note:

1 The Initiator can present these commands, however, they eitherrequire additional user-application logic to support them or have notbeen thoroughly tested

Trang 27

receiving data This Interface supports a sustained

band-width of up to 528 MBytes/sec The design can be

config-ured to take advantage of the ability of the LogiCORE

PCI64 Interface to do very long bursts Since the FIFO is

not of fixed size, bursts can go on for as long as the chipset

arbiter will allow Furthermore, since the FIFOs and DMA

are decoupled from the proven core, a designer can modify

these functions without affecting the critical PCI timing

The flexible Xilinx backend, combined with support for

many different PCI features, gives users a solution that

lends itself to being used in many high-performance

appli-cations Xilinx is able to support different depths of FIFOs

as well as dual port FIFOs, synchronous or asynchronous

FIFOs and multiple FIFOs The user is not locked into one

DMA engine, hence, a DMA that fits a specific application

can be designed

The theoretical maximum bandwidth of a 64-bit, 66 MHz

PCI bus is 528 MBytes/sec Attaining this maximum

band-width will depend on several factors, including the PCI

design used, PCI chipset, the processor’s ability to keep up

with your data stream, the maximum capability of your PCI

design, and other traffic on the PCI bus Older chipsets and

processors will tend to allow less bandwidth than newer

ones

No additional states are inserted in response to a

wait-state from another agent on the bus Either IRDY or TRDY

is kept asserted until the current data phase ends, as

required by the V2.2 PCI Specification

See Table 3 for PCI bus transfer rates for various

opera-tions

Table 3: LogiCORE PCI64 Transfer Rates

Timing Specification

The Virtex Series FPGA devices, together with the

Logi-COREPCI64 product enable design of fully compliant PCI

systems The maximum speed at which your back-end is

capable of running can be affected by the size of the design

as well as by the loading of the hot signals coming directly

from the PCI bus Table 4 shows the key timing parameters

for the LogiCORE PCI64 Interface that must be met for full

a behavioral host and target, and several “plug-in” modules,including a PCI signal recorder and a PCI protocol monitor.The Xilinx PCI testbench is a powerful verification tool that

is also used as the basis for verification of the PCI CORE The PCI LogiCORE is also tested in hardware forelectrical, functional, and timing compliance

Logi-Ping Reference Design

The Xilinx “PING64” Application Example, delivered in ilog and VHDL, has been developed to provide an easy-to-understand example which demonstrates many of the prin-ciples and techniques required to successfully use a Logi-CORE PCI64 Interface in a System On A Chip solution.The PING64 design is also used as a test vehicle when ver-ifying the PCI core

Ver-Zero Wait-State Mode

Operation Transfer Rate

Initiator Write (PCI ← LogiCORE) 3-1-1-1

Initiator Read (PCI → LogiCORE) 4-1-1-1

Target Write (PCI→ LogiCORE) 5-1-1-1

Target Read (PCI ← LogiCORE) 6-1-1-1

***Note: Initiator Read and Target Write operations have effectively

the same bandwidth for burst transfer

Parameter Ref PCI Spec.

LogiCORE PCI64 XCV300-064Min Max Min Max

CLK to Bus nals Valid3

Sig-TICKOF 2 6 22 6

CLK to REQ# and GNT# Valid3

GNT# Setup to CLK (CLB)

1 Controlled by TIMESPECS, included in product

2 Verified by analysis and bench-testing

3 IOB configured for Fast slew rate

4 Virtex Timing will be included when silicon testing is finished

Trang 28

Synthesizable PCI Bridge Design

(SB07)

The synthesizable PCI bridge design, SB07, is an

applica-tion bridge for use with the LogiCORE PCI64 Interface It is

delivered in Verilog and VHDL and has been fully tested

with various devices This example demonstrates how to

in-terface to the PCI core and provide a modular foundation

upon which to base other designs The reference design

can be easily modified to remove select portions of

func-tionality

This design is a general purpose data transfer engine to beused with the LogiCORE PCI64 Interface Figure 3 pre-sents a block diagram of the SB07 design Typically, theuser will customize the local interface to conform to a par-ticular peripheral bus (ISA, VME, i960) or attach to a mem-ory device The design is modular so that unused portionsmay be removed Other bridge applications can be de-signed using subsets of SB07 The Synthesizable PCIBridge Design Data Sheet lists the set of features and spe-cifics for the SB07 design

Device Utilization

The Target/Initiator options require a variable amount of

CLB resources for the PCI64 Interface

Utilization of the device can vary slightly, depending on the

configuration choices made by the designer Factors that

can affect the size of the core are:

• Number of Base Address Registers Used Turning off

any unused BARs will save resources

• Size of the BARs Setting the BAR to a smaller size

requires more flip-flops A smaller address space

requires more flip-flops to decode

• Latency timer Disabling the latency timer will save

resources It must be enabled for bursting

Recommended Design Experience

The LogiCORE PCI64 Interface is pre-implemented ing engineering focus at the unique back-end functions of aPCI design Regardless, PCI is a high-performance systemthat is challenging to implement in any technology, ASIC orFPGA Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx imple-mentation software, TIMESPECs, and guide files is recom-mended The challenge to implement a complete PCIdesign including back-end functions varies depending onconfiguration and functionality of your application Contactyour local Xilinx representative for a closer review and esti-mation for your specific requirements

allow-Figure 1: Block Diagram of Synthesizable Bridge Design for PCI64 LogiCORE Interface, SB07

RESOLVE

TARGET STATE LogiCORE PCI Interface

ADIO S_CBE

TARGET CONTROL

INITIATOR CONTROL

INITIATOR STATE

TRANSFER

TARGETFIFO

REGISTERS

BAR 1 CONTROL

FORCE_RETRY

XFER STATUS

XFER STATE

BAR 0 CONTROL

Target Burst Logic with FIFOs

Target Register Logic (non-burst) Initiator Transfer Engine with FIFOs

PCIM_LC SYNTHESIZABLE BRIDGE (SB07)

IFIFO_OUT IFIFO_IN IADDR ICONTROL

LDOUT LDIN LADDR LWE LRE LINT_N

TFIFO_OUT TFIFO_IN TADDR TCONTROL

PCI_TOP

PCI BUS

x8950

Trang 29

With Xilinx LogiCORE PCI32 Virtex Interface, a designer

can build a customized, 32-bit, 33 MHz fully PCI compliant

system with the highest possible sustained performance,

128 Mbytes/sec, and up to 300,000 System Gates in the

Virtex family FPGA

Features

• Fully 2.2 PCI compliant 32-bit, 33 MHz PCI

Initiator/Target Interface

• Programmable single-chip solution with customizable

back-end functionality

Xilinx Virtex Series FPGAs

• 3.3 V and 5 V Operation

• Fully verified design tested with Xilinx testbench and

hardware

maximum burst speed

• Supported Initiator functions

commands

- Bus Parking

Multi-standard SelectIOSelectMAP Configuration (optional)

Block SelectRAM+™(optional user FIFO)Boundary scan (optional)

Supported Devices2/Percent Resources Used

PCI Implementation Guide

PCI Data BookDesign File Formats Verilog/VHDL Simulation Model,

Verilog/VHDL Instantiation Code,

NGO Netlist,Constraint Files M1 User Constraint File (UCF)

M1 Guide filesVerification Tools Verilog/VHDL TestbenchReference designs &

application notes

Example designsPING Reference DesignSynthesizable PCI32 Bridge(SB08)

Tested cation Tools3

Entry/Verifi-For CORE instantiation:Synopsys FPGA ExpressSynopsys FPGA CompilerSynplicity SynplifyFor CORE verification:Cadence Verilog XLMTI ModelSim PE/Plus V4.7g

Xilinx provides technical support for this LogiCORE™ product when used as described in the Design and Implementation Guides and

in the Application Notes Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed above, or if customized beyond that referenced in the product documentation, or if any changes are made in sections of design marked as “DO NOT MODIFY”

Trang 30

• Supported Target functions (PCI Master and Slave)

adjustable block size from 16 Bytes to 2 GBytes,

medium decode speed)

(PERR# and SERR#)

- Extended Capabilities Registers (backend module)

Multiple (MRM), Memory Read Line (MRL), Memory

Write Invalidate (MWI) commands

- Interrupt Acknowledge

- 32-bit data transfers, burst transfers with linear

address ordering

- Full Command/Status Registers

• Available for configuration and download on the web

- Web-based configuration tool

- Instant access to new releases

• Hot Swap CompactPCI boards

• Other applications that need PCI

General Description

The LogiCORE™ PCI32 Master and Slave Interface haspre-implemented and fully tested modules for the Xilinx Vir-tex Series FPGAs The pinout for the device and the rela-tive placement of the internal Configurable Logic Blocks(CLBs) are pre-defined Critical paths are controlled byTimeSpecs and placement to ensure predictable timing.This significantly reduces engineering time required toimplement the PCI portion of your design Resources caninstead be focused on the unique back-end logic in theFPGA and on the system level design As a result, Logi-CORE™ PCI products can minimize your product develop-ment time

Xilinx Virtex Series FPGAs enable designs of fully compliant systems The devices meet all required electricaland timing parameters including AC output drive character-istics, input capacitance specifications (10pF), 3 ns setupand 0 ns hold to system clock, and 11 ns system clock tooutput These devices meet all specifications for both 3.3 Vand 5 V PCI

PCI-The PCI Compliance Checklist has detailed informationabout electrical compliance Other features that enable effi-cient implementation of a complete PCI system in the Vir-tex Series includes:

1 The exact number of Slices depends on user configuration of the

example, a factor that can affect the size of the design are the

number and size of the BARs

3 See Xilinx Web Site for updates on tested design tools

Checker

LC005

TRDY-Base Address 0

Base Address 1

Command/

Status Register

Base Address 2

Figure 1: LogiCORE ™ PCI32 Interface Block Diagram

Trang 31

• Block SelectRAM+™ memory: Blocks of on-chip

ultra-fast RAM with synchronous write and dual-port RAM

capabilities Used in PCI Interfaces to implement FIFO

Used in PCI Interfaces to implement FIFO

The Master and Slave Interface module is carefully

opti-mized for best possible performance and utilization in the

Virtex FPGA architecture When implemented in a

XCV300, 12% of the FPGA’s slices are used

timing

LogiCORE PCI Core

of the device size

The LogiCORE PCI32 Master and Slave Interface is

parti-tioned into five major blocks and an user application as

shown in Figure 1 Each block is described below

PCI Configuration Space

This block provides the first 64 Bytes of Type 0, version 2.1

Configuration Space Header (CSH) (see Table 1) to

sup-port software-driven “Plug-and-Play” initialization and

con-figuration This includes information for Command, Status,and three Base Address Registers (BARs) These BARsillustrate how to implement memory or I/O mapped addressspaces

Each BAR sets the base address for the interface andallows the system software to determine the addressablerange required by the interface Each BAR designated as amemory space can be made to represent a 32-bit space Using a combination of Configurable Logic Block (CLB) flip-flops for the read/write registers and CLB look-up tables forthe read-only registers results in optimized logic mappingand placement

The LogiCORE PCI32 Interface includes the ability to addextended configuration capabilities as defined in the V2.2PCI specification This capability, including the ability toimplement a CapPtr in configuration space, allows the user

to implement extended functions such as Power ment, Hot Swap CSR, and Message Based Interrupts in

Cache Line Size

0Ch

Base Address Register 0 (BAR0) 10hBase Address Register 1 (BAR1) 14hBase Address Register 2 (BAR2) 18hBase Address Register 3 (BAR3) 1ChBase Address Register 4 (BAR5) 20hBase Address Register 5 (BAR5) 24hCardbus CIS Pointer 28hSubsystem ID Subsystem Vendor ID 2ChExpansion ROM Base Address 30h

Note:

Italicized address areas are not implemented in the LogiCOREPCI32 Virtex Interface default configuration These locations returnzero during configuration read accesses

Trang 32

The I/O interface block handles the physical connection to

the PCI bus including all signaling, input and output

syn-chronization, output three-state controls, and all

request-grant handshaking for bus mastering

This block generates/checks even parity across the AD

bus, the CBE lines, and the PAR signal It also reports data

parity errors via PERR- and address parity errors via

SERR-

This block controls the PCI interface for Target functions

controller is a high-performance state machine using

one-hot (state-per-bit) encoding for maximum

perfor-mance State-per-bit encoding of the next-state logic

func-tions facilitates a high performance implementation in the

Xilinx FPGA architecture

This block controls the PCI interface for Initiator functions

Ini-tiator Control Logic also uses state-per-bit encoding for

maximum performance

The LogiCORE PCI32 Interface provides a simple,

gen-eral-purpose interface with a 32-bit data path and latched

address for de-multiplexing the PCI address/data bus The

general-purpose user interface allows the rest of the device

to be used in a wide range of 32-bit applications

increase PCI system performance An on-chip read/write

FIFO, built from the on-chip synchronous dual-port RAM

(Block SelectRAM+™) available in Virtex Series FPGAs,

supports data transfers in excess of 66 MHz

Several synthesizable re-usable bridge designs including

commonly used backend functions, such as doorbells and

mailboxes, are provided with the core

The LogiCORE PCI32 Interface can easily be configured to

fit unique system requirements by using Xilinx web-based

PCI configuration tool or by changing the Verilog or VHDL

configuration file The following customization options are

supported by the LogiCORE product and described in

product documentation

• Initiator or target functionality

• Base Address Register configuration (1 - 3 Registers,size and mode)

Table 2 illustrates the PCI bus commands supported by theLogiCORE™ PCI32 Interface The PCI Compliance Check-list has more details on supported and unsupported com-mands

Burst Transfer

The PCI bus derives its performance from its ability to port burst transfers The performance of any PCI applica-tion depends largely on the size of the burst transfer AFIFO to support PCI burst transfer can efficiently be imple-mented using the Virtex on-chip RAM features, both Dis-tributed SelectRAM and Block SelectRAM+™

sup-Each Virtex CLB supports four 16x1 RAM blocks Thiscorresponds to 64 bits of single-ported RAM or 32 bits ofdual-ported RAM, with simultaneous read/write capability Each Virtex device has two columns of Block RAM TheV300 device has 65,536 bits of Block SelectRAM+™ thatcan be used to create deep, dual-ported FIFOs

Master

PCI Slave

Note:

Trang 33

Xilinx LogiCORE PCI32 Interface supports fully compliant

zero wait-state burst operations for both sourcing and

receiving data This Interface supports a sustained

band-width of up to 128 MBytes/sec The design can be

config-ured to take advantage of the ability of the LogiCORE

PCI32 Interface to do very long bursts Since the FIFO is

not of fixed size, bursts can go on for as long as the chipset

arbiter will allow Furthermore, since the FIFOs and DMA

are decoupled from the proven core, a designer can modify

these functions without affecting the critical PCI timing

can be designed

The theoretical maximum bandwidth of a 32-bit, 33 MHz

PCI bus is 128 MBytes/sec Attaining this maximum

band-width will depend on several factors, including the PCI

design used, PCI chipset, the processor’s ability to keep up

with your data stream, the maximum capability of your PCI

design, and other traffic on the PCI bus Older chipsets and

ones

No additional states are inserted in response to a

wait-state from another agent on the bus Either IRDY or TRDY

is kept asserted until the current data phase ends, as

required by the V2.2 PCI Specification

See Table 3 for PCI bus transfer rates for various

opera-tions

Table 3: LogiCORE PCI32 Transfer Rates

The Virtex Series FPGA devices, together with the

Logi-COREPCI32 product enable design of fully compliant PCI

systems The maximum speed at which your back-end is

capable of running can be affected by the size of the design

as well as by the loading of the hot signals coming directly

from the PCI bus Table 4 shows the key timing parameters

for the LogiCORE PCI32 Interface that must be met for fullPCI compliance

Table 4: 33 MHz Timing Parameters [ns]

Verification Methods

Xilinx has developed a system-level testbench that allowssimulation of an open PCI environment in which a Logi-CORE-PCI-based design may be tested by itself or withother simulatable PCI agents Included in these agents are

a behavioral host and target, and several “plug-in” modules,including a PCI signal recorder and a PCI protocol monitor.Using these tools, the PCI developers can write microcode-style test scripts that can be used to verify different bus-operation scenarios, including those in the PCI ComplianceChecklist

The Xilinx PCI testbench is a powerful verification tool that

is also used as the basis for verification of the PCI CORE The PCI LogiCORE is also tested in hardware forelectrical, functional, and timing compliance

Logi-Ping Reference Design

The Xilinx “PING” Application Example, delivered in Verilogand VHDL, has been developed to provide an easy-to-understand example which demonstrates many of the prin-ciples and techniques required to successfully use a Logi-CORE PCI32 Interface in a System On A Chip solution.The PING design is also used as a test vehicle when veri-

Zero Wait-State Mode

LogiCORE PCI32 XCV300-5 Min Max Min Max

2 Verified by silicon characterization

Trang 34

Synthesizable PCI Bridge Design

(SB08)

The synthesizable PCI bridge design, SB08, is an

applica-tion bridge for use with the LogiCORE PCI32 Interface It is

delivered in Verilog and VHDL and has been fully tested

with various devices This example demonstrates how to

in-terface to the PCI core and provide a modular foundation

upon which to base other designs The reference design

can be easily modified to remove select portions of

func-tionality

This design is a general purpose data transfer engine to beused with the LogiCORE PCI32 Interface Figure 1 pre-sents a block diagram of the synthesizable PCI bridge de-sign Typically, the user will customize the local interface toconform to a particular peripheral bus (ISA, VME, i960) orattach to a memory device The design is modular so thatunused portions may be removed The Synthesizable PCIBridge Design Data Sheet lists the set of features and spe-cifics for the SB08 design

Figure 1: Block Diagram of Synthesizable Bridge Design for PCI32 LogiCORE Interface

The Target/Initiator options require a variable amount of

CLB resources for the PCI32 Interface

Utilization of the device can vary slightly, depending on the

configuration choices made by the designer Factors that

can affect the size of the core are:

• Number of Base Address Registers Used Turning off

any unused BARs will save resources

• Size of the BARs Setting the BAR to a smaller size

requires more flip-flops A smaller address space

requires more flip-flops to decode

• Latency timer Disabling the latency timer will save

resources It must be enabled for bursting

The LogiCORE PCI32 Interface is pre-implemented ing engineering focus at the unique back-end functions of aPCI design Regardless, PCI is a high-performance systemthat is challenging to implement in any technology, ASIC orFPGA Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx imple-mentation software, TIMESPECs, and guide files is recom-mended The challenge to implement a complete PCIdesign including back-end functions varies depending onconfiguration and functionality of your application Contactyour local Xilinx representative for a closer review and esti-mation for your specific requirements

TARGET CONTROL

INITIATOR CONTROL

INITIATOR STATE

TRANSFER

TARGETFIFO

REGISTERS

BAR 1 CONTROL

FORCE_RETRY

XFER STATUS

XFER STATE

BAR 0 CONTROL

Target Burst Logic with FIFOs

Target Register Logic (non-burst) Initiator Transfer Engine with FIFOs

IFIFO_OUT IFIFO_IN IADDR ICONTROL

LDOUT LDIN LADDR LWE LRE LINT_N

TFIFO_OUT TFIFO_IN TADDR TCONTROL

PCI_TOP

PCI

BUS

x8951

Trang 35

With Xilinx LogiCORE PCI32 4000 XLA Interfaces Version

3.0, a designer can build a customized, 32-bit, 33 MHz fully

PCI compliant system with the highest possible sustained

performance, 132 Mbytes/sec, and up to 124,000 system

gates in a XC4000XLA FPGA

Xilinx XC4000XLA FPGAs

• 5 V and 3.3 V operation

• Fully verified design

- Tested with Xilinx internal testbench and in hardware

(proven in FPGAs and HardWire devices)

maximum burst speed (see Xilinx Documents section)

• Supported Initiator functions

commands

- Bus Parking

Bi-directional data busesSelectRAM™ (optional user FIFO)Boundary scan (optional)

Supported Devices2/Resources Remaining

XLT to XLA Conversion Guide

PCI Data BookDesign File Formats Verilog/VHDL Simulation Model

Verilog/VHDL Instantiation Code

NGO NetlistConstraint Files M1 User Constraint File (UCF)

M1 Guide filesVerification Tools VHDL\Verilog Testbench

Reference designs &

application notes

Ping Reference DesignSynthesizable PCI Bridge Design

Tested cation Tools3

Entry/Verifi-For CORE instantiation:Synopsys FPGA Express, Compiler

Synplicity SynplifyFor CORE verification:Cadence Verilog XLMTI ModelSim PE/Plus V4.7g

Support

Xilinx provides technical support for all LogiCORE ucts when used as described in product documentation Xilinx cannot guarantee timing, functionality, or support if implemented in unspecified devices or customized beyond that referenced in product documentation, or if changes are made to “DO NOT MODIFY” sections of the design

Trang 36

• Supported Target functions

adjustable block size from 16 bytes to 2 GBytes,

slow or medium decode speed)

(PERR# and SERR#)

Multiple (MRM), Memory Real Line (MRL), Memory

Write, Invalidate (MWI) commands

- 32-bit data transfers, burst transfers with linear

address ordering

- Full Command/Status Register

• Available for configuration and download on the Web

- Web-based configuration with intuitive GUI

Applications

• PCI add-in boards such as graphic cards, video

adapters, LAN adapters and data acquisition boards

• Embedded applications within networking,

telecommunication, and industrial systems

pre-to ensure that timing is always met This significantlyreduces engineering time required to implement the PCIportion of your design Resources can instead be focused

on unique back-end logic in FPGA and on system leveldesign Consequently, LogiCORE™ PCI products can min-imize development time

Xilinx XC4000XLA Series FPGAs enables designs of fullyPCI-compliant systems The devices meet all requiredelectrical and timing parameters for 3.3V and 5V including

AC output drive characteristics, input capacitance cations (10pF), 7 ns setup and 0 ns hold to system clock,and 11 ns system clock to output

specifi-The XC4000XLA devices have programmable clampdiodes as required by the PCI 3.3V electrical specification.For more details about this see the XC4000XLA FPGAData Sheet

The PCI Compliance Checklist (See the Xilinx PCIDatabook) has additional details about electrical compli-ance Other features that enable efficient implementation of

a complete PCI system in the XC4000XLA include:

1 The exact number of CLBs depends on user configuration of the

example, a factor that can affect the size of the design are the

number and size of the BARs

3 See Xilinx Web Site for update on tested design tools

Checker

LC005

TRDY-Base Address 0

Base Address 1

Command/

Status Register

Base Address 2

Figure 1: LogiCORE ™ PCI32 Interface Block Diagram

Trang 37

used in PCI Interfaces to implement the FIFO

The module is carefully optimized for best possible

sus-tained performance and utilization in the XC4000XLA

FPGA architecture When implemented in a XC4013, more

than 50% of the FPGA’s resources remain for integrating a

unique back-end interface and other system functions into

a fully programmable one-chip solution When

imple-mented in a XC4062, 90% of the FPGA’s resources

remain

timing

LogiCORE PCI Core

of the device size

The LogiCORE PCI32 4000 XLA Interfaces are partitioned

into five major blocks, and the user application as shown in

Figure 1 Each block is described below

The I/O interface block handles physical connection to thePCI bus including all signaling, input and output synchroni-zation, output three-state controls, and all request-granthandshaking for bus mastering

Generates/checks even parity across the AD bus, the CBElines, and the PAR signal Reports data parity errors viaPERR- and address parity errors via SERR-

This block manages control over the PCI interface for get functions The states implemented are a subset ofequations defined in “Appendix B” of the PCI Local BusSpecification The controller is a high-performance statemachine using state-per-bit (one-hot) encoding for maxi-mum performance State-per-bit encoding has narrowerand shallower next-state logic functions that closely matchthe Xilinx FPGA architecture

Tar-Initiator State Machine

This block manages control over the PCI interface for tor functions The states implemented are a subset of equa-tions defined in “Appendix B” of the PCI Local BusSpecification The Initiator Control Logic also uses state-per-bit encoding for maximum performance

Initia-PCI Configuration Space

This block provides the first 64 Bytes of Type 0, V 2.1, figuration Space Header (CSH) (see Table 1) to supportsoftware-driven “Plug-and Play” initialization and configura-tion This includes Command, Status, and three BaseAddress Registers (BARs) BAR 2 is not shown in figure 1.These BARs illustrate how to implement memory- or I/O-mapped address spaces Each BAR sets base address forthe interface and allows system software to determineaddressable range required by the interface Using a com-bination of Configurable Logic Block (CLB) flip-flops for theread/write registers and CLB look-up tables for the read-only registers results in optimized packing density and lay-out

Con-With this release, the hooks for extending configurationspace has been built into the backend interface Thesehooks, including the ability to implement a CapPtr in config-uration space, allows the user to implement functions such

as Advanced Configuration and Power Interface (ACPI) inthe backend design

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The LogiCORE PCI32 4000 XLA Interface is a

general-pur-pose interface with a 32-bit data path and latched address

for de-multiplexing the PCI address/data bus The

general-purpose user interface allows the rest of the device to be

used in a wide range of applications

increase PCI system performance (An Application Note is

available, please see the Xilinx Documents section) An

on-chip read/write FIFO, built from the on-on-chip synchronous

dual-port RAM (SelectRAM™) available in XC4000XLA

devices, supports data transfers in excess of 33 MHz

The LogiCORE PCI32 4000 XLA Interfaces can easily be

configured to fit unique system requirements using Xilinx

web-based graphical configuration tool or changing the

VHDL or Verilog configuration file The following

customiza-tion is supported by the LogiCORE product and described

Table 2 illustrates the PCI bus commands supported by theLogiCORE™ PCI32 4000 XLA Interfaces The PCI Compli-ance Checklist, found later in this data book, has moredetails on supported and unsupported commands

Burst Transfer

The PCI bus derives its performance from its ability tosupport burst transfers The performance of any PCIapplication depends largely on the size of the burst transfer

A FIFO to support PCI burst transfer can efficiently beimplemented using the XC4000XLA on-chip RAM feature,SelectRAM™ Each XC4000XLA CLB supports two 16x1RAM blocks This corresponds to 32 bits of single-portedRAM or 16 bits of dual-ported RAM, with simultaneousread/write capability

Cache Line Size

0Ch

Base Address Register 0 (BAR0) 10h

Base Address Register 3 (BAR3) 1Ch

Cardbus CIS Pointer 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Note:

Italicized address areas are not implemented in LogiCORE PCI32

4000 XLA Interface default configuration These locations return

zero during configuration read accesses

Master

PCI Slave

Note:

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The Xilinx PCI32 4000 XLA Interfaces support a sustained

bandwidth of up to 132 MBytes/sec (except in the

XC4062XLA HQ240) The design can be configured to take

advantage of the ability of the LogiCORE PCI32 Interface

to do very long bursts Since the FIFO isn’t a fixed size,

burst can go on as long as the chipset arbiter will allow

Fur-thermore, since the FIFOs and DMA are decoupled from

the proven core, a designer can modify these functions

without effecting the critical PCI timing

can be designed

The theoretical maximum bandwidth of a 32 bit, 33 MHz

PCI bus is 132 MB/s How close you get to this maximum

will depend on several factors, including the PCI design

used, PCI chipset, the processor’s ability to keep up with

your data stream, the maximum capability of your PCI

design and other traffic on the PCI bus Older chipsets and

ones

In this version of the Interface, all devices are zero wait

state except for the XC4062XLA HQ240, which is a one

wait state design The XC4013XLA-09, XC4028XLA-09

and XC4062XLA-09 support zero wait-state burst, equal to

a sustained bandwidth of up to 132 MBytes/sec Only the

XC4062XLA HQ240 requires one wait-state while sourcing

data See Table 3 for a PCI bus transfer rates for various

operations in either zero or one wait-state mode

Table 3: LogiCORE PCI32 4000 XLA Transfer Rates

In the Zero wait-state mode, no wait-states are inserted

either while sourcing data or receiving data This allows a

100% burst transfer rate in both directions with full PCIcompliance No additional wait-states are inserted inresponse to a wait-state from another agent on the bus.Either IRDY or TRDY is kept asserted until the current dataphase ends, as required by the V2.2 PCI Specification

In one wait-state mode, the LogiCORE PCI32 4000 XLAInterface automatically inserts a wait-state when sourcingdata (Initiator Write, Target Read) during a burst transfer Inthis mode, the LogiCORE PCI32 4000 XLA Interface canaccept data at 100% burst transfer rate and supply data at50%

The XC4000XLA family, together with the LogiCOREPCI32products enables design of fully compliant PCI systems.Backend design can affect the maximum speed yourdesign is capable of Factors in your back-end designs thatcan affect timing include loading of hot signals comingdirectly from the PCI bus, and gate count Table 4 showsthe key timing parameters for the LogiCORE PCI32 Inter-faces that must be met for full PCI compliance

Table 4: Timing Parameters [ns]

Zero Wait-State Mode

One Wait-State Mode (XC4062XLA HQ240 only)

Note: Initiator Read and Target Write operations have effectively

the same bandwidth for burst transfer

LogiCORE PCI32 4000 XLA XC4000XLA-1 Min Max Min Max

GNT# Setup to CLK (CLB)

2 Verified by analysis and bench-testing

3 IOB configured for Fast slew rate

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Verification Methods

Xilinx has developed a testbench with numerous vectors to

test the Xilinx PCI design; this is included with the

Logi-CORE PCI32 4000 XLA Interfaces A version of this

test-bench is also used internally by the Xilinx PCI team to verify

the PCI32 Interfaces Additionally, the PCI32 Interfaces

have been tested in hardware for electrical, functional and

timing compliance

The testbench shipped with the interface verifies the PCI

interface functions according to the test scenarios specified

in the PCI Local Bus Specification, V2.1; see Figure 2 This

testbench consists of 28 test scenarios, each designed to

test a specific PCI bus operation Refer to the checklists

chapter in this databook for a complete list of scenarios

Figure 2: PCI Protocol Testbench

Ping Reference Design

The Xilinx LogiCORE PCI “PING” Application Example,

delivered in VHDL and Verilog, has been developed to

pro-vide an easy-to-understand example which demonstrates

many of the principles and techniques required to

success-fully use a LogiCORE PCI32 4000 XLA Interface in a

Sys-tem On A Chip solution

Synthesizable PCI Bridge Design Example

Synthesizable PCI bridge design examples, delivered inVerilog and VHDL, are available to demonstrate how tointerface to the LogiCORE PCI32 4000 XLA V3.0 Interfacesand provides a modular foundation upon which to baseother designs See separate data sheet for details

Utilization can vary widely, depending on the configurationchoices made by the designer Options that can affect thesize of the core are:

• Number of Base Address Registers Used Turning offany unused BARs will save on resources The core nowincludes a switch to force the entire deletion of unusedBase Address Registers

• Size of the BARs Setting the BAR to a smaller sizerequires more flip-flops A smaller address spacerequires more flip-flops to decode

• Latency timer Disabling the latency timer will save afew resources It must be enabled for bursting

The LogiCORE PCI32 4000 XLA Interfaces are mented allowing engineering focus at the unique back-endfunctions of a PCI design Regardless, PCI is a high-perfor-mance system that is challenging to implement in any tech-nology, ASIC or FPGA Therefore, we recommend previousexperience with building high-performance, pipelinedFPGA designs using Xilinx implementation software,TIMESPECs, and guide files The challenge to implement acomplete PCI design including back-end functions variesdepending on configuration and functionality of your appli-cation Contact your local Xilinx representative for a closerreview and estimation for your specific requirements

pre-imple-LogiCORE PCI Interface

Simple Arbiter

X7951

Tiêu đề	Xilinx PCI Data Book
Trường học	Xilinx, Inc.
Chuyên ngành	Electrical Engineering / Computer Engineering
Thể loại	Data Book
Năm xuất bản	1999

Định dạng
Số trang	258
Dung lượng	4,37 MB