Apple imac 27 a1419 d8 MLB 051 9504 rev 7 0 0

1 2 4 5 7 8 REVISION BRANCH THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

C

A

D DATE

BRANCH

7

B

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

D8 MLB

1 OF 117

2012-08-28ENGINEERING RELEASED

1 OF 143 7.0.0 051-9504

04/23/2012 3

12/19/2011 4

06/22/2012 5

06/20/2012 6

03/25/2012 7

04/02/2012 8

08/23/2011 9

03/23/2012 10

03/15/2012 11

03/15/2012 12

03/15/2012 13

03/15/2012 14

03/29/2012 15

12/20/2011 16

01/26/2012 17

N/A 18

03/15/2012 19

03/15/2012 20

N/A 21

N/A 22

03/15/2012 23

N/A 24

01/26/2012 25

N/A 26

03/23/2012 27

04/23/2012 28

03/19/2012 29

03/19/2012 30

03/19/2012 31

03/19/2012 32

03/19/2012 33

03/19/2012 34

07/02/2012 35

N/A 36

03/15/2012 37

03/15/2012 38

07/02/2012 39

07/02/2012 40

07/02/2012 41

03/23/2012 42

03/15/2012 43

01/31/2012 45

03/23/2012 46

03/23/2012 47

03/22/2012 49

07/19/2012 50

N/A 51

06/22/2012 52

06/20/2012 53

02/25/2012 54

06/07/2012 55

07/19/2012 56

04/23/2012 59

06/13/2012 61

06/13/2012 62

06/13/2012 63

06/13/2012 64

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

System Block diagram can be found on Kismet

PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram

System Block Diagram

prefsb

051-9504 7.0.0

2 OF 143

2 OF 117

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Regulator

U7600PP3V42_G3H

IW0R

Fan

TBT IO Speaker amps GPU

LCD

PPVCCSA_S0PP1V05_S0_CPU

PPVCORE_S0_CPU

PPVAXG_S0

PPFBVDDQ_S0_GPUPPVCORE_S0_GPU GPU (Core)

TBT Router TBT Router

Vin en

PP5V_S0_HDD HDD (5V)

PP5V_S4 CAM, USB Ports, VRegCtl

PH05IH05VH05

SSD

PP3V3_S0_SSDPH1R

IW1RV3V3PP3V3_S0

S0LDOS0

en VTT

VTT

LDO S3

S3Reg

PPDDRVTT_S0

DIMM (VTT) DIMM VREF Margining CA

IC0MVC0MPC0M

PPDDRVTT_S3

PP1V5_S0PPVDDQ_S3_DDR

PP1V5_S0_CPU_MEM CPU (Mem)

Audio DIMM (1V5)

Vin

PH02IH02VD2R

UB750

Regulator

Loads

IN1RVN1RPN1R

S0Reg Core IC0C

PC0C

en Reg S0 VccSA

VD2R

VD2RIC0I PC0I

PP5V_S0

en Vin

Vin

PP5V_S5PP12V_S0_BLC

PC0I+PC0S+

)

PC0MPC0G+PC0C

5.7 (GK104/GK107_BLENDED_CONSTANT)+

PG0F+PG0C1.176 *

1.176 *

High-side Component Total Power Keys

SYNC_DATE=04/23/2012SYNC_MASTER=D8_MARK

Power Block Diagram

prefsb

051-9504 7.0.0

3 OF 143

3 OF 117

TABLE_5_ITEM

TABLE_BOMGROUP_ITEMBOM OPTIONS

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM TABLE_5_ITEM

PART NUMBERALTERNATE FOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEMCRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

BOM OPTIONS BOM NAME

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

PART NUMBERALTERNATE FOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEMCRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

D8 ALTERNATES

VRAM MODULE PARTS

Bar Code Labels / EEEE #’s

IC, GPU, NV GK107-GE-PS-A2

825-7896 1 LABEL,MLB,2D EEEE_DHNM CRITICAL EEEE:DHNM

CRITICAL FB:BOTH_SAMSUNG

333S0619 4 IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF U8400,U8450,U8500,U8550333S0620 4 IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE U8400,U8450,U8500,U8550 CRITICAL FB:BOTH_HYNIX

1

341S3645 IC,ENET 1MBIT, SPI,ROM, V1.13 D8

CAMROM:BLANKCRITICAL

335S0852 IC,FLASH,SPI,1MBIT,3V3

SMC:PROGCRITICAL

335S0862 IC,SERIAL FLASH,2MBIT, 2.7V, REF F

335S0807 1 IC,64 MBIT SPI SERIAL FLASH U5110 CRITICAL BOOTROM:BLANK

825-7896

337S4355 1 IVB,SR0TA,PRQ,N1,2.9,65W,4+1,1.1,6M,LGA CPU CRITICAL CPU:4C_2P9GHZ

D8_DEVEL XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV

SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROGD8_PROGPARTS

XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V,FBA,FBBD8_COMMON1

D8_PRODUCTION VREFMRGN:N,PRODUCTION

D8_COMMON COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION

825-7896 1 LABEL,MLB,2D EEEE_F654 CRITICAL EEEE:F654

825-7896 1 LABEL,MLB,2D EEEE_F49T CRITICAL EEEE:F49T

prefsb

051-9504 7.0.0

4 OF 143

4 OF 117

D

SIN

GD

SIN

GD

SIN

GD

S

GD

SIN

IN

GD

S

D

SIN

GD

S

D

SIN

GD

SIN

GD

SIN

GD

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM 1V5_S3 LED LED GND ISOLATION SWITCH

GPU VCORE LED SLP_S3 LED

R507

DEVELOPMENT

MF-LF

2.0X1.25MM-SM GREEN-3.6MCD

64

115

402MF-LF5%

1/16W1K

R502

DEVELOPMENT

2.0X1.25MM-SM GREEN-3.6MCD

LED502

DEVELOPMENT

1/16W5%

4021K

1/16W1K5%

21

Q511SOT-363

2N7002DW-X-G

47

112

MF-LF402

1K5%

GREEN-3.6MCD 2.0X1.25MM-SM

1K402

R514

DEVELOPMENT

2.0X1.25MM-SM GREEN-3.6MCD

DEVELOPMENT

1/16W1K5%

R505

402MF-LF

DEVELOPMENT

GREEN-3.6MCD 2.0X1.25MM-SM

64

110

402MF-LF5%

R506

1K

DEVELOPMENT

GREEN-3.6MCD 2.0X1.25MM-SM

LED506

DEVELOPMENT

Q505SOT-363

2N7002DW-X-GDEVELOPMENT

64

115

4025%

1K1/16W

R503

DEVELOPMENT

LED503

2.0X1.25MM-SM GREEN-3.6MCD

DEVELOPMENT

SOT-363

Q503

2N7002DW-X-GDEVELOPMENT

64

115

1/16W5%

1K402

R510

DEVELOPMENT

2.0X1.25MM-SM GREEN-3.6MCD

2N7002DW-X-GDEVELOPMENT

1/16W5%

1K402

PM_LED_A_VIDEO_ON

VIDEO_ON_L

NO_TEST=TRUENC_Q513_1

NO_TEST=TRUENC_Q513_6

NC_Q513_2NO_TEST=TRUE

PM_PGOOD_REG_P1V05_S0

=PP3V3_S0_LEDPM_PGOOD_REG_VDDQ_S3

=PP3V3_S5_LED

PM_PGOOD_REG_CPUCORE_S0PM_PGOOD_REG_FBVDDQ_S0

PM_LED_K_PGOOD_CPUCORE_S0PM_LED_A_PGOOD_CPUCORE_S0

=PP3V3_S0_LEDLED_GNDPM_LED_K_PGOOD_REG_FBVDDQ_S0

PM_LED_A_S5

=PP3V3_S5_LED

MIN_NECK_WIDTH=0.2 MM

LED_GNDMIN_LINE_WIDTH=0.3 MM

prefsb

051-9504 7.0.0

1

2

KA

1

2

KA

KA

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712

MLB to AC-DC Supplemental Signal Connector

Enabled when system is in run

Enabled when Thunderbolt cable is plugged in

Thunderbolt Rails (S0)

G3H Rails

On with AC/DC plugged in

Enabled when system has AC and is in run or sleep

S4 Rails

J600.5:10MMEMC

25V 5%

402 NP0-C0G

1000PF

C603

J600.5:10MMEMC

402 25V 5%

10UFJ600.4:10MM

53

117

J601

504050-0791M-RT-SM

SILK_PART=PWRSIG

PLACE_NEAR=J601.3:30MM

R603

402 1/16W

0.1UF

10%

C605

SYNC_MASTER=D8_DOUGPower Connectors/Aliases

=PP1V5_S0_CPU_MEM

=PP12V_S0_FAN

=PP12V_S0_HDD_PWR

=PP12V_S0_REG_CPU_P1V05_PWRSMC_ACDC_ID

=PPVCCIO_S0_CPU

=PPVCCIO_S0_SMC

=PPVCCIO_S0_XDPPP1V05_S0_CPU_REG

PPDDRVTT_S0_LDOPP12V_S0_HDD_SNS

=PP5V_S5_PCHPP3V3_S5_REG

6 OF 143

6 OF 117

21

21

21

8

9

4

23

567

21

1

2

12

12345612

78

10119

21

21

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU HEATSINK MOUNTING FEATURES

(998-5013 PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)

998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD)

HEATPIPE MTG HOLES

WIRELESS CARD MTG HOLES

998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD)

11

11

11

11

1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH and CPU FDI

PCH Miscellaneous

CPU Reserved

PCH Reserved

SYNC_DATE=04/02/2012Unused Signal AliasesSYNC_MASTER=D8_MLB_ULTIMATE

TP_MEM_A_DQS_P<8>

TP_MEM_A_DQ_CB<7 0>

NC_DMI_MIDBUS_CLK100NX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCIE2_R2D_CNX

TP_PCIE2_R2D_CNTP_PCIE2_R2D_CP

TP_PCI_CLK33M_OUT2TP_PCI_CLK33M_OUT3

TP_PCH_PWM3TP_PCH_SST

TP_PCH_RESERVE_0

NC_DP_IG_C_AUXNXDP_IG_C_MLP<3 0>

NC_PCIE_CLK100M_PE5NX

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PE_TNX<3 0>

DP_IG_D_CTRL_DATADP_IG_D_HPD

TP_SATA_E_D2RN

TP_SATA_F_R2D_CNTP_MEM_A_DQS_N<8>

TP_PCH_PWM0TP_HDA_SDIN2

TP_CPU_FDI_FSYNC<1 0>

TP_CPU_FDI_LSYNC<1 0>

TP_CPU_FDI_INT

TP_PCH_CL_DATA1TP_PCH_CL_CLK1TP_HDA_SDIN3TP_PCH_RESERVE_8

TP_PCH_L_VDD_ENTP_PCH_L_BKLTEN

TP_PCH_RESERVE_27TP_PCH_RESERVE_25

TP_PCH_RESERVE_17TP_PCH_RESERVE_18

TP_PCH_RESERVE_15TP_PCH_RESERVE_16TP_PCH_RESERVE_14TP_PCH_RESERVE_13TP_PCH_RESERVE_12

TP_PCH_RESERVE_10TP_PCH_RESERVE_11TP_PCH_RESERVE_9

TP_PCH_RESERVE_5TP_PCH_RESERVE_6

TP_PCH_RESERVE_3TP_PCH_RESERVE_4

TP_SDVO_TVCLKINP

DP_IG_C_AUX_P

DP_IG_C_CTRL_CLK

TP_PCH_L_BKLTCTLTP_SDVO_STALLN

DP_IG_D_MLP<3 0>

TP_SDVO_TVCLKINN

DP_IG_D_AUXNDP_IG_D_AUXPDP_IG_D_MLN<3 0>

TP_SATA_F_D2RP

TP_CRT_IG_DDC_DATATP_CRT_IG_VSYNCTP_CRT_IG_BLUE

TP_CRT_IG_REDTP_CRT_IG_GREEN

TP_SATA_E_R2D_CP

TP_SATA_C_D2RNTP_SATA_C_D2RPTP_SATA_C_R2D_CN

TP_PCH_TP20TP_PCH_TP19TP_PCH_TP18TP_PCH_TP17TP_PCH_TP16TP_PCH_TP15

TP_PCH_TP13TP_PCH_TP14TP_PCH_TP12TP_PCH_TP11TP_PCH_TP10TP_PCH_TP9TP_PCH_TP8TP_PCH_TP7TP_PCH_TP6TP_PCH_TP5TP_PCH_TP4TP_PCH_TP3

TP_SATA_D_D2RP

TP_PCH_TP2TP_SATA_C_R2D_CP

TP_SATA_E_D2RP

DP_IG_C_HPD

DP_IG_D_CTRL_CLKDP_IG_C_CTRL_DATA

TP_LPC_DREQ0_LTP_PCH_INIT3V3_L

TP_PCI_AD<31 0>

TP_PCI_C_BE_L<3 0>

TP_PCI_PARTP_PCI_RESET_LTP_PCH_PCI_GNT0_L

TP_PCH_RESERVE_2TP_PCH_RESERVE_1

USB_PCH_11_P

USB_PCH_12_PUSB_PCH_12_N

USB_PCH_13_PUSB_PCH_13_N

TP_PCH_CLKOUT_DPP

TP_PCIE_CLK100M_PE7N

TP_PCIE2_D2RNTP_PCIE1_D2RP

TP_CRT_IG_DDC_CLKTP_PCIE1_R2D_CP

NC_DP_IG_D_AUXPX

NC_CPU_FDI_LSYNC<1 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_FDI_RPX<7 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_FDI_RNX<7 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CPU_FDI_TPX<7 0>

NC_PCH_L_BKLTENNC_PCH_L_VDD_EN

NC_PCH_PWM3

NO_TEST=TRUE NO_TEST=TRUE

NC_PCH_PWM2

MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_PWM1

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_D_AUXNX

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_11

NC_PCH_RESERVE_9

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_8

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_1

NO_TEST=TRUE MAKE_BASE=TRUE

NC_SDVO_STALLNX

NC_DP_IG_C_HPD

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_C_MLPX<3 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_C_MLNX<3 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RPX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RNX

NC_SATA_F_R2D_CPX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_B_CTRL_CLK

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NC_CRT_IG_RED

NO_TEST=TRUE MAKE_BASE=TRUE

NC_CRT_IG_GREEN

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXPX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_B_HPD

NO_TEST=TRUE MAKE_BASE=TRUE

NC_DP_IG_B_AUXPX

NC_PCI_AD<31 0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_LPC_DREQ0_L

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_16

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_15

NO_TEST=TRUE MAKE_BASE=TRUE

NC_SATA_E_D2RPX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_SATA_F_R2D_CNX

NO_TEST=TRUE

NC_PCH_RESERVE_19

MAKE_BASE=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_20

NO_TEST=TRUE NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_23

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_26

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_RESERVE_28

NC_PCH_TP20

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5PX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PE_RPX<3 0>

NC_USB_PCH_4NX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_USB_PCH_4PX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_USB_PCH_5PX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_USB_PCH_5NX

NC_USB_PCH_6NX

NO_TEST=TRUE MAKE_BASE=TRUE

NC_USB_PCH_6PX

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPNX

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

NO_TEST=TRUE MAKE_BASE=TRUE

TP_PCH_CLKOUT_DPN

USB_PCH_4_N

USB_PCH_5_NUSB_PCH_5_P

TP_PCH_GPIO66_CLKOUTFLEX2TP_PCH_GPIO65_CLKOUTFLEX1

NO_TEST=TRUE MAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCIE_CLK100M_PE4PTP_PCIE_CLK100M_PE4NTP_PCIE_CLK100M_PE0P

prefsb

051-9504 7.0.0

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

9 OF 143

9 OF 117

INININ

IN

ININININ

ININININININ

INININININ

OUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUT

IN

ININININININININININININININININ

PEG_RX_4*

PEG_RX_4

PEG_RX_3*

PEG_RX_3PEG_RX_2

DMI_TX_3*

DMI_TX_3

DMI_TX_2*

DMI_TX_2DMI_TX_1

FDI_COMPIOFDI_ICOMPOFDI_INT

PEG_COMPIPEG_ICOMPO

PEG_RX_1PEG_RX_14*

PEG_RX_12*

PEG_RX_6*

PEG_RX_13PEG_RX_14

RSVD_NCTF_AV1RSVD_NCTF_AW2RSVD_NCTF_AY3

RSVD_NCTF_B39

NCTF_AW38NCTF_AU40NCTF_D1NCTF_C2NCTF_A38CFG_8

RSVD_J34RSVD_J33RSVD_J31

CFG_0CFG_1CFG_2CFG_3CFG_4CFG_5CFG_6CFG_7

CFG_9CFG_10CFG_11CFG_12CFG_13CFG_14CFG_15CFG_16CFG_17

RSVD_K9RSVD_K31RSVD_K34RSVD_L9RSVD_L31RSVD_L33RSVD_L34RSVD_M34RSVD_N33RSVD_N34

RSVD_P35RSVD_P37RSVD_P39RSVD_R34RSVD_R36RSVD_R38RSVD_R40RSVD_AB6RSVD_AB7RSVD_AD34RSVD_AD35RSVD_AD37RSVD_AE6RSVD_AF4RSVD_AG4RSVD_AJ11RSVD_AJ29RSVD_AJ30RSVD_AJ31RSVD_AN20RSVD_AP20RSVD_AT11RSVD_AT14RSVD_AU10RSVD_AV34RSVD_AW34RSVD_AY10

RSVD_J9RSVD_H8RSVD_H7

RSVD_C38

RSVD_D38RSVD_C39

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CFG [6:5] PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = 1 X8, 2 X4 CFG [3] PCIE STATIC X4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [1:0] RESERVED CONFIGURATION LANE

( IVY BRIDGE EDS #473717 TABLE 6-5 )

CFG [17:7] RESERVED CONFIGURATION LANE CFG [4] RESERVED CONFIGURATION LANE

INTEL SUGGESTS TO KEEP THESE TPS

ThermDA ThermDC

ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE.

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1

CFG [2] PCIE STATIC X16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

24.91%

PLACE_NEAR=U1000.B4:12.7MMR1010

NC_SNS_CPU_THERMDNNO_TEST=TRUE

B7

B8

E9

E10C10

AE5AC5

AA8

AA7

Y7

Y6W7

AE2AE1AG3

B4B5

D12M4K4A6

L1M3

C4

H4G1F3E1

C9B12

C5

C3

W5V4

AV1AW2AY3B39

AW38AU40D1C2A38J38

J34J33J31

H36J36J37K36L36N35L37M36

L35M38N36N38N39N37N40G37G36

K9K31K34L9L31L33L34M34N33N34

P35P37P39R34R36R38R40AB6AB7AD34AD35AD37AE6AF4AG4AJ11AJ29AJ30AJ31AN20AP20AT11AT14AU10AV34AW34AY10

J9H8H7

C38

D38C39

IN

IN

OUTOUTOUT

ININOUT

OUTBIBI

SA_DIMM_VREFDQSB_DIMM_VREFDQSM_VREFSM_DRAMRST*

SM_DRAMPWROKPM_SYNC

PREQ*

TMSTRST*

TDITDO

BCLK_ITP

BCLK_0BCLK_ITP*

ININ

INOUTIN

ININ

ININ

OUT

OUT

BIBIBI

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BASED ON INTEL MOBILE SOLUTION

402MF-LF

MF-LF

U1000

BGA-SKT-K70

OMIT_TABLE IVY-BRIDGE

R1141

1/16W1%

1K

402MF-LF

R1140

1/16W1%

402MF-LF

1K

10%

X7R-CERM16V

200

R1121

130

MF-LF4021%

PLT_RESET_LS1V05_L PM_SYNC

CPU_PWRGD

CPU_THRMTRIP_L

CPU_PECI CPU_CATERR_L CPU_PROC_SEL CPU_SKTOCC_L

K40

L38J39

L40L39

E39

H40H38G38G40G39F38E40F40

M40K38

C40

W2D40

W1

J40

AJ33

F36G35

E37

J35

H34K32

12

12

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

OUT

OUTOUT

OUTOUT

BIBI

BIBI

BIBI

BIBI

BIBI

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUTOUT

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUT

OUTOUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUTOUT

BIBIBIBIBI

BIBI

BI

BI

BIBI

BI

BIBI

BIBI

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUT

OUTOUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUTOUT

SA_DQ_32SA_DQ_33

SA_DQS_8*

SA_BS_2SA_CAS*

SA_BS_1SA_BS_0SA_DQ_63SA_DQ_62SA_DQ_61SA_DQ_60

SA_DQ_9

SA_CK_1

SA_ODT_2SA_ODT_1SA_ODT_0

SA_RAS*

SA_WE*

SA_CK_0SA_CK_0*

SA_CK_1*

SA_CK_2SA_CK_2*

SA_CK_3SA_CK_3*

SA_CKE_0

SA_CKE_1

SA_CKE_2

SA_CKE_3SA_CS_0*

SA_CS_1*

SA_CS_2*

SA_CS_3*

SA_DQ_0SA_DQ_1

SA_DQ_10SA_DQ_11SA_DQ_12SA_DQ_13SA_DQ_14SA_DQ_15SA_DQ_16SA_DQ_17SA_DQ_18SA_DQ_19SA_DQ_2

SA_DQ_20SA_DQ_21SA_DQ_22SA_DQ_23SA_DQ_24SA_DQ_25SA_DQ_26SA_DQ_27SA_DQ_28SA_DQ_29SA_DQ_3

SA_DQ_30SA_DQ_31

SA_DQ_34SA_DQ_35SA_DQ_36SA_DQ_37SA_DQ_38SA_DQ_39SA_DQ_4

SA_DQ_40SA_DQ_41SA_DQ_42SA_DQ_43SA_DQ_44SA_DQ_45SA_DQ_46SA_DQ_47SA_DQ_48SA_DQ_49SA_DQ_5

SA_DQ_50SA_DQ_51SA_DQ_52SA_DQ_53SA_DQ_54SA_DQ_55SA_DQ_56SA_DQ_57SA_DQ_58SA_DQ_59

SA_DQ_6SA_DQ_7SA_DQ_8

SA_DQS_0SA_DQS_0*

SA_DQS_1SA_DQS_1*

SA_DQS_2SA_DQS_2*

SA_DQS_3SA_DQS_3*

SA_DQS_4SA_DQS_4*

SA_DQS_5SA_DQS_5*

SA_DQS_6SA_DQS_6*

SA_DQS_7SA_DQS_7*

SA_DQS_8

SA_ECC_CB_0SA_ECC_CB_1SA_ECC_CB_2SA_ECC_CB_3SA_ECC_CB_4SA_ECC_CB_5SA_ECC_CB_6SA_ECC_CB_7

SA_MA_0SA_MA_1

SA_MA_10SA_MA_11SA_MA_12SA_MA_13SA_MA_14SA_MA_15

SA_MA_2SA_MA_3SA_MA_4SA_MA_5SA_MA_6SA_MA_7SA_MA_8SA_MA_9

SB_CKE_3SB_CS_0*

SB_CK_0SB_CK_0*

SB_CK_1

SB_CK_2SB_CK_2*

SB_CK_3SB_CK_3*

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_DQ_0SB_DQ_1

SB_DQ_10SB_DQ_11SB_DQ_12SB_DQ_13SB_DQ_14SB_DQ_15SB_DQ_16SB_DQ_17SB_DQ_18SB_DQ_19SB_DQ_2

SB_DQ_20SB_DQ_21SB_DQ_22SB_DQ_23SB_DQ_24SB_DQ_25SB_DQ_26SB_DQ_27SB_DQ_28SB_DQ_29SB_DQ_3

SB_DQ_30SB_DQ_31SB_DQ_32

SB_DQ_34SB_DQ_35SB_DQ_36SB_DQ_37SB_DQ_38SB_DQ_39SB_DQ_4

SB_DQ_40SB_DQ_41SB_DQ_42SB_DQ_43SB_DQ_44SB_DQ_45SB_DQ_46SB_DQ_47SB_DQ_48SB_DQ_49SB_DQ_5

SB_DQ_50SB_DQ_51SB_DQ_52SB_DQ_53SB_DQ_54SB_DQ_55SB_DQ_56SB_DQ_57SB_DQ_58SB_DQ_59SB_DQ_6

SB_DQ_60SB_DQ_61SB_DQ_62SB_DQ_63

SB_DQ_7SB_DQ_8SB_DQ_9

SB_DQS_0SB_DQS_0*

SB_DQS_1

SB_DQS_1*

SB_DQS_2*

SB_DQS_3SB_DQS_4*

SB_DQS_5SB_DQS_5*

SB_DQS_6SB_DQS_6*

SB_DQS_7SB_DQS_7*

SB_DQS_8

SB_ECC_CB_0SB_ECC_CB_1SB_ECC_CB_2SB_ECC_CB_3SB_ECC_CB_4SB_ECC_CB_5SB_ECC_CB_6SB_ECC_CB_7

SB_MA_0SB_MA_1

SB_MA_10SB_MA_11SB_MA_12SB_MA_13SB_MA_14SB_MA_15

SB_MA_2SB_MA_3SB_MA_4SB_MA_5SB_MA_6SB_MA_7SB_MA_8SB_MA_9

SB_ODT_0SB_ODT_1SB_ODT_2SB_ODT_3

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

12 OF 143

12 OF 117

AU35AW37

AV12

AV20AV30AW28AY29AE40AE39AG38AG39

AN4

AU24

AU30AU32AV31

AU28AW29

AY25AW25

AU25

AW27AY27

AV26AW26

AV19

AT19

AU18

AV18AU29AV32AW30AU33

AJ3AJ4

AR3AR4AN2AN3AR2AR1AV2AW3AV5AW5AL3

AU2AU3AU5AY5AY7AU7AV9AU9AV7AW7AL4

AW9AY9

AU39AU36AW35AY36AU38AU37AJ2

AR40AR37AN38AN37AR39AR38AN39AN40AL40AL37AJ1

AJ38AJ37AL39AL38AJ39AJ40AG40AG37AE38AE37

AL2AL1AN1

AK3AK2

AP3AP2

AW4AV4

AV8AW8

AV37AV36

AP38AP39

AK38AK39

AF38AF39

AV13

AU12AU14AW13AY13AU13AU11AY12AW12

AV27AY24

AV28AU21AT21AW32AU20AT20

AW24AW23AV23AT24AT23AU22AV22AT22

AV15AN25AN26AL25AT26

AK25AP24AR25

AP23AM24AW17

AL21AL22

AL20

AL23AM22

AP21AN21

AU16

AY15

AW15

AG7AG8

AM10AL10AL6AM6AL9AM9AP7AR7AP10AR10AJ9

AP6AR6AP9AR9AM12AM13AR13AP13AL12AL13AJ8

AR12AP12AR28

AL28AL29AP28AP29AM28AM29AG5

AP32AP31AP35AP34AR32AR31AR35AR34AM32AM31AG6

AL35AL32AM34AL31AM35AL34AH35AH34AE34AE35AJ6

AJ35AJ34AF33AF35

AJ7AL7AM7

AH7AH6

AM8

AL8AP8

AN13AN28

AP33AR33

AL33AM33

AG35AG34

AN16

AL16AM16AP16AR16AL15AM15AR15AP15

AK24AM20

AN23AU17AT18AR26AY16AV16

AM19AK18AP19AP18AM18AL18AN18AY17

AL26AP26AM26AK26

VCCIO_44

VCCIO_SELVCCIO_45VCCIO_30

VSSAXG_SENSEVCCAXG_SENSEVSSIO_SENSEVCCIO_SENSE

VCC_024

VCC_038

VCCIO_42

VCCIO_29VCCIO_28

VCCIO_09

VCC_001VCC_002VCC_003VCC_004

VCCIO_27

VCC_012

VCC_015

VCC_005VCC_006VCC_007VCC_008VCC_009VCC_010VCC_011

VCC_013VCC_014

VCC_016VCC_017VCC_018

VCC_020VCC_021VCC_022VCC_023

VCC_025VCC_026VCC_027VCC_028VCC_029VCC_030VCC_031VCC_032VCC_033VCC_034VCC_035VCC_036VCC_037

VCC_039VCC_040VCC_041VCC_042VCC_043VCC_044VCC_045VCC_046VCC_047VCC_048VCC_049VCC_050VCC_051VCC_052

VCC_057VCC_058VCC_059VCC_060VCC_061VCC_062VCC_063VCC_064VCC_065VCC_066VCC_067VCC_068VCC_069VCC_070

VCCIO_02VCCIO_01

VCCIO_20

VCCIO_26

VCCIO_33VCCIO_34VCCIO_35VCCIO_36

VCCIO_40

VCCIO_43

VCCIO_04VCCIO_05VCCIO_06VCCIO_07VCCIO_08

VCCIO_10VCCIO_11VCCIO_12VCCIO_13VCCIO_14

VCCIO_03

VCC_019

VCCIO_15

VCCIO_17VCCIO_18

VCCIO_22VCCIO_21VCCIO_23VCCIO_24VCCIO_25

VCCIO_32

VCCIO_37VCCIO_38VCCIO_39

VCCSA_VIDSYM 6 OF 10

VCCAXG_02VCCAXG_03

VDDQ10

VCCPLL1VCCPLL0

VDDQ22VDDQ21VDDQ20VDDQ19VDDQ16VDDQ14VDDQ13VDDQ12VDDQ11VDDQ9VDDQ8VDDQ7VDDQ6VDDQ4VDDQ3VDDQ2VDDQ1VDDQ0VCCAXG_16

VCCAXG_15VCCAXG_14VCCAXG_13VCCAXG_12VCCAXG_11VCCAXG_10VCCAXG_09VCCAXG_07VCCAXG_06VCCAXG_05VCCAXG_04

VCCAXG_42VCCAXG_41VCCAXG_40VCCAXG_39VCCAXG_38VCCAXG_37VCCAXG_36VCCAXG_35VCCAXG_34VCCAXG_33VCCAXG_32VCCAXG_31VCCAXG_30VCCAXG_29VCCAXG_28VCCAXG_27VCCAXG_26VCCAXG_25VCCAXG_24VCCAXG_22VCCAXG_21VCCAXG_19VCCAXG_18VCCAXG_17

VCCAXG_23VCCAXG_20

VDDQ15

VDDQ17VDDQ18VDDQ5

VCCAXG_01

VCCAXG_08SYM 7 OF 10

VCC_097

VCC_091VCC_090VCC_089VCC_088VCC_087VCC_083

VCC_112

VCC_117

VCC_113VCC_114VCC_115VCC_116

VCC_118VCC_119VCC_120VCC_121VCC_122VCC_123VCC_124VCC_125

VCC_128VCC_129VCC_130

VCC_131VCC_132VCC_133VCC_134VCC_135VCC_136VCC_137VCC_138VCC_139VCC_140VCC_141VCC_142VCC_143VCC_144VCC_145VCC_146VCC_147VCC_148VCC_149VCC_150VCC_151VCC_152VCC_153

VCC_156VCC_157VCC_158VCC_159VCC_160

VCCSA0VCCSA1VCCSA2VCCSA3VCCSA4VCCSA5VCCSA6

VCCSA8VCCSA9

VSS_NCTF1

VCC_073VCC_072VCC_071

VCC_155VCC_154

VCC_084

VCC_093

VSS_NCTF0

VCC_100VCC_101

VCC_104

VCC_106VCC_105

VCC_096VCC_095VCC_094

VCC_086VCC_085

VCCSA7

VCCSA10VCC_107

VCC_111

VCC_098VCC_099

VCC_075

VCC_081

VCC_103VCC_102

VCC_078VCC_079VCC_080

VCC_108VCC_109VCC_110

OUTOUT

OUTOUT

OUTIN

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

05%

PLACE_NEAR=U1000.A37:10mm

MF-LF

R1300

1/16W1%

75402

PLACE_NEAR=U1000.B37:10mm

402

R1302

1101%

CPU POWER

CPU_VIDSOUTCPU_VIDALERT_R_L

=PPVCCIO_S0_CPU

CPU_VIDSCLK_R

CPU_VIDALERT_L

SNS_CPU_VCORE_NSNS_CPU_VCCSA

NO_TEST=TRUENC_CPU_VCCIO_VIDNC_CPU_VCCSA_VIDNO_TEST=TRUE

prefsb

051-9504 7.0.0

M32L32AB3AB4

C18

D14

U4

J7J4

AJ26

A12A13A14A15

J3

B16

B25

A16A18A24A25A27A28B15

B18B24

B27B28B30

B33B34C15C16

C19C21C22C24C25C27C28C30C31C33C34C36D13

D15D16D18D19D21D22D24D25D27D28D30D31D33D34

E18E19E21E22E24E25E27E28E30E31E33E34E35F15

A7A11

B9

G4

L7M13N3N4

R7

U7

AB8AF8AG33AJ16AJ17

AJ28AJ32AK15AK17AK19

AA3

B31

AK21

AK27AK29

D6D10E3E4G3

L4

N7R3R4

P34

Y38Y37

AB34AB35

AU19

AK12AK11

AY28AY26AY23AW31AV25AV21AU31AU27AU23AR24AR23AR22AR21AJ24AJ23AJ20AJ14AJ13AC40

AC39AC38AC37AC36AC35AC34AC33AB39AB38AB37AB36

Y36Y35Y34Y33W38W37W36W35W34W33U40U39U38U37U36U35U34U33T40T38T37T35T34T33

T39T36

AV24

AV29AV33AR20

AB33

AB40

G25

AV39AY37

G32

G24G22G21G19G18F33

H31

J18

H32J12J15J16

J19J21J22J24J25J27J28J30

K18K19K21

K22K24K25K27K28K30L13L14L15L16L18L19L21L22L24L25L27L28L30M14M15M16M18

M22M24M25M27M28

H10H11H12J10K10K11L11

M10M11

B3

F19F18F16

M21M19

F34

G27

A4

H14H15

H19

H22H21

G31G30G28

G16G15

L12

M12H24

H30

G33H13

F22

F31

H18H16

F27F28F30

H25H27H28

VSS_090VSS_089VSS_088VSS_087VSS_086VSS_085VSS_084VSS_083VSS_082VSS_081VSS_080VSS_079VSS_078VSS_077VSS_076VSS_075VSS_074VSS_073VSS_072VSS_071VSS_070VSS_069VSS_068VSS_067VSS_066VSS_065VSS_064VSS_063VSS_062VSS_061VSS_060VSS_059VSS_058VSS_057VSS_056VSS_055VSS_054VSS_053VSS_052VSS_051VSS_050VSS_049VSS_048VSS_047VSS_046VSS_045VSS_044VSS_043VSS_042VSS_041VSS_040VSS_039VSS_038VSS_037VSS_036VSS_035VSS_034VSS_033VSS_032VSS_031VSS_030VSS_029VSS_028VSS_027VSS_026VSS_025VSS_024VSS_023

VSS_020VSS_019

VSS_001VSS_002VSS_003VSS_004VSS_005

VSS_012

VSS_006VSS_007VSS_008VSS_009VSS_010VSS_011

VSS_013VSS_014VSS_015

VSS_021VSS_022

VSS_016VSS_017VSS_018

SYM 8 OF 10

VSS_360VSS_359VSS_358VSS_357VSS_356VSS_355VSS_354VSS_353VSS_352VSS_351VSS_350VSS_349VSS_348VSS_347VSS_346VSS_345VSS_344VSS_343VSS_342VSS_341VSS_340VSS_339VSS_338VSS_337VSS_336VSS_335VSS_334VSS_333VSS_332VSS_331VSS_330VSS_329VSS_328VSS_327VSS_326VSS_325VSS_324VSS_323VSS_322VSS_321VSS_320VSS_319VSS_318VSS_317VSS_316VSS_315VSS_314VSS_313VSS_312VSS_311VSS_310VSS_309VSS_308VSS_307VSS_306VSS_305VSS_304VSS_303VSS_302VSS_301VSS_300VSS_299VSS_298VSS_297VSS_296VSS_295VSS_294VSS_293VSS_292VSS_291VSS_290VSS_289VSS_288VSS_287VSS_286VSS_285VSS_284VSS_283VSS_282VSS_281VSS_280VSS_279VSS_278VSS_277VSS_276VSS_275VSS_274VSS_273VSS_272VSS_271

VSS_270VSS_269VSS_268VSS_267VSS_266VSS_265VSS_264VSS_263VSS_262VSS_261VSS_260VSS_259VSS_258VSS_257VSS_256VSS_255VSS_254VSS_253VSS_252VSS_251VSS_250VSS_249VSS_248VSS_247VSS_246VSS_245VSS_244VSS_243VSS_242VSS_241VSS_240VSS_239VSS_238VSS_237VSS_236VSS_235VSS_234VSS_233VSS_232VSS_231VSS_230VSS_229VSS_228VSS_227VSS_226VSS_225VSS_224VSS_223VSS_222VSS_221VSS_220VSS_219VSS_218VSS_217VSS_216VSS_215VSS_214VSS_213VSS_212VSS_211VSS_210VSS_209VSS_208VSS_207VSS_206VSS_205VSS_204VSS_203VSS_202VSS_201

VSS_196VSS_195VSS_194

VSS_200VSS_199VSS_198VSS_197

VSS_188

VSS_193VSS_192VSS_191VSS_190VSS_189

VSS_182

VSS_187VSS_186

VSS_181

VSS_185VSS_184VSS_183SYM 9 OF 10

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU GROUNDS

prefsb

051-9504 7.0.0

14 OF 143

14 OF 117

AV10AU8AU6AU4AU34AU26AU15AU1AT9AT8AT7AT6AT5AT40AT4AT39AT38AT37AT36AT35AT34AT33AT32AT31AT30AT3AT29AT28AT27AT25AT2AT17AT16AT15AT13AT12AT10AT1AR5AR36AR30AR27AR19AR18AR17AR14AR11AP5AP40AP4AP37AP36AP30AP27AP25AP22AP17AP14AP11AP1AN9AN8AN7AN6AN5AN36AN35AN34AN33AN32AN31AN30AN27AN24AN22AN19AN17AN14AN11AN10AM5AM40AM4AM39AM38AM37AM36AM30AM3AM27

AM25AM23AM21AM2AM17AM14AM11AM1AL5AL36AL30AL27AL24AL19AL17AL14AL11AK9AK8AK7AK6AK5AK40AK4AK37AK36AK35AK34AK33AK32AK31AK28AK22AK16AK14AK13AK10AK1AJ5AJ36AJ27AJ25AJ21AJ18AJ15AJ12AH8AH5AH40AH39AH38AH37AH36AH33AH3AH2AG36AF7AF6AF5AF40AF37AF36AF34AF1AE36AE33AE3

AD40AD39

A17A23A26A29A35

AA6

AA33AA34AA35AA36AA37AA38

AB5AC1AC6

AD5AD8

AD33AD36AD38

Y8Y5W6V5V40V39V38V37V36V35V34V33V2V1U8T6T5T1R8R39R37R35R33P6P5P40P38P36P2P1N8M9M6M5M39M37M35M33M29M26M23M20M2M17M1L8L29L26L23L20L17L10K6K5K39K37K35K33K29K26K23K20K2K17K14K13K12K1J32J29J26J23J20J17J11H9H6H5H39H37H35H33H29H26H23H20H2H17H1G8

G7G34G29G26G23G20G17G12G11F9F6F5F39F37F35F29F26F23F20F2F17F14F13F10F1E8E7E36E32E29E26E23E20E17E12E11D9D5D4D39D37D32D29D26D23D20D2D17C8C7C35C32C29C26C23C20C17C12C11B6B38B35B32B29B26B23B17B14B13B10

AY18AY14AY11

AY8AY6AY4AY35

AW10

AW6AW36AW16AW14AW11

AV14

AV6AV38

AV11

AV35AV3AV17

SG

OUTIN

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DP_AUXIO_EN GLITCHES ON S0/S3 TRANSITIONS RDAR://11085566

D8: ISOLATION FET TO PREVENT TBT 3V3_TBTLC LEAKAGE RDAR://10885566

D7/D7I: CHECK CACTUSRIDGE POWER SEQUENCING & LEAKAGE RDAR://10739300

AP CLKREQ# ISOLATION

ISOLATION FET TO PREVENT LEAKAGE ON AP_PWR_EN AND AP_CLKREQ_L RDAR://11068662

UNUSED clock terminations for FCIM MODE

DP_AUXCH_ISOL IS ACTIVE LOW!

Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP

DP_AUXIO_EN Inversion

TBT CLKREQ# ISOLATION

CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16

11 = 1x16 (default) 1 = DIR 1 = DIR

R1501

10K

402MF-LF5% 1/16WR1502

10K

MF-LF5%

R1504

R1509402

10K

1/16WR1510

10K

MF-LF 4025% 1/16W

10K

MF-LFR15111/16W

402R15281/16W MF-LF5%

10K

402MF-LF1K

5%

NOSTUFF

R15121/16W

PLACE_NEAR=U1000.L37:20MM

PLACE_NEAR=U1000.K36:20MM

4021K

NOSTUFF R15231/16W

PLACE_NEAR=U1000.J37:20MM

1/16W5%

1K

402MF-LFR1522

5%

10K

1/16WR1531402MF-LF

10K

5% 1/16WR1534MF-LF 402

10K

5% 1/16WR1533402MF-LF

5%

1/16W MF-LF 402

4021/16W5%

10K

MF-LFR1505

4025%

R15561/16W

402

402MF-LF5% 1/16W

10K

MF-LF5%

R1516

R1537MF-LF 4025%

1K1/16W

R15361/16W1K

1K5% 1/16W MF-LF 402R1514

1/16W

4021/16WR1538

10K

MF-LF5%

5%

R15351/16WMF-LF402

100K

10K

5% 1/16WR1563402MF-LF

20K

5% 1/16W MF-LFR1532402

10K

5% 1/16WMF-LF402R1551

10K

5% 1/16WR1548MF-LF 402

PLACE_NEAR=U1800.P33:5mm

5% 1/16W MF-LF 402R1549

10K

10K

1/16WR1550

5%

10K

1/16WR1547MF-LF 402

PLACE_NEAR=U1800.R33:5mm

10K

402R1546MF-LF1/16W5%

PLACE_NEAR=U1800.AF55:6MM

1/16W5%

PLACE_NEAR=U1800.BF38:5mm

4.7K

MF-LFR1564

1/16W5%

40210K R1590

CRITICAL

Q1509VESM

SSM3K15AMFVAPE

10K

R15914021/16W

MF-LF5%

1/16W402

10K

10K

MF-LFR15271/16W

Q1530

SOD-VESM-HFSSM3K15FV

SOT563

CRITICALSSM6N15AFEQ1540

1/16W

402

R1598

MF-LF 1/16W 5%

R1593

U1500SOT35374LVC1G08GW

21 99

5%

10KMF-LFR1521

4021/16W

1/16W5%

402

R1583 10K

MF-LF 5% 1/16W

0R1585

NOSTUFF

402

1/16W5%

MF-LF402

10K

Q1550

SSM3K15FVSOD-VESM-HF

15

112

R1588

MF-LF5%

1/16W402

10K

Q1560

SOD-VESM-HFSSM3K15FV

15

99

SOT353U150174LVC1G08GW

86 88 112

U1500.5:3MMC1500

16V0402

0.1UF

X7R-CERM10%

U1501.5:3MM0.1UF

040216VX7R-CERM

C1501

10%

R15241% 1/16WMF-LF402

NOSTUFF R15540

=PP3V3_S4_AP

JTAG_TBT_TCK_ISOLJTAG_TBT_TCK

SSD_CLKREQ_LENET_CLKREQ_LTBT_PCH_CLKREQ_L

=PP3V3_S0_PCH_STRAPSPCH_GPIO48

AP_PWR_ENAP_CLKREQ_L

12

21

21

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY ITPLL (CPU VCCSFR) DECOUPLING

Memory (CPU VCCDDR) DECOUPLING

PLACEMENT_NOTE (C1660-C1665):

PLACEMENT_NOTE (C1650-C1657):

CPU VCCIO DECOUPLING 8X 22UF 0805, 6X 10UF 0805

10x 10UF and 10x 1UF CAPACITORS

BULK CAPS ON VTT REG PAGE 77

INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders

PLACEMENT_NOTE (C1600-C1613):

Bulk decoupling is on VCCSA reg page 75

2x 10uF 0603 INTEL RECOMMENDATION 2X 10uF 0805 CPU VCCSA DECOUPLING

BULK CAPS ON CPU VREG PAGE 74BULK CAPS ON CPU VREG PAGE 72

2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402 INTEL RECOMMENDATION 1x 10uF 0805

CPU VCORE DECOUPLING 14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)

REPLACED WITH 603 PER RDAR://10700439

10V402

1UF

C1693

6.3V10%

402

2.2UF

603X5R-CERM6.3V10%

4.7UF

10V603

10UF

Place inside socket cavity

C1629

10V603

10UF

Place inside socket cavity

C1628

10V603

10UF

Place inside socket cavity

C1627

10V603

10UF

Place inside socket cavity

C1626

10V603

10UF

Place inside socket cavity

C1624

10V603

10UF

Place inside socket cavity

C1623

10V603

10UF

Place inside socket cavity

C1622

10V603

Place inside socket cavity

10UF

C1621

10V603

10UF

Place inside socket cavity

C1620

16V402

1UF

Place inside socket cavity

C1630

10V603

1UF

16V402

1UF

Place inside socket cavity

C1634

16V402

1UF

Place inside socket cavity

C1635

16V402

1UF

Place inside socket cavity

C1636

16V402

1UF

Place inside socket cavity

C1637

16V402

1UF

Place inside socket cavity

C1638

16V402

6.3VX5R

10UF

20%

C1695

0201X5R20%

1UF

6.3V

C1682

02016.3V20%

X5R

1UF

C1683

6.3V20%

0201X5R

1UF

C1684

6.3V20%

0201X5R

1UF

C1685

1UF

6.3V20%

0201X5R

C1687

6.3V603

10uF

X5R20%

C1667 C1666

X5R6.3V20%

10uF

0603

22UF20%

6.3VX5R-CERM2

22UF060320%

6.3VX5R-CERM2 X5R-CERM2

0603

C1602

22UF20%

6.3V

0603

22UF20%

6.3VX5R-CERM2

C1603

0603

22UF20%

6.3VX5R-CERM2

0603X5R-CERM26.3V20%

22UF

0603

C1606

22UF20%

6.3VX5R-CERM2

C1607

0603

22UF20%

6.3VX5R-CERM2

C1608

0603

22UF20%

6.3VX5R-CERM2

C1609

0603

22UF20%

6.3VX5R-CERM2

X5R-CERM26.3V20%

22UF0603

X5R-CERM26.3V20%

22UF0603

C1612

6.3VX5R-CERM220%

0603

22UF

X5R-CERM26.3V20%

22UF0603

C1613

22UF20%

6.3VX5R-CERM2

C1650

C1651

X5R-CERM26.3V20%

22UF

6.3V0603

C1652

X5R-CERM220%

0603

22UF20%

6.3VX5R-CERM2 X5R-CERM2

0603

C1654

6.3V20%

22UF

0603

C1655

X5R-CERM26.3V20%

22UF

0603

C1656

X5R-CERM26.3V20%

22UF

0603

C1657

X5R-CERM26.3V20%

22UF

X5R-CERM26.3V20%

22UF0603

22UF060320%

6.3VX5R-CERM2 X5R-CERM2

C1678

0603

22UF20%

6.3V

C1679

0603

22UF20%

6.3VX5R-CERM2

C1680

22UF20%

6.3VX5R-CERM2

6.3V20%

22UF0603

X5R-CERM2 X5R6.3V

20%

080547UF

C1696

X5R20%

6.3V080547UF

C1697

Place at edge of socket

10uF

X5R20%

20%

C1661

X5R6.3V20%

603

10V402

1UF

C1694

SYNC_MASTER=D7_MLBCPU NON-GFX DECOUPLING

16 OF 143

16 OF 117

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

1

2

21

21

21

21

21

21

1

2

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE (C1704-C1709):

AXG BULK CAPS

INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF VAXG DECOUPLING

R1730

0

MF-LF4025%

1/16W

R1740

1/16W5%

402MF-LF

6.3V

C1711

4.7UF

X5R-CERMPlace inside socket cavity

60310%

603

C1795X5R20%

10UF

10V603

C179410V

10UF

20%

X5RCASE-D2-SM

CRITICAL

C1793POLY20%

2V

330UF-0.006OHM

CASE-D2-SM2V

2VPOLY

330UF-0.006OHMCRITICALCRITICAL

2VC1790CASE-D2-SMPOLY20%

330UF-0.006OHM

CASE-D2-SM

330UF-0.006OHM

C1789POLY20%

22UF

0603

C1705

X5R-CERM26.3V20%

22UF

0603

C1706

X5R-CERM26.3V20%

22UF

0603

C1707

X5R-CERM26.3V20%

22UF

0603

C1708

X5R-CERM26.3V20%

22UF

0603

C1709

X5R-CERM26.3V20%

22UF

1UF

6.3V 402 10%

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2MMMAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3V

prefsb

051-9504 7.0.0

21

21

21

2

11

21

21

21

21

21

2

21

21

21

21

21

21

2 1

2 1

OUTOUT

OUTOUT

ININ

ININ

ININ

OUTBI

BI

OUT

SATA3COMPISATA3RCOMP0SATA3RBIAS

SATA3RXP

HDA_SYNCINTRUDER* LDRQ1*/GPIO23

FWH1/LAD1FWH2/LAD2FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA2TXNSATA2TXP

SATA3TXNSATA3TXP

SATA4RXNSATA4RXPSATA4TXNSATA4TXP

SATA5RXN

SATA5TXNSATA5TXP

SATAICOMPOSATAICOMPI

SATALED*

SATA0GP/GPIO21SATA1GP/GPIO19

HDA_SDO

GPIO33GPIO13

SATA0TXPSATA0TXN

SATA2RXNSATA2RXP

SATA5RXP

SATA0RXPLDRQ0*

L_BKLTENL_VDD_EN

FWH0/LAD0

INTVRMEN

SPI_CS1*

HDA_SDIN0SRTCRST*

CLKOUT_PEG_B_N

CLKIN_DOT_96P

CL_DATA1CL_CLK1CLKIN_GND1_PCLKIN_GND1_NCLKIN_GND0_PCLKOUT_ITPXDP_NCLKOUTFLEX3/GPIO67CLKOUTFLEX2/GPIO66CLKOUTFLEX1/GPIO65CLKOUTFLEX0/GPIO64XCLK_RCOMPXTAL25_OUTXTAL25_INCLKIN_PCILOOPBACKREFCLK14INCLKIN_SATA_PCLKIN_DOT_96N

CLKOUT_DP_NCLKOUT_DP_P

CLKOUT_DMI_PCLKOUT_DMI_NCLKOUT_PEG_A_P

SMBCLKSMBALERT*/GPIO11

SML1DATA/GPIO75SML1CLK/GPIO58SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLKSMBDATA

PERN3PETP2

CLKOUT_PCIE2PCLKOUT_PCIE2N

CLKOUT_PCIE1NCLKOUT_PCIE1P

CLKOUT_PCIE0NCLKOUT_PCIE0PPETP8

PERP8PETN8

PETP7

PERN8PETN7PERP7PERN7

PETN6PETP6

PERP5

PETP4

PERN5PETN4PERP4

PETP3

PERN4PETN3PERP2

CLKIN_SATA_N

CLKIN_GND0_NCLKOUT_ITPXDP_PCLKOUT_PEG_B_P

PETN5PETP5

PERN6PERP6

PERP1PERN1

PETN1PETP1

OUTOUT

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DOES THIS NEED LENGTH MATCH???

TIE THEM TOGETHER VERY CLOSE TO PINS PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)

402 1/16W

R1820

MF-LF 402

402

R183149.9

1%

1/16W 402 MF-LF

47 49 101

MF-LF 402

1/16W 5%

402 402 5%

MF-LF

20KR1802

1/16W

C18031UF

X5R 10%

C18021UF

10V 402

R18011M

1/16W 402 5%

402

R1800

MF-LF 5%

5%

4021/16W0

R1851

NOSTUFF

MF-LF4025%

8

8

SYNC_MASTER=D8_MLBPCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=N/A

DMI_MIDBUS_CLK100M_N

ITPXDP_CLK100M_N

TP_PCH_GPIO65_CLKOUTFLEX1TP_PCH_GPIO64_CLKOUTFLEX0

PCH_CLKIN_GND1

TP_PCH_GPIO67_CLKOUTFLEX3TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_CL_CLK1

TP_PCH_CL_DATA1PCH_CLK100M_SATAP

TP_PCIE2_R2D_CP

TP_PCIE1_D2RNTP_PCIE1_D2RPTP_PCIE1_R2D_CNTP_PCIE1_R2D_CP

TP_PCIE2_R2D_CN

TP_PCIE2_D2RNTP_PCIE2_D2RP

TP_PCIE_CLK100M_PE0NTP_PCIE_CLK100M_PE0PPCIE_AP_D2R_P

PCIE_CLK100M_AP_N

TP_SATA_D_R2D_CP

TP_SATA_E_D2RNTP_SATA_E_D2RPTP_SATA_E_R2D_CNXDP_PCH_TDI

TP_SATA_C_R2D_CPTP_SATA_C_D2RPTP_SATA_C_D2RN

SATA_SSD_R2D_NSATA_SSD_R2D_P

TP_SATA_C_R2D_CN

PCIE_CLK100M_TBT_N

PEG_CLKREQ_LPCIE_TBT_R2D_C_P<3>

XDP_PCH_TCKHDA_SDOUT_R

SATARDRVR_EN_R

TP_SATA_F_R2D_CNTP_SATA_F_D2RP

SATA_SSD_D2R_P

SATA_HDD_R2D_C_NSATA_HDD_D2R_PPCH_INTRUDER_L

TP_PCH_CL_RST1

PCH_CLK96M_DOTNSML_PCH_1_DATA

TP_SATA_F_D2RN

TP_PCH_L_BKLTENTP_PCH_L_BKLTCTL

TP_LPC_DREQ0_LTBT_PWR_EN_PCH

LPC_SERIRQ

SATA_SSD_D2R_NPCH_CLK32K_RTCX1

SATA_HDD_R2D_C_PSATA_HDD_D2R_N

=PP3V3_S0_PCHPCH_CLK32K_RTCX2

LPC_FRAME_LLFRAME_L

PCH_SATA3RBIASPCH_SATAICOMPPCIE_TBT_D2R_N<0>

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_N

SATARDRVR_ENPCH_CLK25M_XTALIN

TP_PCIE_CLK100M_PE5PTP_PCIE_CLK100M_PE5N

PCH_INTVRMENPCH_INTRUDER_LPCH_SRTCRST_LRTC_RESET_L

NO_TEST=TRUESPI_CLK_R

BJ17BJ20BG20

BG17

AA56

AL56AL53

AN56AM55

AN49AN50AT50AT49

AT46

AV50AV49

AJ53AJ55

BF57

BC54AY52

AG12

BC22BE56

BF22

BJ22BK22

BT23

BC25BA25

AE44AE46

AL50AL49

AT44

AB55BK17

AG18AG17

BK15

BN41

AR56

BD22BN37

AE12

BF38

BF50BA50P27R27V52R52BA2AW5BA5AT9AL2AJ5AJ3BD15AN8AG56BD38

N56M55

R31P31AG9

BT47BN49

BK46BJ46BR46BM50

BU49

BT51BR49

H17A22

AA5W5

AE6AC6D13

J10B13

F13

H10

F15H12J12

A16B15

M15

E17

N15

F18M17

B21

P17E21R20

AF55

W53N52AE11

B17C16

J15L15

L20J20

F25F23

P20

1

2 1

2

2 1 2 1

1

2 1

2

1234

8765

OUT

OUTOUT

OUTOUT

IN

ININ

INININ

INIT3_3V*

GPIO32DMI2TXP

PWRBTN*

RSMRST*

SYS_RESET*

DMI3RXNDMI2RXN

DMI2RXPDMI3RXP

DMI_ZCOMP

SUSACK*

SLP_SUS*

DSWVRMENDF_TVSSLP_LAN*/GPIO29PMSYNCH

SLP_A*

SLP_S3*

SLP_S4*

SUSCLK/GPIO62SUS_STAT*/GPIO61

FDI_LSYNC0FDI_FSYNC1FDI_INTFDI_RXP7FDI_RXP6FDI_RXP5FDI_RXP4FDI_RXP3FDI_RXP1FDI_RXN7FDI_RXN6FDI_RXN5FDI_RXN4FDI_RXN3FDI_RXN2FDI_RXN1FDI_RXN0

RI*

SUSWARN*/GPIO30

PWROKSYS_PWROKDMI_IRCOMPDMI2RBIAS

DMI1TXNDMI0TXN

DMI1RXPDMI0RXP

FDI_RXP0

FDI_LSYNC1

DMI0RXN

FDI_RXP2DMI1RXN

FDI_FSYNC0

APWROK

DMI2TXNDMI3TXN

DMI0TXPDMI1TXP

GPIO31GPIO72

DMI3TXP

SLP_S5*/GPIO63WAKE*

DPWROKDRAMPWROK

(3 OF 10)

DDPB_AUXNDDPB_AUXP

DDPB_0PDDPB_1NDDPB_1P

DDPB_3NDDPB_3P

DDPC_CTRLCLKDDPC_CTRLDATA

DDPC_AUXNDDPC_AUXPDDPC_HPD

DDPC_0N

DDPD_CTRLCLKDDPD_CTRLDATA

DDPD_HPD

DDPD_0NDDPD_0PDDPD_1NDDPD_1PDDPD_2N

DDPD_3P

CRT_BLUECRT_GREENCRT_RED

CRT_DDC_CLKCRT_DDC_DATA

CRT_HSYNCCRT_VSYNC

DAC_IREFCRT_IRTN

SDVO_TVCLKINNSDVO_TVCLKINP

SDVO_STALLNSDVO_STALLP

SDVO_INTNSDVO_INTP

SDVO_CTRLCLKSDVO_CTRLDATA

DDPB_HPD

DDPB_0N

DDPB_2NDDPB_2P

DDPC_0PDDPC_1NDDPC_1PDDPC_2NDDPC_2PDDPC_3NDDPC_3P

DDPD_AUXNDDPD_AUXP

DDPD_2PDDPD_3N

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE CLOSE TO U1800 PIN

SHORT THESE TWO PINS VERY NEAR THE PINS PLACE THE RESISTOR VERY CLOSE TO COMMON POINT

KEEPING TP, IF NEED TO USE IT LATER

10K

5%

R1915

MF-LF 402 5%

R1981

1/16W 402

2.2K

5%

R1980

402 MF-LF 5%

1/16W

SYNC_DATE=03/15/2012SYNC_MASTER=D7_MLB

PCH DMI/FDI/GRAPHICS

PCH_RI_LPCH_DMI2RBIAS

CPU_PROC_SELPCIE_WAKE_L

DMI_S2N_P<1>

DP_IG_B_HPDDP_IG_B_AUX_N

DMI_N2S_P<2>

DMI_S2N_N<0>

TP_PCH_RESERVE_7TP_PCH_RESERVE_5TP_PCH_RESERVE_4TP_PCH_RESERVE_3

TP_PCH_RESERVE_1TP_PCH_RESERVE_2

TP_PCH_RESERVE_8

TP_PCH_RESERVE_12

TP_PCH_RESERVE_15TP_PCH_RESERVE_16TP_PCH_RESERVE_17

TP_PCH_RESERVE_0

TP_PCH_RESERVE_13

TP_PCH_RESERVE_20TP_PCH_RESERVE_21TP_PCH_RESERVE_19TP_PCH_RESERVE_18

TP_PCH_RESERVE_26

TP_PCH_RESERVE_28TP_PCH_RESERVE_27

TP_CRT_IG_BLUETP_CRT_IG_GREEN

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNCTP_CRT_IG_VSYNC

=PP3V3_S0_PCH_GPIOPCH_FDI_RX_N<1>

PM_SYNCPCH_GPIO72

PCH_FDI_RX_P<4>

PCH_FDI_RX_P<5>

TP_PCH_INIT3V3_L

TP_CRT_IG_DDC_DATATP_CRT_IG_RED

prefsb

051-9504 7.0.0

BN56

BC56J38

BT43BK38BE52

E37B37

C36F38

E31

BP45BD43BR42R47BH49F55BC41BM53BN52

BA47BN54

E49C52H46P43H43C49A46D47F43

M43J43B47B45C46H41F45C42

BJ48BU46

BJ38BJ53B31A32

P38J36

B35B33

B43

D51

D33

J41A36

B51

BC46

H38M41

H36R38

BG43AV46

P41

BH50BC44

BT37BG46

Y50

R9R8

R14M12M11

M3L5

AL12AL14

U12U14N2

J3

AL9AL8

M1

B5D5D7C6C9

E11

U43M49M50R50

U44U46U50R44U49AB44AB49E52H52F53J55L56K46

AB50L53Y44G56AB46K49K50M48

AM1AN2AN6

AW3AW1

AR4AR2

AT3AM6

U9U8

U5W3

T3U2

AL15AL17

T1

R12

K8H8

L2G4G2F5F3E2E4

R6N6

B7B11

Y41H50J57

BIBI

BIBI

IN

OUTIN

OUT

OUT

OUT

OUTIN

USB3TN1USB3TP1USB3RN1

USB3RN2USB3RP2

CLKOUT_PCI0CLKOUT_PCI1

USBP13P

AD0AD1AD2AD3

AD18

USBP8PUSBP8NUSBP7P

AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17

AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28

PIRQD*

REQ0*

REQ2*/GPIO52REQ3*/GPIO54

GNT0*

GNT3*/GPIO55

PIRQE*/GPIO2PIRQF*/GPIO3PIRQG*/GPIO4PIRQH*/GPIO5

USBP1NUSBP1P

USBP2NUSBP2P

USBP3NUSBP3P

USBP4NUSBP4P

USBP5NUSBP5P

USBP6NUSBP6P

USBP7N

USBP9NUSBP9P

USBP10N

USBP11NUSBP11P

USB3TN2USB3TP2

USB3TP4

USB3TN4

OC0*/GPIO59

OC2*/GPIO41OC1*/GPIO40

OC3*/GPIO42OC4*/GPIO43OC5*/GPIO9

OC7*/GPIO14OC6*/GPIO10

ININININ

OUT

ININ

IN

BIBI

BIBI

BI

BIBI

BIBI

BI

BIBI

BIBI

BIBI

BIBI

OUT

OUTOUT

OUT

BIBI

BIBI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

UNUSED UNUSED

CAMERA INTERNAL HUB (BT,SMC12)

EHCI - EXT D

UNUSED EHCI - EXT B

UNUSED UNUSED UNUSED EXT D EXT C EXT B EXT A

TIE TRACES TOGETHER CLOSE TO PINS PLACE THE RESISTOR CLOSE TO COMMON POINT

1/16W402

R2002 R2003

0

MF

SIGNAL_MODEL=EMPTY

5% 1/20W MF0

PLACE_NEAR=U1800.BM25:2mm

R2070

10K

MF-LF 4025% 1/16W

R2010

1/16W MF-LF 4025%

10K

R2011

MF-LF 4021/16W

10K

5%

R2012

402MF-LF5% 1/16W

10K

R2013

10K

MF-LF5% 1/16W 402

R2015

10K

MF-LF1/16W 4025%

R2016

10K

MF-LF 4025% 1/16W

10K

MF-LF5%

R2025

4021/16W

10K

402

R2030

PCH PCI/USBSYNC_MASTER=D7_MLB SYNC_DATE=03/15/2012

AP_PWR_ENUSB_EXTB_OC_EHCI_LUSB_EXTC_OC_L

PCI_PERR_L

PCI_INTB_L PCI_INTC_L PCI_INTD_L PCI_REQ0_L

USB_EXTA_OC_R_L

USB_EXTC_OC_R_LUSB_EXTD_OC_R_LUSB_EXTB_OC_EHCI_R_L

AP_PWR_EN_R

USB_EXTD_OC_EHCI_L

USB3_EXTD_RX_F_P USB3_EXTD_RX_F_N

SDCONN_STATE_CHANGE_RUSB_EXTD_OC_EHCI_R_L

AUD_I2C_INT_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

TBT_PWR_REQ_L

PCI_IRDY_L

PCI_TRDY_L PCI_STOP_L BLC_GPIO

TP_PCI_AD<6>

BT_PWR_RST_L

TP_PCH_STRP_ESI_L TP_PCH_STRP_BBS1 JTAG_GMUX_TMS TP_PCI_AD<28>

USB_PCH_10_N USB_PCH_9_P

USB_PCH_7_N USB_PCH_6_P USB_PCH_6_N USB_PCH_5_P USB_PCH_5_N USB_PCH_4_P USB_PCH_4_N USB_PCH_3_P USB_PCH_3_N USB_PCH_2_P USB_PCH_2_N USB_PCH_1_P USB_PCH_1_N USB_PCH_0_P USB_PCH_0_N

TP_PCI_AD<1>

USB3_EXTB_RX_F_P USB3_EXTB_RX_F_N

20 OF 143

20 OF 117

C29E29H31

J27L27

AT11AN14

BK27

BF15BF17BT7BT13

BC6

BR29BN27BD31

BG12BN11BJ12BU9BR12BJ3BR9BJ10BM8BF3BN2BE4BE6BG15

BT11BA14BL2BC4BL4BC2BM13BA9BF9BA8

BP5

BG5

BK8AV11

BA15

BE2

BN9AV9BT15BR4

AV14

BR6BM3

BF11BH8BH9BC11

BA17

BC12BC8

AV15

BK48

BF36BD36

BC33BA33

BM33BM35

BT33BU32

BR32BT31

BN29BM30

BK33BJ33

BF31

BR26BT27

BK25

BJ31BK31

BD27

BJ25

BP13

BN4BP7BG2

BK10

BU12AV8

BM15BJ5

BM25

J31

AT14AT17AT12

F28E27

D25

B25

BM43

BG41BD41

BK43BP43BJ41

BM45BT45

IN

OUTIN

GPIO27

GPIO28

GPIO35/NMI*

GPIO57GPIO8

VSSADAC

GPIO15LAN_PHY_PWR_CTRL/GPIO12

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RDAR://11363991 D7/D7I/D8/J35/J36: RENAME GPU/TBT MUX SELECT TO DP_TBT_SEL

Place this near the T point

R2190

49

114

NOSTUFF0

402 MF-LF

R2101

R2104

2015% 1/20W MF0

201MFR2111

201R21131/20W

335%

PCH MISC

SYNC_DATE=N/ASYNC_MASTER=D8_MLB

DP_TBT_SEL

PCH_CAM_RESET_RENET_LOW_PWR_PCH

JTAG_TBT_TDOAUD_IPHS_SWITCH_EN_PCH_R

HDD_PWR_EN

PCH_PECI

PCH_PROCPWRGD

TP_PCH_PWM0TP_PCH_PWM1TP_PCH_PWM2TP_PCH_PWM3

PCH_RCIN_L

ENET_LOW_PWR_PCH_RPCH_GPIO22

TP_PCH_SST

TBT_SW_RESET_R_LLPCPLUS_GPIO

TP_PCH_TP15

PCH_CAM_RESETSPIROM_USE_MLBPCH_GPIO48

PCH_CAM_EXT_BOOT_L

PCH_BLC_MCU_RESET

PCH_BLC_EXT_BOOT_RPCH_BLC_EXT_BOOT

ISOLATE_CPU_MEM_L

GPU_GOOD GPU_GOOD_R

DP_TBT_SEL_RTBT_SW_RESET_L

PCH_CAM_EXT_BOOT_R_L

PCH_BLC_MCU_RESET_R

prefsb

051-9504 7.0.0

BF55BE54AU56

AV44

BU16

BM57B2

BB57

AA2

AE2AF1

BJ43

BJ55

BJ57

BT53BP51

BU54BU6

BM1

BP1

BU4BU52

AU2

BM55BK50

BT2BP57

BP53

BB55

AE43

F1D1

VCCCLKDMIVCCAPLLDMI2

VCCSPI

VCCIOV5REF

VCCAPLLSATAVCC3_3

DCPSUSBYPVCCACLK

VCCSUS3_3

VCCSSC

VCC3_3DCPSUS

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH output, for decoupling only

Max and Idle = 1mA

20mA Max, 10mA Idle

(VCCIO[1-31] total)3.456A Max, 426mA Idle

PCH output, for decoupling only

57 mA Max, 30mA Idle

1.44 A Max, 474mA Idle

55mA Max, 5mA Idle

20mA Max, 1mA Idle3mA Max, 1mA Idle

200 mA Max, 2mA Idle

(VCCSUS3_3 - 11 TOTAL)

Need to check layout decoupling

409 mA Max, 42mA Idle

Max and Idle = 1 MA

40mA Max, 10mA Idle 40mA Max, 5mA Idle

Max and Idle = 1mA

97mA Max, 15mA Idle

(VCCVRM 4 total)159mA Max, 114mA Idle

105mA Max, 90mA Idle

10 mA Max, 1mA Idle

1.61A Max, 433mA Idle(VCC3_3[1-9] total)

Max and Idle = 1mA

PLACE_NEAR=U1800.BR54:4MM

C2210

0.1UF

402 20%

CERM 10V

C2222

PLACE_NEAR=U1800.BA46:2mm0.1UF

6.3V X5R 10%

0.1UF

PLACE_NEAR=U1800.BU42:2mm

C2232

402 CERM 10VC2231CERM 402

=PP3V3_S5_PCH_VCC_SPI

PP1V8_S0_PCH_VCCVRM_F

PP3V3_S0_PCH_VCCA_DAC_FTP_PPVOUT_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH_VCCTP_DCPSUS_2

=PP3V3_S0_PCH_VCC_GPIO

=PP1V05_S0_PCH_VCCIO_DMI

PP1V8_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_VCCCLKDMITP_PP1V05_S0_PCH_VCCAPLLDMI2

=PP1V05_S0_PCH_VCCIO_USBTP_PP1V05_S0_PCH_VCC_A_CLK

prefsb

051-9504 7.0.0

22 OF 143

22 OF 117

2 1

2 1

2 1 2

1

AG26AG28AJ24

AN34AL34

AJ28AJ26B53

AJ20A19AN32AC32

Y26

V33AA36

Y20Y22Y24

Y28V22V25V27F20

AT1

R56

B41

Y30Y32

Y34

Y36

V36V31F30

AF57

AJ1

AU32AV36AU34AG24

AL24AL28AN22AN24AN26AN28AR24AR26AR28AR30AR36AR38AU30AU36

AC24AC26AC28AC30

AE24AE28AE30AE32AE34AE36

AJ32AJ34AJ36AL32

AR32AR34

BC17BD17BD20

C54

E41

AG32AG34AA34

B56

BU42

BT25AC2

AN52

AG40AG38AG41BA38AN40AN41BF1

U56

AV20AU20A12

AN38

AV41AL5

AE15AE17AG15

AV40

AY25AY27AV24AV26

AV30AV32AY31AY33BJ36BK36BM36AT40AU38BT35

AJ38AE40

AL40

R2

AV28

R54BT56

U31

AC20AE20

VSS VSS

(8 OF 10)

VSSVSS

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

23 OF 143

23 OF 117

AE56BR36

AB15

AB43AA28

AN11AM57AM52AM3AL47AL46AL41AL36AL30AL26AL22AL20AL18AL11

AJ22AJ30

AK6AK52AJ57

AG5AG50AG53AH52AH6

AG30AG36AG43AG44AG46

AF6AG11AG14AG20AG22AF52

AE4AE47AE8AE9AE38

AE14AE18AE22AE26AC54

AC34AC36

AC4AC22

AB47AB52AB57AB6

AB11AA38

AB40AB41

AA30AA26AA24AA22AA20A9A49A42A26

BG33BG36BG31

BF25BF33BF41BF43BF46BF52BF6BG22BG25BG27

BC27BC31BC36BC38BC47BC9BD25BD33BF12BF20

BA41BA44BA49BB1BB3BB52BB6BC14BC15BC20

BA31

AV47AV6AW57AY38AY6B23BA11BA12AV34

AT52AT6AT8AU24AU26AU28AU5AV12AV18AV22

AN54AN9AR20AR22AR52AR6AT15AT18AT43AT47

AN12AN15AN17AN18AN20AN30AN36AN4AN43AN47

AC38

AV38

A29AY22C12

J46J48J5J53K52K6K9L12L17L38L41L43M20M22M25M27M31M33M36M46M52M57M6M8M9N4N54R11R15R17R22R4R41R43R46R49

T6U11U15U17U20U22U25U27U33U36U38U41U47U53V20V38V6W1W55W57Y11Y15Y38Y40Y43Y46Y47Y49Y52Y6AL43AL44R36P36R25P25

BH52BH6BJ1BJ15BK20BK41BK52BK6BM10BM12BM16BM22BM23BM26BM28BM32BM40BM42BM48

BN47BN6BP3BP33BP35BR22BR52BU19BU26BU29BU36BU39C19C32C39C4D15D23D3D35D43D45E19E39E54E6E9F10F12F16F22F26F32F33F35F36F40F42F46F48F50F8G54H15H20H22H25H27H33H6J1J33

T52

BN31BM5BG38

NCNC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

INTEL PDG: 2X 1UFPLACEMENT_NOTES:

PCH VCCIO BYPASS(PCH USB 1.05V PWR)PLACEMENT_NOTEs:

PLACE C2439 AT BALL BF1

100

5%

402 1/16WR24052

1

20%

402 CERM

0.1UF

10VC2438

PLACE C2438 AT BALL BT25

SOT-363BAT54DW-X-G

D2400

402 5%

CERM 10V

0.1UF

20%

CERM 402 10VC2441

PLACE C2441 AT BALL AV28

PLACE C2450 AT BALL AV26

1UF

CERM 402 10%

6.3VC2450

PLACE C2419 AT BALL B41

402 10%

1UF

6.3VC2419

C2422

PLACE C2422 AT BALL AU20

402 CERM

1UF

6.3V 10%

PLACE C2449 AT BALL AY27

CERM 402

1UF

10%

6.3VC2449

PLACE C2410 AT BALL Y20

10UF

C2410CERM 20%

6.3V 805-1

PLACE C2480 AT BALL AC20

6.3V 805-1C2437

PLACE C2435 AT BALL AE17

CERM

1UF

10%

6.3V 402C2435

PLACE C2434 AT BALL AE15

1UF

6.3V 402 CERM 10%

PLACE C2469 AT BALL V36

10%

CERM 402

6.3V

PLACE C2401 AT BALL V22

C240120%

2.2UF

C2412

402 6.3V 10%

PLACE C2412 AT BALL AT40

PLACE C2499 AT BALL AV40

402 20%

CERM10V

0.1UF

C2499

CERM 10%

1UF

402

C24426.3V

PLACE C2442 AT BALL AN52

C2445

10UF

PLACE C2445 AT BALL R2

805-1CERM20%

C2443

PLACE C2443 AT BALL AJ1

6.3V 402

1UF

10%

CERM 402

CERM

C243610%

PLACE C2444 AT BALL BA38

10%

402 6.3V

C2446

805-1 20%

CERMC2472

PLACE C2472 AT BALL V31

10UF1UF

402 10%

PLACE C2470 AT BALL Y32

6.3VC2470

PLACE C2482 AT BALL AC24

C2482CERM 10%

1UF

6.3V 402

PLACE C2481 AT BALL AC32

6.3V 402

1UF

10%

CERMC2481

CERMC24836.3V

1UF

10%

402

PLACE C2483 AT BALL AL34

PLACE C2407 AT BALL Y28

402 CERM

C24156.3V 402

PLACE C2420 AT BALL AU32

6.3V20%

CERM

10UF

805-1C2420

PLACE C2418 AT BALL AN22

C2418CERM 20%

10UF

805-1

PLACE C2498 AT BALL AR24

CERM 10%

1UF

402C2498

PLACE C2496 AT BALL AR36

C2496

1UF

6.3V 10%

CERM 402 6.3V

C2456

PLACE C2456 AT BALL AG28

CERM 402

C241110%

X5R

1UFPLACE C2411 AT BALL AJ20

2.2UF

10%

X5R 6.3V

PLACE C2412 AT BALL AV30

C2413

0.1UF

10%

X7R-CERM 0402

C2484

0.1UF

10%

X7R-CERM 0402

C2430

0402 X7R-CERM 16V

C2423

0402 X7R-CERM 16V

C2447

X7R-CERM 10%

0402 16V

0.1UF

SYNC_DATE=N/ASYNC_MASTER=D8_MLB

PCH DECOUPLING

PP1V8_S0_PCH_VCCVRM_F

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM MAKE_BASE=TRUE VOLTAGE=1.8V

VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_S0_PCH_V5REF

prefsb

051-9504 7.0.0

24 OF 143

24 OF 117

2 1

2 1

6

1 5

3

4 2

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

21

2 1

21

2 1

21

2 1

2 1

21

2 1

2 1

21

2 1

2 1

2 1

2 1

2 1

2 1

21

2 1

2 1

2 1

2 1

2 1

21

2 1

21

2 1

2 1

21

21

2 1

2 1

2 1

2 1

21

2 1

21

21

21

2 1

2 1

2 1

2 1

21

2 1

21

21

21

21

21

21

21

21

21

ININ

ININ

ININ

NC

INBI

OUT

ININ

ININ

ININ

ININ

ININ

ININ

IN

INOUTOUTOUT

OUT

IN

IN

ININININ

OUTOUTOUTIN

ININ

ININ

ININ

ININ

ININ

IN

IN

OUTOUT

ININ

ININ

NC

BIIN

OUT

ININ

ININOUT

IN

NCNC

NCNC

NCNC

NC

NCNC

NCNC

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- Unused GPIOs 0 & 15 not isolated.

be replaced with aliases Otherwise these R’s must

and path to non-XDP signal destination.

Pull-up to 3.3V on csa 26 (PCH Support)1K series resistor on csa 26 (PCH Support)

Connects to PCH XDP Conn

- For isolated GPIOs:

- MXM_GOOD not isolated as only LED is affected.

needs to split between route from PCH to J2550

- ’Output’ PCH/XDP signals require pulls.

PCH Micro2-XDP

1K series resistor on csa 26 (PCH Support)obsdata_b0

obsdata_c2obsdata_c3

obsen_c0

obsen_d0

obsdata_c0obsen_c1

itpclk/hook4

tdo

tditms

obsdata_a2obsdata_a3

obsen_b0

vcc_obs_abpwrgd/hook0

sclsdahook3hook1obsdata_b2obsen_b1

hook2obsdata_b0

tck0tck1sclsda

vcc_obs_abhook2hook3

hook1pwrgd/hook0obsdata_b3obsdata_b2obsdata_b1

obsdata_a1obsdata_a0

obsdata_a0obsen_a1obsen_a0

obsdata_b1

obsdata_b3

CPU Micro2-XDP

obsdata_a1

PCH/XDP Signal Isolation Notes:

events while using PCH XDP.

obsdata_d0obsdata_d1

obsdata_d2

obsdata_c0obsen_c1obsen_a0

XDP Signals

- ’Output’ non-XDP signals require pulls.

If PCH XDP not implemented, all of R2524-R2537 can

connect to appropriate non-XDP signals on PCB.

obsen_b1obsen_b0oc3#/gpio42

oc2#/gpio41oc0#/gpio59

oc6#/gpio10oc5#/gpio9

sata1gp/gpio19sata0gp/gpio21

gpio0

gpio35

sata5gp/gpio49sata4gp/gpio16mgpio7/gpio28

xdp_present#

trstndbr#/hook7itpclk#/hook5obsdata_d2obsdata_d1obsdata_d0

be stuffed even in production so that PCH pins

R2524-R2537 should be placed where signal path

- USB OC#’s not isolated, avoid USB port overcurrent

tck0tck1

0

R25055%

XDP

1/16W

R1554.1:5MM0XDP

R25001/16W5% MF-LF402

1K

MF-LF

U4900.D10:350MM0

R2501

4021/16W

XDP

5%

MF-LF

U1000.H36:25MM1K

51

MF-LF5%

402MF-LF1/16W5%

5%

1/16W402

200

1/16WR2560402

MF-LF

1/16W4025%

100

U1800.BA43:10MM

XDP

R25651/16W

5%

402MF-LF

402MF-LF1/16W33

5%

402MF-LF33

1/16WR2521

5%

MF-LF33

402 1/16WR2522

MF-LF

402 1/16W5%

33 R2523 R2524

1/16W5%

402MF-LF33

5%

1/16W

402MF-LF33

R2525

402MF-LF1/16W5%

33 R2526

5%

1/16WMF-LF33

402R2527

402 1/16WMF-LF

R2537

1/16W33

402MF-LF

1/16WR2534

402MF-LF 5%

33

1/16WR2535

MF-LF1/16W5%

33

402R2536

21

MF-LF33

402 1/16W5%

R2531

402MF-LF1/16W5%

33 R2532

11 25 99

11 25 99

U4900.D10:117MMXDP

0.1UF

C2551X7R-CERM16V0402

CPU and PCH XDPSYNC_MASTER=D7_MLB SYNC_DATE=01/26/2012

=PP3V3_S5_XDP

=PPVCCIO_S0_XDP

=SMBUS_XDP_SCL

XDP_CPU_PWRGDXDP_CPU_PWRBTN_L

XDP_CPU_TMS

=PP3V3_S5_XDPXDP_CPU_TDI

VOLTAGE=3.3V

PP3V3_S5_XDP_R

MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM

XDP_FC0_PCH_GPIO15

GPU_GOOD_R

DP_TBT_SEL_R

XDP_DB3_SDCONN_STATE_CHANGEXDP_DB1_USB_EXTD_OC_EHCI_LXDP_DB0_USB_EXTB_OC_EHCI_LXDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_LXDP_DA1_USB_EXTB_OC_LSDCONN_STATE_CHANGE_R

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_CPU_PLTRST_L

XDP_DA0_USB_EXTA_OC_L

XDP_DD3_ENET_LOW_PWR_PCHXDP_DC1_GPU_GOOD

XDP_CPU_CFG<0>

PM_SYSRST_LCPU_CFG<16>

XDP_DD2_AUD_IPHS_SWITCH_EN_PCHXDP_DD1_JTAG_TBT_TCKXDP_DD0_DP_TBT_SEL

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DD1_JTAG_TBT_TCKTBT_CIO_PLUG_EVENT_R XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_PCH_TDI

XDP_DC3_SATARDRVR_ENXDP_DC2_DP_AUXCH_ISOLXDP_DC0_ISOLATE_CPU_MEM_L

XDP_PCH_TDIXDP_PCH_TDOXDP_DC2_DP_AUXCH_ISOL

XDP_DC1_GPU_GOODXDP_DA3_USB_EXTD_OC_L

AP_PWR_EN_R

XDP_DD0_DP_TBT_SELXDP_DA2_USB_EXTC_OC_L

XDP_BPM_L<6>

CPU_CFG<0>

XDP_PCH_TMSXDP_DD2_AUD_IPHS_SWITCH_EN_PCH

XDP_DC3_SATARDRVR_EN

ITPXDP_CLK100M_NCPU_CFG<6>

XDP_CPU_CLK100M_NXDP_CPU_CLK100M_P

DP_AUXCH_ISOL_R

PM_PWRBTN_L

prefsb

051-9504 7.0.0

43413529231917151175

9

32

13

1012141681

21

27

33

3739

454749

5755

59

6

20222426

3230

38

4244

4846

505254

5856

60

28

40

184

3436

25

31

6162

6364

5351

43413529231917151175

9

32

13

1012141681

21

27

33

3739

454749

5755

59

6

20222426

3230

38

4244

4846

505254

5856

60

28

40

184

3436

25

31

6162

6364

1

21

21

21

21

21

NCNC

OUTOUT

IN

OUTIN

OUT

NCNC

THRM

XINXOUT

OUT

Y A

OUT

Y A

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED

ENET > S0 > TBT, so ENET is used here

VDD must be powered if any VDDIO is

GreenClk 25MHz Power

VTT VOLTAGE DIVIDER AND PU ON CPU PAGE

Clock series termination

511-0054

RDAR://11218892 TESTPOINT TO RESET RTC FOR APPLE CARE

GPIO Isolation to prevent glitches on critical core well GPIOs

1/16WR2602

BAT54DW-X-G

SOT-363D2600

33

MF-LF 402

5%

1/16WR2681

MF-LFR2690

MF-LF 402

MF-LF 5%

100K

1/16W 402R2680

J2600

SM

BB10201-C1403-7H

MF-LF 402

10M

1/16W5%

R2611

MC74VHC1G08SOT23-5-HF

U2680

0.1UF

20%

CERM 402C2690

402 MF-LF

MF-LF

R26995%

1/16W

35 112

1/16W5%

402 MF-LF

33

R2688

1/16W5%

402 MF-LF

402 CERM 20%

0.1UF

10VC2622 C2624

0.1UF

402 20%

1MR2606

1/16W

39 101

PLACE_NEAR=U2600.4:10MM

MF-LF 402 5%

33R2628

SLG3NB146V

CRITICAL32.768K-12.5PFY2610SM-HF

SILK_PART=SYS RESET

0

5%

MF-LF 402 1/16WR2696NOSTUFF

47 116

R2694VREFMRGN:EXT33

5%

1/16W 402

0.1UF

CERM 402 10V

74LVC2G08GT

U26508

CERM

0.1UF

402

SOT83374LVC2G08GT

39 41 113

MF-LF4025%

1/16W

4.7K

R2697

1/16W402MF-LF

140

1%

R26721%

402MF-LF

R26911/16W5%

0402 C0G-CERM 50V5%

PLACE_NEAR=Y2610.1:2MM12PF

SYNC_MASTER=D8_MLB

=PP3V3_S5_PCH

AUD_IPHS_SWITCH_EN

LPC_CLK33M_LPCPLUSLPC_CLK33M_LPCPLUS_R

PPVBATT_G3_RTC_R

PP3V3_G3_RTC

MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM

PCH_CLK25M_XTALIN

TBT_PWR_EN

=PP3V3_S5_PCHTBT_PWR_EN_PCH

XDP_CPU_PLTRST_L

PCA9557D_RESET_L

prefsb

051-9504 7.0.0

26 OF 143

26 OF 117

3 6

2 4 1

2

34

21

2 1 2

1 2

110

721

2 1

36

5

51

2

34

BIBI

NCNCNCNC

TEST1

USBDM_DN1USBDP_DN1VBUS_DET

USBDP_DN2USBDM_DN2

SUSP_IND/NON_REM0

NCXTALOUTXTALIN/CLKINTESTRESET*

HS_INDNON_REM1

PRTPWR1PRTPWR2OCS1*

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NON_REM 0 and 1 are used to indicate whether thedownstream ports are removable or captive

NON_REM[1:0] = 1x -> ports 1 and 2 are non-removable

via array to GND

NON_REM[1:0] = 01 -> port 1 is non-removable

ePad needs a minimum of 3x3

NON_REM[1:0] = 00 -> ports 1 and 2 are removable155S0220

402MF-LF100K

R2708

402100KMF-LF5%

1/16W

5%

10KMF-LF402

R2703

C2705

6.3V603

4.7UF10%

X5R-CERM

1UF10%

C2708

X5R

402MF-LF5%

1M1/16W

R2706

R2711

2015%

1/20WMF4.7K

1/16W402

R2704

100K5%

18PF

18PF

040250VC0G-CERM5%

C2702

MF-LF5%

C2712

16VCERM

CRITICAL

Y2700

5X3.2X1.5-SM24.000M-50PPM-16PF

X7R-CERM16V0.1UF0402

C2709

X7R-CERM16V0.1UF0402

C2710

X7R-CERM16V0.1UF0402

C2711

C2703

10%

0.1UF040216VX7R-CERM

10%

0.1UF040216VX7R-CERM

C2704

C2707

X7R-CERM16V0.1UF

0.1UF10%

X7R-CERM

C2706

SYNC_DATE=03/23/2012SYNC_MASTER=D8_ROSITA

USB 2.0 HUB (BT/SMC)

MIN_NECK_WIDTH=0.25MM MAX_NECK_LENGTH=3MM

PP3V3_S4_USB_HUB_VDD

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3MM VOLTAGE=1.2V

PP1V2_USB_HUB_PLLFILT

MIN_LINE_WIDTH=0.4MM

PP1V2_USB_HUB_CRFILT

VOLTAGE=1.2V MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.2MM

USB_HUB_XTAL2_R

USB_HUB_XTAL1

PM_PGOOD_P3V3_S4_FETUSB_HUB_RESET_L

USB_HUB_NON_REM1

USB_HUB_XTAL2

USB_HUB_NON_REM0USB_PCH_7_P

USB_HUB_RBIAS

USB_HUB_2NUSB_BT_P

USB_HUB_2P

prefsb

051-9504 7.0.0

21

32

19

523246171613

71181226

21

21

21

21

21

212

1

21

IN

GD

S

OUT

D

SG

D

SG

D

SG

D

SG

NC

NC

IN

DS

GG

D

SG

IN

ININ

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEMVTT_EN = CPU_PWRGD * PM_SLP_S3_L (VTT is enabled when PCH tells CPU to enable VCCORE)

MEMVTT Clamp actively holds MEMVTT rail low until MEMVTT is enabled.

Clamping MEMVTT will keep the MEM_CKE low until CPU actively controls it.

CPU does not drive MEM_CKE until VCCORE activated but CPU 1V5 (VDDQ) leaks into it.

MEMVTT_EN Generator

Enables MEMVTT when PCH drives CPU PWRGD.

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L (Block CPU from driving MEM_RESET_L in S3)

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuits below handle MEMVTT power during S0->S3->S0 transitions, as well

WHEN LOW: MEM_RESET_L IS ISOLATED.

0 0 1

1 1

1 1

1 1

1

1

1 1 1

1 1

0 (*) X X

CPU_MEM_RESET_L

MEMVTT_EN

1

1 0

1 1 1

1 1 0

1

0 1 1 1

1 1

1 1

1 0 0 0 0 0 0

NOTE: On a S5->S0 transition, ISOLATE_CPU_MEM_L will default low.

must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

Ensures CKE signals are held low in S3 and in S0 before CPU PWRGD

75mA max load @ 0.75V 60mW max power

MEMVTT Clamp

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

With optional delay from 1V5 S0 PGOOD

1V5 S0 "PGOOD" for CPU

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behaviour of signals.

WHEN HIGH: MEM_RESET_L NOT ISOLATED.

MEM_RESET_L Generator

rdar://11117167

S3

PLT_RESET_L equivalent Open-drain buffer

1/16W402

R2850

MF-LF4021/16W

4021/16W

CRITICAL

Q2850

SSM6N15AFESOT563

Q2850

CRITICAL SSM6N15AFESOT563

Q2810

SOT563SSM6N15AFE CRITICAL

74LVC1G07SC70

1/16W

20K50V

C2899

40210%

CERM0.0022UF

Q2899

2N7002SOT23-HF1

5%

1/16W 402 MF-LF

R2899

1/16W5%

402 MF-LF

20K

Q2898SOT-363

0.01UF

0.001UF20%

0402

NOSTUFF

C2820

50VCERM

50VCERM

C2851

0.001UF20%

0402NOSTUFF

4025%

MF-LF0

R2831

402

01/16W5%

NOSTUFF

R2832

R2830

1/16W402

402

R2833

20%

0.01UF16V

C2831

NOSTUFF

X7R-CERM0402

SYNC_DATE=04/23/2012CPU Memory S3 SupportSYNC_MASTER=D8_MARK

6

12

3

45

6

12

4

1 325

1

221

1

32

21

21

12

12

1

2

12

21

BI

IN

BIBI

BIBI

BIBI

BIIN

BI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BI

BIBI

BI

BIBI

BIBI

ININ

ININ

ININ

ININ

ININ

ININ

ININ

BIBI

BIBI

BI

IN

BIBI

BIBI

BIBI

BI

BIBI

BIBI

BI

BIBI

BIBI

BIBI

BIBI

OUTBIIN

IN

IN

ININ

ININ

ININ

ININ

ININ

ININ

ININ

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

VSS_3DM0

VSS_12DQ16

VSS_14

DQ18

VSS_21

VSS_24DQ27

VSS_48DQ58DM7VSS_47DQ57DQ56VSS_45

DQ50DQ51

DQ49VSS_40

DQS6VSS_43DQ48

VSS_36DQ42DQ43VSS_38DM5

DQ40

VSS_35

VSS_33

DQ41DQ35

VSS_28

DQS4VSS_31DQ34

DQ32TESTVDD_16

VDD_4

A5

CKE0

VSS_22DM3

DQ26

VSS_19DQ19

DQ25DQ24

VSS_17DQS2DQ17

DQ10DQ11VSS_10DQS1VSS_8DQ9DQ8VSS_6DQ3DQ2

SCLSDA

VSS_49DQ62DQ63VSS_51DQS7

VTT_1

DM6

DQ53VSS_41

VSS_42

DQ60DQ61VSS_46DQ52

DQ45VSS_34

VSS_39

DQS5VSS_37DQ46DQ44

DQ47

VSS_32DM4

VDD_17VREFCAVSS_27DQ36DQ37VSS_29

VSS_30DQ38DQ39

BA1VDD_11

VDD_13

ODT0VDD_15ODT1NC_1

CK1A0A2

A6A4

A11A7

VDD_7VDD_5

VDD_9

VDD_3A14A15

CKE1VDD_1VSS_25DQ30

DQS3VSS_23

DM2

DQ29VSS_20DQ28

DQ23VSS_18

VSS_16DQ22VSS_15DQ21

DM1

DQ13VSS_9

VSS_11DQ14DQ15VSS_13DQ20

DQ12VSS_7VSS_4

DQ1

DQ7DQ6

DQ4DQ5

DQS0VSS_5VSS_2VSS_0

VSS_44DQ55DQ54

A3

A10_APBA0VDD_12

VDD_14A13KEY

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Signal aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

30 33

30 33

10VCERM

C2931

20%

0.1UF

402CERM

10K R2940

1/16W5%

402MF-LF20%

6.3V402-LF

C2940 2.2UF

C2900

6.3V20%

603

6.3V603

10UF

20%

C2910 0.1UF

CERM20%

402

C2911 0.1UF

40220%

CERM

C2912

10V402CERM

0.1UF

CERM40220%

10V

C2914

CERM402

10V402CERM

0.1UF

20%

C2916

10V402CERM

0.1UF

CERM

C2917 0.1UF

40220%

C2918

10V402CERM

10V402CERM

0.1UF

10V402CERM

0.1UF

40220%

CERM

10V402CERM

20%

402CERM

0.1UF

10V

1UF

X5R10%

C2953 C2952

10V402

1UF

C2951

1UF

X5R10%

C2950

10V402

29 OF 143

29 OF 117

21

21

21

21

1

21

22

1

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

5

13

911

3739

43

51

61

7169

198186169

152135

121115

114113

110

104103

6245

3027

10

70

757779818385

89

195

203

199201197193

189191187185183181179

175177

165167

171173163

155157159161153

147

151

145

149143

133

137139141

129125123

87

91

73

6563

67

5553

5957

494741

33353129252321191715

202200

190192194196188

204

170

166168

172

180182184

164

148150

162

154156158146

160

144136

124126128130132134

138140142

108106

112

116118120122

1029896

9092

8486

9488

100

828078

74767268

6466

46

586056

5254

4850

4442

28

2426

3234363840

222013

7

1816

46

121482

178176174

95

107109111

117119

205206207208209

BI

IN

BIBI

BIBI

BIBI

BIIN

BI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BI

BIBI

BI

BIBI

BIBI

ININ

ININ

ININ

ININ

ININ

ININ

ININ

BIBI

BIBI

BI

IN

BIBI

BIBI

BIBI

BI

BIBI

BIBI

BI

BIBI

BIBI

BIBI

BIBI

OUTBIIN

IN

IN

ININ

ININ

ININ

ININ

ININ

ININ

ININ

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

VSS_3DM0

VSS_12DQ16

VSS_14

DQ18

VSS_21

VSS_24DQ27

VSS_48DQ58DM7VSS_47DQ57DQ56VSS_45

DQ50DQ51

DQ49VSS_40

DQS6VSS_43DQ48

VSS_36DQ42DQ43VSS_38DM5

DQ40

VSS_35

VSS_33

DQ41DQ35

VSS_28

DQS4VSS_31DQ34

DQ32TESTVDD_16

VDD_4

A5

CKE0

VSS_22DM3

DQ26

VSS_19DQ19

DQ25DQ24

VSS_17DQS2DQ17

DQ10DQ11VSS_10DQS1VSS_8DQ9DQ8VSS_6DQ3DQ2

SCLSDA

VSS_49DQ62DQ63VSS_51DQS7

VTT_1

DM6

DQ53VSS_41

VSS_42

DQ60DQ61VSS_46DQ52

DQ45VSS_34

VSS_39

DQS5VSS_37DQ46DQ44

DQ47

VSS_32DM4

VDD_17VREFCAVSS_27DQ36DQ37VSS_29

VSS_30DQ38DQ39

BA1VDD_11

VDD_13

ODT0VDD_15ODT1NC_1

CK1A0A2

A6A4

A11A7

VDD_7VDD_5

VDD_9

VDD_3A14A15

CKE1VDD_1VSS_25DQ30

DQS3VSS_23

DM2

DQ29VSS_20DQ28

DQ23VSS_18

VSS_16DQ22VSS_15DQ21

DM1

DQ13VSS_9

VSS_11DQ14DQ15VSS_13DQ20

DQ12VSS_7VSS_4

DQ1

DQ7DQ6

DQ4DQ5

DQS0VSS_5VSS_2VSS_0

VSS_44DQ55DQ54

A3

A10_APBA0VDD_12

VDD_14A13KEY

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

P/N: 516S1030

29 33

29 33

402CERM

402-LFCERM

402

C3040

6.3V20%

402-LFCERM

2.2UF

C3000

6.3V20%

603

6.3V20%

603

10UF

C3010 0.1UF

CERM40220%

C3011 0.1UF

CERM40220%

C3012 0.1UF

CERM40220%

C3013 0.1UF

CERM40220%

C3014 0.1UF

CERM40220%

C3015 0.1UF

CERM40220%

C3016 0.1UF

10V402CERM

C3017 0.1UF

20%

CERM402

C3018

CERM40210V

CERM10V

10V402CERM

10V402CERM

0.1UF C3023 0.1UF

10V402CERM

1UF 1UF

C3051

10V402402

30 OF 143

30 OF 117

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

5

13

911

3739

43

51

61

7169

198186169

152135

121115

114113

110

104103

6245

3027

10

70

757779818385

89

195

203

199201197193

189191187185183181179

175177

165167

171173163

155157159161153

147

151

145

149143

133

137139141

129125123

87

91

73

6563

67

5553

5957

494741

33353129252321191715

202200

190192194196188

204

170

166168

172

180182184

164

148150

162

154156158146

160

144136

124126128130132134

138140142

108106

112

116118120122

1029896

9092

8486

9488

100

828078

74767268

6466

46

586056

5254

4850

4442

28

2426

3234363840

222013

7

1816

46

121482

178176174

95

107109111

117119

205206207208209

IN

ININ

ININ

IN

ININ

ININ

IN

NC

BIBI

BIBI

BIBI

BI

IN

BIBI

BI

BIBI

BIBI

BI

IN

BI

BIBI

BIBI

IN

IN

ININ

IN

ININ

ININ

ININ

VSS_3DM0

VSS_12DQ16

VSS_14

DQ18

VSS_21

VSS_24DQ27

VSS_48DQ58DM7VSS_47DQ57DQ56VSS_45

DQ50DQ51

DQ49VSS_40

DQS6VSS_43DQ48

VSS_36DQ42DQ43VSS_38DM5

DQ40

VSS_35

VSS_33

DQ41DQ35

VSS_28

DQS4VSS_31DQ34

DQ32TESTVDD_16

VDD_4

A5

CKE0

VSS_22DM3

DQ26

VSS_19DQ19

DQ25DQ24

VSS_17DQS2DQ17

DQ10DQ11VSS_10DQS1VSS_8DQ9DQ8VSS_6DQ3DQ2

SCLSDA

VSS_49DQ62DQ63VSS_51DQS7

VTT_1

DM6

DQ53VSS_41

VSS_42

DQ60DQ61VSS_46DQ52

DQ45VSS_34

VSS_39

DQS5VSS_37DQ46DQ44

DQ47

VSS_32DM4

VDD_17VREFCAVSS_27DQ36DQ37VSS_29

VSS_30DQ38DQ39

BA1VDD_11

VDD_13

ODT0VDD_15ODT1NC_1

CK1A0A2

A6A4

A11A7

VDD_7VDD_5

VDD_9

VDD_3A14A15

CKE1VDD_1VSS_25DQ30

DQS3VSS_23

DM2

DQ29VSS_20DQ28

DQ23VSS_18

VSS_16DQ22VSS_15DQ21

DM1

DQ13VSS_9

VSS_11DQ14DQ15VSS_13DQ20

DQ12VSS_7VSS_4

DQ1

DQ7DQ6

DQ4DQ5

DQS0VSS_5VSS_2VSS_0

VSS_44DQ55DQ54

A3

A10_APBA0VDD_12

VDD_14A13KEY

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BI

BIBI

BI

OUT

ININ

ININ

ININ

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBIBIBI

BIBI

BIBI

BIBI

BIBI

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- =PPVDDQ_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PP1V5_S0_MEM_B

Signal aliases required by this page:

BOM options provided by this page:

0.1UF

20%

C3116 0.1UF

CERM40210V

12 97

10V402

C3115 0.1UF

CERM20%

CERM

C3114

40220%

0.1UF

10V

C3113

CERM40220%

0.1UF

C3122

10V402CERM

0.1UF C3121

10V

0.1UF

CERM40220%

0.1UF C3120

CERM40210V

C3119

10V402CERM

0.1UF C3111

CERM40220%

0.1UF C3110

10V402CERM

0.1UF

20%

32 33

C3118 0.1UF

CERM40220%

C3101

X5R20%

6.3V

10UF C3100 10UF

X5R20%

402MF-LF

10K

C3140

6.3V20%

402-LFCERM

31 OF 143

31 OF 117

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

5

13

911

3739

43

51

61

7169

198186169

152135

121115

114113

110

104103

6245

3027

10

70

757779818385

89

195

203

199201197193

189191187185183181179

175177

165167

171173163

155157159161153

147

151

145

149143

133

137139141

129125123

87

91

73

6563

67

5553

5957

494741

33353129252321191715

202200

190192194196188

204

170

166168

172

180182184

164

148150

162

154156158146

160

144136

124126128130132134

138140142

108106

112

116118120122

1029896

9092

8486

9488

100

828078

74767268

6466

46

586056

5254

4850

4442

28

2426

3234363840

222013

7

1816

46

121482

178176174

95

107109111

117119

205206207208209

21

21

21

21

1

2

1

22

1

21

IN

ININ

ININ

IN

ININ

ININ

IN

NC

BIBI

BIBI

BIBI

BI

IN

BIBI

BI

BIBI

BIBI

BI

IN

BI

BIBI

BIBI

IN

IN

ININ

IN

ININ

ININ

ININ

VSS_3DM0

VSS_12DQ16

VSS_14

DQ18

VSS_21

VSS_24DQ27

VSS_48DQ58DM7VSS_47DQ57DQ56VSS_45

DQ50DQ51

DQ49VSS_40

DQS6VSS_43DQ48

VSS_36DQ42DQ43VSS_38DM5

DQ40

VSS_35

VSS_33

DQ41DQ35

VSS_28

DQS4VSS_31DQ34

DQ32TESTVDD_16

VDD_4

A5

CKE0

VSS_22DM3

DQ26

VSS_19DQ19

DQ25DQ24

VSS_17DQS2DQ17

DQ10DQ11VSS_10DQS1VSS_8DQ9DQ8VSS_6DQ3DQ2

SCLSDA

VSS_49DQ62DQ63VSS_51DQS7

VTT_1

DM6

DQ53VSS_41

VSS_42

DQ60DQ61VSS_46DQ52

DQ45VSS_34

VSS_39

DQS5VSS_37DQ46DQ44

DQ47

VSS_32DM4

VDD_17VREFCAVSS_27DQ36DQ37VSS_29

VSS_30DQ38DQ39

BA1VDD_11

VDD_13

ODT0VDD_15ODT1NC_1

CK1A0A2

A6A4

A11A7

VDD_7VDD_5

VDD_9

VDD_3A14A15

CKE1VDD_1VSS_25DQ30

DQS3VSS_23

DM2

DQ29VSS_20DQ28

DQ23VSS_18

VSS_16DQ22VSS_15DQ21

DM1

DQ13VSS_9

VSS_11DQ14DQ15VSS_13DQ20

DQ12VSS_7VSS_4

DQ1

DQ7DQ6

DQ4DQ5

DQS0VSS_5VSS_2VSS_0

VSS_44DQ55DQ54

A3

A10_APBA0VDD_12

VDD_14A13KEY

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BI

BIBI

BI

OUT

ININ

ININ

ININ

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBIBIBI

BIBI

BIBI

BIBI

BIBI

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power aliases required by this page:

Signal aliases required by this page:

Page Notes

C3253

10V402

0.1UF C3223

C3216

10V402CERM

0.1UF

12 97

C3215

10V402CERM

0.1UF C3214

10V402CERM

0.1UF C3213

10V402CERM

0.1UF

C3222

10V402CERM

0.1UF C3221

0.1UF

CERM10V402

C3220

20%

402CERM

0.1UF C3219

10V402CERM

0.1UF

C3212 0.1UF

CERM40220%

C3211 0.1UF

CERM40220%

0.1UF C3210

CERM40220%

31 33

C3218 0.1UF

CERM40220%

C3201

6.3V20%

10UF

603

C3200 10UF

X5R20%

402-LFCERM

402-LFCERM

32 OF 143

32 OF 117

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

5

13

911

3739

43

51

61

7169

198186169

152135

121115

114113

110

104103

6245

3027

10

70

757779818385

89

195

203

199201197193

189191187185183181179

175177

165167

171173163

155157159161153

147

151

145

149143

133

137139141

129125123

87

91

73

6563

67

5553

5957

494741

33353129252321191715

202200

190192194196188

204

170

166168

172

180182184

164

148150

162

154156158146

160

144136

124126128130132134

138140142

108106

112

116118120122

1029896

9092

8486

9488

100

828078

74767268

6466

46

586056

5254

4850

4442

28

2426

3234363840

222013

7

1816

46

121482

178176174

95

107109111

117119

205206207208209

21

21

21

21

21

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=03/19/2012DDR3 ALIASES AND BITSWAPSSYNC_MASTER=D8_KOSECOFF

MAKE_BASE=TRUEMEM_A_DQS_N<6>

MEM_B_DQ<37>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<13> MAKE_BASE=TRUEMEM_B_DQ<14>

MEM_B_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_N<2>

MAKE_BASE=TRUEMEM_A_DQ<51> MAKE_BASE=TRUE

MEM_A_DQ<45>

MEM_A_DQ<46>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_A_DQ<47>

MAKE_BASE=TRUEMEM_A_DQS_P<5> MAKE_BASE=TRUE

MEM_A_DQS_N<5>

MEM_A_DQ<32>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_A_DQ<33>

MAKE_BASE=TRUEMEM_B_DQ<32>

MEM_B_DQ<33>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_B_DQ<35>

MAKE_BASE=TRUEMEM_B_DQS_N<5>

MAKE_BASE=TRUEMEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_A_DQ<25>

MAKE_BASE=TRUEMEM_A_DQ<24>

MEM_A_DQ<30>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<8>

MEM_A_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<12>

MEM_A_DQ<55>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<10>

MAKE_BASE=TRUEMEM_A_DQ<14>

MAKE_BASE=TRUEMEM_A_DQ<21>

MAKE_BASE=TRUEMEM_A_DQ<16>

MEM_A_DQ<38>

MAKE_BASE=TRUEMEM_A_DQ<36>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<27>

MEM_B_DQ<63>

MAKE_BASE=TRUEMEM_B_DQ<61>

MAKE_BASE=TRUEMEM_B_DQ<60>

MAKE_BASE=TRUEMEM_A_DQ<37>

MAKE_BASE=TRUEMEM_A_DQS_P<6>

MAKE_BASE=TRUEMEM_B_DQS_P<5>

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<15>

MAKE_BASE=TRUEMEM_A_DQ<5>

MAKE_BASE=TRUEMEM_A_DQ<4>

MAKE_BASE=TRUEMEM_A_DQ<3>

MAKE_BASE=TRUEMEM_A_DQ<2>

MAKE_BASE=TRUEMEM_A_DQ<1>

MAKE_BASE=TRUEMEM_A_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQS_N<1>

MAKE_BASE=TRUEMEM_A_DQS_P<1>

MAKE_BASE=TRUEMEM_A_DQS_N<4>

MAKE_BASE=TRUEMEM_B_DQ<47>

MAKE_BASE=TRUEMEM_B_DQ<41>

MAKE_BASE=TRUEMEM_B_DQS_P<6>

MAKE_BASE=TRUEMEM_B_DQ<50> MAKE_BASE=TRUEMEM_B_DQ<51>

MAKE_BASE=TRUEMEM_B_DQ<43> MAKE_BASE=TRUEMEM_B_DQ<44> MAKE_BASE=TRUEMEM_B_DQ<45> MAKE_BASE=TRUEMEM_B_DQ<46>

MEM_B_DQ<36>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<49>

MAKE_BASE=TRUEMEM_B_DQ<24>

MAKE_BASE=TRUEMEM_B_DQ<29>

MAKE_BASE=TRUEMEM_B_DQ<23>

MAKE_BASE=TRUEMEM_B_DQ<17>

MAKE_BASE=TRUEMEM_B_DQS_P<3>

MEM_B_DQ<22>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_B_DQ<21>

MEM_B_DQ<9>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_B_DQ<8>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_P<1> MAKE_BASE=TRUEMEM_B_DQS_N<1>

MAKE_BASE=TRUEMEM_B_DQ<5>

MAKE_BASE=TRUEMEM_B_DQ<4>

MEM_B_DQ<3>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_B_DQ<2>

MAKE_BASE=TRUEMEM_B_DQ<1>

MAKE_BASE=TRUEMEM_B_DQ<15>

MEM_B_DQ<12>

MAKE_BASE=TRUEMEM_B_DQ<11>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<26> MAKE_BASE=TRUEMEM_B_DQ<27> MAKE_BASE=TRUEMEM_B_DQ<28>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<6>

MAKE_BASE=TRUEMEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<7>

MAKE_BASE=TRUEMEM_A_DQ<17>

MAKE_BASE=TRUEMEM_B_DQ<19>

MEM_A_DQ<20>

MAKE_BASE=TRUEMEM_A_DQ<19>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<11>

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MAKE_BASE=TRUEMEM_B_DQ<39>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_B_DQ<38>

MEM_A_DQ<41>

MAKE_BASE=TRUEMAKE_BASE=TRUEMEM_A_DQ<42>

MAKE_BASE=TRUEMEM_A_DQ<61>

MAKE_BASE=TRUEMEM_A_DQ<63>

MAKE_BASE=TRUEMEM_A_DQ<56> MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQ<55>

MAKE_BASE=TRUEMEM_B_DQ<54>

MAKE_BASE=TRUEMEM_B_DQ<48>

MEM_B_DQ<62>

MAKE_BASE=TRUEMEM_A_DQ<62>

MAKE_BASE=TRUE =MEM_A_DQ<61>=MEM_A_DQ<58>

V+

NCNC

RESET*

A0A1

SCL

P0P1

P5P7P3

THRMVCC

GNDPAD

4 5

7 8

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Addr=0x98(WR)/0x99(RD) NOTE: CPU DAC output step sizes:

VRef DQ Driven by CPU

8.59mV / step @ output +61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A) 1.000V - 2.000V (+/- 500mV) 0.000V - 3.000V (0x00 - 0x74)

GPU Frame Buffer (1.8V, 70% VRef)

1.056V - 1.442V (+/- 180mV) +6.0mA - -5.0mA (- = sourced) 0.000V - 3.300V (0x00 - 0xFF) 1.267V (DAC: 0x8B)

1.51mV / step @ output 0.000V - 1.501V (0x00 - 0x74)

soft-resets and sleep/wake cycles.

a DAC output, cannot enable NOTE: MEMVREG and FRAMEBUF share RST* on ’platform reset’ so that system

watchdog will disable margining.

Addr=0x30(WR)/0x31(RD)

(OD)

NOTE: Margining will be disabled across all

both at the same time!

Nominal value

DDR3 (1.5V) 7.70mV per step

C3402

0.1UF20%

CERM402VREFMRGN:EXT

U3402

402OMIT

NONESHORT

1%

4021KMF-LF

R3442

PLACE_NEAR=R3441.2:4MM

1%

1/16WPLACE_NEAR=Q3420.6:64MM

402

R3421

MF-LF1K

PLACE_NEAR=Q3420.3:70MM

R3441

1/16W4021%

1K

VREFMRGN:EXT

MF-LF 402

402 1/16W

R3480

0

402 MF-LF

PLACE_NEAR=Q3420.3:70MM

X7R-CERM 0402

C3440

0.1UF

10%

X7R-CERM 0402

C3420

16V

0.1UF

0402 X7R-CERM

C3421

VREFMRGN:EXT

R3402

MF-LF4025%

100K1/16W

MF-LF

VREFMRGN:EXT

R3401

100K5%

1/16W

2 1

402CRITICAL

QFNPCA9557 U3401

50

50

40220%

C3401

0.1UF10VCERMVREFMRGN:EXT

6.3V402-LF20%

VREFMRGN:EXT2.2UF

C3400

40220%

C3403

CERM0.1UFVREFMRGN:EXT

SYNC_MASTER=D8_KOSECOFFDDR3/FRAMEBUF VREF MARGINING

PP3V3_S4_VREFMRGN_CTRLMIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmPP3V3_S4_VREFMRGN_DAC

34 OF 143

34 OF 117

21

C4C1

C3C2

A4A1

A3A2

2 1

2 1

2 1

1

215

3

5

12

67

121314

1011

8

354216

7

9

10

21

21

21

INOUT

OUT

OUTOUT

OUT

ININ

OE*

S

DP_1DM_1DM_2DP_2

OUT

NC

D

SG

G

S

DP-CH

N-CH

IN

VIN

ONVOUT

GND

VIN

ONVOUT

GND

IN

OUTENMR*

GNDTHRMIN

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SUPERVISOR & CLKREG # ISOLATION DELAY = 130 MS +/- 20%

514S0335

AIRPORT BLUETOOTH WI-FI POWER CONSUMPTION: RDAR://10174119

R3532

4021/16W

100K

1%

MF-LF1%

10UF

C3504

6.3V

MF-LF402

10K5%

R3570

SOD-VESM-HF

Q3570

SSM3K15FVCRITICALSIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

C3531

R3542402MF-LF5%

10K1/16W

4021/16W

FERR-220-OHM-2.5A0603

L3501

CRITICAL

X7R-CERM16V0.1UF

C3502

16V0.1UF0402

C3503

X7R-CERM0402

C3507

0.1UF16V

AIRPORT/BT

PP3V3_G3H_BT_FLT

MIN_LINE_WIDTH=0.5MMVOLTAGE=3.3V

NET_PHYSICAL_TYPE=POWER_PHY

PP3V3_S4_AP_FLT

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

MIN_NECK_WIDTH=0.2MMVOLTAGE=3.3V

PP3V3_G3H_BT_FET

BT_PWR_EN

MIN_LINE_WIDTH=0.6 mmVOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

35 OF 143

35 OF 117

211

18

21

1920

101112

13

161514

179

12345678

21

34

2176

123

1

2

21

1

2

6

12

C2

B1A1

A2B2

C2

B1A1

863

21

21

21

21

OUT

INININ

OUT

OUTOUT

OUT

INOUT

IN

OUT

OUTOUT

INININ

OUT

ININOUT

OUTOUT

OUTININ

OUTOUT

OUTOUT

BIBI

IN

INININOUT

OUTOUT

BIBI

IN

OUTOUTOUT

OUTOUTOUT

OUTOUT

PETN_3

PETN_2PETP_2

PETP_1PETN_1

PETP_0PETN_0

MONOBS_N

MONDC0MONDC1

PERN_3PERP_3

PERN_2PERP_2

PERN_1PERP_1

PERP_0PERN_0

MONOBS_P

TMU_CLK_INTMU_CLK_OUT

DPSRC_3_P

DPSRC_2_PDPSRC_3_N

DPSRC_1_PDPSRC_2_N

DPSRC_1_NDPSRC_0_P

DPSRC_AUX_PDPSRC_0_N

DPSRC_HPD_ODDPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_ODGPIO_6/CIO_SDA_ODGPIO_5/CIO_PLUG_EVENTGPIO_4/WAKE_N_ODGPIO_3

PB_CIO3_TX_N/DP_SRC_2_NPB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_NPB_CONFIG1/CIO_2_LSEOPB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_PPB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_NPB_DPSRC_1_NPB_DPSRC_1_PPB_LSRX/CIO_3_LSOE

PB_CIO3_RX_NPB_LSTX/CIO_3_LSEOPB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1GPIO_13/PB_DP_PWRDN/BYP2GPIO_1/PB_HV_EN/BYP0PB_DPSRC_HPDPB_AUX_NPB_AUX_P

THERMDA

EE_DIEE_DOEE_CS_N

TDIEE_CLK

TDO

DPSNK0_2_PDPSNK0_3_N

DPSNK0_1_PDPSNK0_2_N

DPSNK0_0_PDPSNK0_1_N

DPSNK0_AUX_PDPSNK0_0_N

DPSNK0_HPDDPSNK0_AUX_N

DPSNK1_3_NDPSNK1_3_P

DPSNK1_2_NDPSNK1_2_P

DPSNK1_1_NDPSNK1_1_P

DPSNK1_0_NDPSNK1_0_P

DPSNK1_AUX_NDPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_NPA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_NPA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOEPA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_NPA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_NPA_CIO1_RX_P

PA_LSRX/CIO_1_LSOEPA_LSTX/CIO_1_LSEO

PA_DPSRC_1_NPA_DPSRC_1_P

PA_DPSRC_3_NPA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPDPA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_PREFCLK_100_IN_N

XTAL_25_INXTAL_25_OUT

TMSTCK

TEST_ENTEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTNPERST_N

NCRBIAS

PCIE_RST_0_NPCIE_RST_1_N

PCIE_RST_3_NPCIE_RST_2_N

OUT

INBI

IN

DC

IN

OUT

OUT

OUTBI

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: The following pins require testpoints:

DEBUG: For monitoring clock

R3632100K

5%

1/16W 402 MF-LF

402 MF-LF 5%

5%

MF-LF

100K

402 1/16W

0

402 1/16W

R3693

3.3K

5%

402 MF-LF

C3629

16V 10%

C3627

16V 10%

X5R-CERM

C3626

10% 16V X5R-CERM

C3625

16V 10%

X5R-CERM

C3624

10% 16V X5R-CERM

C3623

16V 10%

X5R-CERM

C3622

10% 16V X5R-CERM

X5R-CERM

C3630

16V 10%

X5R-CERM

C3631

16V 10%

X5R-CERM

C3632

16V 10%

X5R-CERM

C3633

16V 10%

X5R-CERM

C3634

16V 10%

X5R-CERM

C3635

16V 10%

X5R-CERM

C3636

16V 10%

X5R-CERM

C3637

16V 10%

X5R-CERM

C3638

16V 10%

X5R-CERM

C3639

16V 10%

CRITICAL

R3697

100K

MF-LF 5%

402

OMIT

R3615NONE

NOSTUFF

NONE 402 NONE

R368810K

5%

1/16W 402

R368710K

5%

1/16W 402 MF-LF

R368610K

1/16W 402 MF-LF 5%

R368510K

5%

402 MF-LF

R368010K

5%

1/16W 402 MF-LF

R368210K

5%

1/16W 402 MF-LF

0.1UF

402 10%

R361047K

5%

1/16W 402 MF-LF

15

15 20 117

R368310K

5%

1/16W 402 MF-LF

R3681

402 1/16W 5%

10% 0201

C3602

16V X5R-CERM

0.1UFC3603

10% 16V X5R-CERM

R3692MF-LF 402 5%

3.3K

0.1UF X5R-CERM0201C3604

10% 16V X5R-CERM

C3605

16V 10%

X5R-CERM 10% 16V 0201 16V 10%

C3644

10% 16V X5R-CERM 0201

C3646

16V 10% X5R-CERM

C3647

0201 X5R-CERM 16V

TBT_GO2SX_BIDIR

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_P<3>

TBT_CIO_PLUG_EVENT_ISOLTBT_PWR_EN

TBT_SPI_CLK

=TBT_WAKE_LTP_DP_TBTSRC_AUXCH_CP

SYSCLK_CLK25M_TBTTBT_SPI_CS_L

DP_TBTSNK0_AUXCH_N

TP_DP_TBTSRC_ML_CN<3>

TBT_GPIO_9TBT_DDC_XBAR_EN_L

TBTROM_HOLD_LTBTROM_WP_L

TP_TBT_MONDC1

TBT_A_CONFIG1_BUF

TP_TBT_PCIE_RESET3_LPCIE_TBT_R2D_C_P<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

TBT_B_LSRXTBT_B_LSTX

TBT_RSENSE

DP_TBTSNK1_AUXCH_NDP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_AUXCH_NDP_TBTSNK0_AUXCH_P

TBT_B_CONFIG1_BUF

DP_TBTPA_HPDDP_TBTPA_AUXCH_C_PDP_TBTPA_ML_C_N<3>

TBT_B_DP_PWRDNTBT_A_DP_PWRDN

TBT_A_HV_ENTBT_B_HV_ENTBT_GPIO_14PCIE_CLK100M_TBT_P

TBT_TEST_ENTBT_TEST_PWR_GOODJTAG_TBT_TDO_ISOL

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

prefsb

051-9504 7.0.0

AD19

AD15 AD13

AD9 AD11

AD5 AD7

W16

AD23 AC24

AB19 AA18

AA16 AB15

AB13 AA12

AB9 AA10

W18

Y3 AA4

A14

A12 B15

A10 B13

B11 A8

C2 B9

V3 D3

Y1

V5

M5 T3 P3 AC2 AB1 AA2 J4 W2

U24 H5 N22 P1 R22

R24 N24

W24

B23 B21 A20 G6 U22 L6 W22

A22

L2 L4 M1 K3 E2 D1

Y7

R4 P5 AD3

V1 W4

R2

E16 D13

E18 D15

E20 D17

A6 D19

U6 B5

D5 E6

D7 E8

D9 E10

D11 E12

B3 A4

T5

E24 G24

E22 G22

G4 K1

J24 L24

J22 L22

J6 N2

B17 A16

B19 A18

F3

H1 F1

M3 G2

AB3 AA6

N4 AB5

E14

J2 R6

U4 W20

N6 T1

U2 Y5

2

9 4

5 6

2

1 3 7 8

2

1

2 1

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSS

VCC1P0_DPAUXVCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PE

VCC1P0_PEVCC1P0_PE

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PE

VCC1P0VCC1P0

VCC3P3_DPVCC3P3_DPVCC3P3_DPVCC3P3_CIOVCC3P3_CIOVCC3P3_CIOVCC3P3VCC3P3VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ON

VCC3P3

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VCC3P3_DPVCC3P3_DPAUX

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP current / power consumption figures from CR DG v0.57, IBL doc #472455

250 mW (Dual-Port)EDP: 240 mA

??? mW (Single-Port)

EDP: 10 mA

C37456.3V

1UF

X5R 0201 20%

C37166.3V

1UF

X5R 0201 20%

C37056.3V 20%

10UF

CERM-X5R 0402-1

C37736.3V

1UF

X5R 0201 20%

C37746.3V

1UF

X5R 0201 20%

C3717

1UF

6.3V X5R 0201 20%

C3713

1UF

6.3V X5R 0201 20%

C3700

10UF

6.3V20%

CERM-X5R 0402-1

C370120%

6.3V

10UF

CERM-X5R 0402-1

C37146.3V

1UF

X5R 0201 20%

C3715

1UF

6.3V X5R 0201 20%

10UF

6.3V CERM-X5R 0402-1

C37726.3V

1UF

X5R 0201 20%

C3771

1UF

6.3V X5R 0201 20%

C3710

1UF

6.3V X5R 0201 20%

C3770

1UF

6.3V X5R 0201 20%

C37906.3V

1UF

X5R 0201 20%

C37116.3V

1UF

X5R 0201 20%

C37126.3V

1UF

X5R 0201 20%

C3744

1UF

6.3V X5R 0201 20%

C3743

1UF

6.3V X5R 0201 20%

C3742

1UF

6.3V X5R 0201 20%

C37416.3V

1UF

X5R 0201 20%

C3740

1UF

6.3V X5R 0201 20%

SYNC_DATE=03/15/2012SYNC_MASTER=D7_MLB

37 OF 143

37 OF 117

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

C18 C20

C14 C16 C12 C10 B7 B1 AC8 AC6 AC4 AC22 AC18 AC20 AC16 AC14 AC12 AB7 AB17

AC10

AA8 AB11

AA14 AA20 AA22

A2 A24

U8 V9

U12 U16 T9

T13 T17 R8 R16 R12 P9 P17 P13 N16 N8

M9 N12 M17 L8 M13 L16 L12 K13 AD1

K9

H9 G8

K7

Y9

G10 G12 G14 G16

H19 G18

K19 M19 P19 T19 V15 V19 W12 W14

K11 K15

H13 H15 H11 R18 N18 L18 P7 M7 W10 V11 U10 T11 R14 R10 P15 N14 P11 N10 M15 M11 L14 L10

W8 T15

V7 U14 K17 J8 J16 J14 J12 J10

T7

C22 C24 C4 C6 C8 D21

E4 D23

F11 F13 F15 F17

F21 F19

F23 F5 F7

G20 F9

H21 H23 J18 J20 K21 K23 L20

M23 M21

N20 P21 P23 R20 T21 T23 U18

V17 V13

V21 V23 Y11 Y13 Y15 Y17 Y19

Y23 Y21

H17 H7

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

6 36 38 86 88

6

6

6 15 36 38 50

VOUT

ONVIN

OUTIN

IN

RESET*

OUTENMR*

GND THRM

IN

VDD

SENSE+

GND

VOUT

ONVIN

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM options provided by this page:

- =TBT_CLKREQ_L

Signal aliases required by this page:

- =PP1V05_TBT_FET (1.05V FET Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

DLY = 60 ms +/- 20%

1.05V TBT "CIO" Switch

Delay = 27.3msTPS3808G25

- =PPVIN_SW_TBTBST (8-13V Boost Input)

TBTBST:Y - Stuffs 15V boost circuitry

- =PP15V_TBT_REG (15V Boost Output)

Power aliases required by this page:

- =TBT_RESET_L

Page Notes

Intel investigating whether RC is sufficient

TBT "POC" Power-up Reset

Supervisor & CLKREQ# Isolation

Platform(PCIe) Reset

TPS22924C

18.5 mOhm TypLoad Switch

20.3 mOhm Typ28.6 mOhm MaxLoad SwitchTPS22924C

U3815

@ 1.0VR(on)

PartTypeMax Current = 2A (85C)

10%

6.3V 402

1UF5%

0

402MF-LFR3816

0.0047UF

25V

Q3825SOT563

MF-LF 402 5%

15

117

Q3840

VESMSSM3K15AMFVAPE

36

117

MF-LF 5%

402

10KR3840

1/16W

0402 X7R-CERM 10%

C3811

402

4021%

36.5K R38111/16W

Thunderbolt Power SupportSYNC_MASTER=D7_MLB SYNC_DATE=03/15/2012

TBT_SW_RESET_L

=PP1V05_TBTCIO_FETTBT_EN_LC_ISOL

38 OF 117

38 OF 143

7.0.0 051-9504

prefsb

A1 B1

C2 B2 A2

2 1

2 1

2 1

4

8 6 3

B1 C1

A1 B1

C2 B2 A2

2 1

2 1

6

1 2

21

BIBIBIBIBI

BI

BIBI

OUT

IN

IN

INOUT

CS*

SO

SPD100LED*/SERIAL_DOTRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_PTRD0_N

TRD1_N

TRD2_NTRD2_P

TRD3_NTRD3_P

PCIE_RXD_NPCIE_RXD_P

PCIE_REFCLK_NPCIE_REFCLK_P

CR_DATA0CR_DATA1

CR_DATA3CR_DATA2

CR_DATA4CR_DATA5CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECTTHRM_PAD

XTALIXTALORDAC

OUT

BI

BIBIIN

BI

BIBI

BIBI

SI

GNDVCC

IN

INOUT

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDD for Card Reader I/O

Special Star routing needed on these pins Decoupling on Pg 37

BCM57765 ENET SR pins are internal 1.2V switching regulator See note for SR_DISABLE below

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor

(IPx-ENET) (IPU-ENET)

Connect only to U3900 pin 20

No MS (Memory Stick) Insert feature needed

Control signal to light LED or control SD bus power

ENET supports both active-levels for WP

(OD)

IF ENET SWITCHING REGULATOR IS USED, THIS PIN SHOULD HAVE A 1K PD TO GND

(IPD-ENET)

SD_DETECT can only be used active low due to errata.

281mA (1000base-T max power, Caesar IV)

(OD) (OD)

(IPU-ENET) (OD)

o

PHY Non-Volatile Memory

NOTE: Pull-down on SO plus internal pull-ups on

=ENET_WAKE_L to PCIE_WAKE_L

info as well as code for Bonjour proxy

(Required ROM size 1 Mbit)Avoids need for EFI to program at startup

Internal 1.2V Switching Regulator pins

ROM contains MAC address, PCIe config

other 3 SPI pins configures ENET for the

ROM is used then the straps must change

NOTE: ENETM requires SI pull-down instead of SO

Atmel AT45DB011D (1Mbit) ROM If a different

NOTE: "IPx" == Programmable pull-up/down

the card reader on-chip I/O

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

(NO IPU OR IPD-ENET) (IPU-ENET) (IPU-ENET)

ENET_SR_DISABLE

ENET_CR SignalsBCM requests SD CR[0:7], CMD, CLK termination

If disabled: Okay to float VDD, VDDP & LX pin VFB must always connect to =PP1V2_S3_ENET_PHY

10UF

6.3VX5R

C3935

20%

4.7UF

X5R-CERM16.3V20%

4.7UF

X5R-CERM16.3V20%

SOIC-8S1

AT45DB011D OMIT_TABLE

33

C3905

0201X5R-CERM16V

0.1UF

16V0201

0.1UF

C3916

16V0201X5R-CERM10%

X5R-CERM0201

C3950

0.1UF

X5R-CERM020110%

0.1UF

C3951

020116VX5R-CERM10%

C3955

020110%

X5R-CERM

C3990

0.1UF

16V0201

PLACE_NEAR=U3900.21:5MM

2015% 1/20W MF

33

R3979

PLACE_NEAR=U3900.25:5MM

2011/20W

5% MF

33

R3971

PLACE_NEAR=U3900.24:5MM5% 1/20W MF 201

33

R3972

PLACE_NEAR=U3900.23:5MM5% 1/20W MF 201

33

R3973

PLACE_NEAR=U3900.22:5MM

2011/20W

PLACE_NEAR=U3900.53:5MM5%

R3976

1/20W MF

33

201PLACE_NEAR=U3900.54:5MM5% 201

0.1UF

10%

4021/16W0

6.3V0201

0201

C3913

10%

1.0UF6.3VX5R-CERM

C3930

402X5R-CERM120%

6.3V

R3997

4.7K

1/16W4025%

ETHERNET PHY (CAESAR IV+)

PCIE_ENET_D2R_C_P PCIE_ENET_R2D_N PCIE_CLK100M_ENET_N ENET_RESET_L ENET_CLKREQ_L_Q

ENET_SR_LX

ENET_CR_PWREN

PCIE_ENET_R2D_P ENET_VMAIN_PRSNT

ENET_CR_DATA<3>

ENET_SR_DISABLE ENET_CR_DATA<7>

=PP3V3_S4_ENET_FET

ENET_MOSI

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3VMIN_LINE_WIDTH=0.4 mmPP3V3_S4_ENET_FET_AVDDH

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.2V

PP1V2_S4_ENET_PHY_GPHYPLL

SDCONN_WP

SDCONN_CLK SDCONN_CMD

VOLTAGE=1.2VMIN_LINE_WIDTH=0.4 mm

PP1V2_S4_ENET_PHY_AVDDL

PP1V2_S4_ENET_PHY_PCIEPLL

VOLTAGE=1.2VMIN_LINE_WIDTH=0.4 mm

ENET_MEDIA_SENSE PP3V3R1V8_ENET_LR_OUT_REG VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

TP_ENET_CR_1V8_EN ENETCONN_MDI_P<0>

39 OF 143

prefsb

051-9504 7.0.0

39 OF 117

21

21

21

21

6365

267

40

4441

43

4746

4950

85

9

58

2728

3433

3031

11123

4

126212524

2223

525354

5955

60

68

181938

85

1

1 2

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

2

1

21

21

21

BIBI

BI

G

DS

IN

GD

SG

ENET_MDI_TRAN0-ENET_MDI_TRAN1-ENET_MDI_TRAN3+

4 5

7 8

REVISION

BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAESAR IV 1.2V INT.VR CMPTS

157S0058

SILKSCREEN:ENET ACT

CAESAR IV WAKE# ISOLATION

"ENET" = "S0" || ("S&& "WOL_EN")

CAESAR IV ACTIVITY LED

Power decoupling

3.3V ENET FET ENET Enable Generation

15

117

Q4021

2N7002DW-X-GCRITICAL

6.3VC4010402X5R-CERM1

MF-LF5%

402

R4070 10K1/16WQ4070

SSM3K15FV

SOD-VESM-HF

CRITICAL

R4050402MF-LF5%

330

DEVELOPMENT

2.0X1.25MM-SM GREEN-3.6MCD

20%

603

10UF6.3V

C4012

40 111

40 111

1/16W402

755%

MF-LF

R4003

4025%

MF-LF751/16W

R4002

755%

402MF-LF

R4001

4025%

1/16W

R4000

75

12061000PFCERM2KV

C4000

NOSTUFF

C4004

0.1UFCERM20%

4020.1UF40220%

CERM10V

C4003 C4002

10V40220%

0.1UFCERM402

0.1UF20%

CERM

C4001

X5R-CERM10%

0201X5R-CERM

C4017

16V

0.1UF

X5R-CERM16V020110%

0.1UF

C4018

X5R-CERM10%

40210K R40711/16WSOD-VESM-HF

0.1UF

C4023

020110%

X5R-CERM6.3V

20%

4.7UF

X5R-CERM1402

C4022

0402 X7R-CERM50V

6.3V

0402X7R-CERM16V0.1UF

MAKE_BASE=TRUE

ENET_WAKE_L

PP1V2_ENET_INTREG

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2MM

PP1V2_ENET_INTREG

VOLTAGE=1.2VMAKE_BASE=TRUE

40 OF 143

40 OF 117

3 2

1 2

3

5 4

21

21

21

1

21

21

21

2

21

21

21

21

21

21

21

21

21

21

21

789

1112

4321

10

65

789

1112

4321

21

21

21

12

438

9

21

1011121314

567

21

21