Lecture Digital logic design - Lecture 10: Circuit analysis procedure

The main contents of the chapter consist of the following: Hazards, glitches, important concept – analyze digital circuits, given a circuit, create a truth table, create a minimized circuit, approaches, boolean expression approach, truth table approach, leads to minimized hardware, provides insights on how to design hardware.

Lecture 10

Circuit Analysis Procedure

- Create a truth table

- Create a minimized circuit

° Approaches

• Boolean expression approach

• Truth table approach

° Leads to minimized hardware

° Provides insights on how to design hardware

Gate Delays

° When the input to a logic gate is changed, the

output will not change immediately.

° The switching elements within a gate take a finite

time to react to a change (transition) in input

° As a result the change in the gate output is delayed

w.r.t to the input change

° Such delay is called the propagation delay of the

logic gate (t p )

° The propagation delay for a 0 to 1 output change

(t pLH ) may be different than the delay for a 1 to 0

change (t pHL )

Important Terms (timing)

° Gate delay — time for change at input to cause

change at output

• min delay – typical/nominal delay – max

delay

• careful designers design for both worst case

and best case

° Rise time — time for output to transition from

low to high voltage

° Fall time — time for output to transition from

high to low voltage

° Pulse width — time that an output stays high or

stays low between changes

Effect of gate delays

° The analysis of combinational circuits ignoring

delays can predict only the steady-state behavior of

a circuits.

That is they predict a circuit’s output as a function

of its inputs under the assumption that the inputs have been stable for a long time, relative to the

delays into the circuit’s electronics.

° Because of circuit delays, the transient behavior of

a combinational logic circuit may differ from what

is predicted by a steady-state analysis.

° In particular a circuit’s output may produce a short

pulse (often called a glitch) at a time when steady state analysis predicts that the output should not change.

Hazards and Glitches

° A glitch is an unwanted pulse at the output of a

combinational logic network – a momentary change

in an output that should not have changed.

° A circuit with the potential for a glitch is said to

have a hazard.

° In other words a hazard is something intrinsic

about a circuit; a circuit with hazard may or may

not have a glitch depending on input patterns and the electric characteristics of the circuit.

When do circuits have hazards ?

° Hazards are potential unwanted transients that

occur in the output when different paths from input

to output have different propagation delays.

Circuit Analysis

 Analyze a logic circuit to determine its behavior.

 For a two-level circuit, the analysis

Relationship Among Representations

How do we convert from one to the other?

° Combinational circuit performs a specific

information-processing operation fully specified

logically by a set of Boolean functions

Sequential circuits

elements (binary cells) in addition to logic gates.

° Their outputs are a function of the inputs

and the state of the memory elements

• The state of memory elements, in turn, is a

function of previous inputs.

° As a consequence, the outputs of a

sequential circuit depend not only on

present inputs , but also on past inputs ,

• the circuit behavior must be specified by a time

sequence of inputs and internal states.

• In general, an AND-OR circuit

can have any number of AND

gates each with any number of

inputs.

A B C D

AB

CD

X=AB+CD

SOP

Basic Combinational Logic Circuits

° The logic gates accept signals from the inputs and

generate signals to the outputs

° This process transforms binary information from

the given input data to the required output data

• Obviously, both input and output data are represented by binary

signals,

° Combinational circuits outputs depend only on

current inputs (not on history).

° Kinds of combinational analysis:

• exhaustive (truth table)

• algebraic (expressions)

• simulation / test bench

- Write functional description in HDL

- Define test conditions / test vectors, including corner

° Sometimes you can write an equation or equations

directly using “logic” (the kind in your brain).

° Example (alarm circuit):

° Corresponding circuit:

The Problem

° How can we convert from a circuit drawing to an

equation or truth table?

° Two approaches

° Create intermediate equations

° Create intermediate truth tables

A B C

A B C’

Out

Label Gate Outputs

1 Label all gate outputs that are a function of input

variables.

2 Label gates that are a function of input variables

and previously labeled gates.

3 Repeat process until all outputs are labelled

By repeated substitution of previously defined

functions, obtain the output Boolean functions

A B C

A B C’

Out

R

Approach 1: Create Intermediate Equations

 Step 1: Create an equation for each gate output based

A B C’

Out

R

Approach 1: Substitute in subexpressions

 Step 2: Form a relationship based on input variables

A B C’

Out

R

Approach 1: Substitute in subexpressions

 Step 3: Expand equation to SOP final result

• Out = ABC + C’(A+B) = ABC + AC’ + BC’

A C’

Out

B C’

A B C

Approach 2: Truth Table

 Step 1: Determine outputs for functions of input

variables.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

R 0 0 0 0 0 0 0 1

S 0 0 1 1 1 1 1 1

A B C

A B C’

Out

R

Approach 2: Truth Table

 Step 2: Determine outputs for functions of

intermediate variables.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

R 0 0 0 0 0 0 0 1

S 0 0 1 1 1 1 1 1

T 0 0 1 0 1 0 1 0

C’

1 0 1 0 1 0 1 0 A

B C

A B C’

Out

R

Approach 2: Truth Table

 Step 3: Determine outputs for function.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

R 0 0 0 0 0 0 0 1

S 0 0 1 1 1 1 1 1

T 0 0 1 0 1 0 1 0

Out 0 0 1 0 1 0 1 1

A B C

A B C’

Out

R

Circuit Analysis More Difficult Example

 Note labels on interior nodes

 Multiple inputs (3) Multi-output (2)

To obtain FI as a function of A, B and C we form a series of substitutions as follows:

More Difficult Example: Truth Table

 Remember to determine intermediate variables

starting from the inputs.

 When all inputs determined for a gate, determine

output

 The truth table can be reduced using K-maps.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 2 0 0 0 1 0 1 1 1

F’ 2 1 1 1 0 1 0 0 0

T 1 0 1 1 1 1 1 1 1

T 2 0 0 0 0 0 0 0 1

T 3 0 1 1 0 1 0 0 0

F 1 0 1 1 0 1 0 0 1

1

0

° Important to be able to convert circuits into truth table

and equation form

• WHY? leads to minimized sum of product representation

° Two approaches illustrated

• Approach 1: Create an equation with circuit output dependent on

circuit inputs

• Approach 2: Create a truth table which shows relationship between

circuit inputs and circuit outputs

° Both results can then be minimized using K-maps.

° Next time: develop a minimized SOP representation

from a high level description