ĐIỆN tử VIỄN THÔNG 22functions v9 khotailieu

• Procedure arguments are similar to port declarations—they can be inputs, outputs, or bidirectional– Mode in can be read, but not changed; treated as constant – Mode out cannot be read,

Functions and Procedures

After completing this module, you will be able to:

Using Subprograms

be defined within a subprogram

– The subprogram can then be called as necessary throughout the design

– Provides flexibility and modularity to the code

– Reduces the volume of coding necessary in a large design

Functions versus

Procedures

– Their parameters (arguments) can only be inputs (not outputs or inouts)

– They must return a single result

– Their arguments can be inputs, outputs, or inouts

– They contain sequential statements that produce an effect

• A procedure can be declared with or without arguments

the design

procedure PROC1 is variable VAR1 ;

begin

(sequential statements .)

end procedure PROC1 ;

procedure PROC1 is variable VAR1 ;

Local Declarations

Procedure Structure

• Procedure arguments are similar to port declarations—they can be inputs, outputs, or bidirectional

– Mode in can be read, but not changed; treated as constant

– Mode out cannot be read, only assigned to; copied back to caller

– Mode inout can be read and assigned to; copied back to caller

• There are similar restrictions in terms of their usage within the procedure

Procedure Parameters

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ; OUT1: out <type> ; BI_DIR1: inout <type> ) is variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

Formal Parameters

Formal Parameters

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ;

BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ;

BI_DIR1: inout <type> ) is

actual parameters, which then map to the formal parameters

That is, PROC2 ( D_IN, D_OUT, D_IO );

Formal  Actual

Associating Parameters

the formal and actual parameters via “named” association

That is, PROC2 ( IN1 => D_IN, OUT1 => D_OUT, BI_DIR1 => D_IO );

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ; OUT1: out <type> ; BI_DIR1: inout <type> ) is variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

• In addition to mode and data type, the formal and actual parameters must also be of the same class

– Constant

– Variable

– Signal

– File

constant, variable, or signal declaration

Parameter Classes

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ; OUT1: out <type> ; BI_DIR1: inout <type> ) is variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

Default Parameter Class

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

• The most important consequence is that formal and actual must be

consistent Therefore, in the previous example, the actual object

associated with OUT1 or BI_DIR must be declared as a variable

That is, PROC2 ( IN1  D_IN, OUT1  D_OUT , BI_DIR1  D_IO );

Must be Variable

Default Parameter Class

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ;

OUT1: out <type> ; BI_DIR1: inout <type> ) is variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

end procedure BIT_REV_32 ;

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

for a 32-bit array

end package MY_PACK;

package body MY_PACK is

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector )is

begin

for i in 31 downto 0 loop

OUT_VEC(i) := IN_VEC(31- i);

end loop;

end procedure BIT_REV_32 ;

end package body MY_PACK;

library IEEE;

use IEEE.std_logic_1164.all;

package MY_PACK is

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector );

end package MY_PACK;

package body MY_PACK is

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector )is

begin

for i in 31 downto 0 loop

OUT_VEC(i) := IN_VEC(31- i);

end loop;

end procedure BIT_REV_32 ;

end package body MY_PACK;

Procedure Declaration

Procedure Declaration

Procedure Body

Procedure Body

Declaring the Procedure

declared within the separate and dependent package body

Calling the Procedure

Sequential Call

• Actually specifying the class of output parameters declared in the

subprogram is often helpful

– Can simplify usage and enhance the readability of the source code

– The difference in use is that you are not required to declare a variable

within the process so that it can be passed into the subprogram and then assigned to an output signal—as in the previous example

In this example, the keyword

signal before the parameter OUT1 declaration changes it

from a variable to a signal

class

Defining Output Parameters

procedure PROC2 ( IN1: in <type> ;

signal OUT1: out <type> ;

BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( IN1: in <type> ;

signal OUT1: out <type> ;

BI_DIR1: inout <type> ) is

Having declared the formal

parameter OUT1 as a signal,

you can pass the output port OUT_BUS (signal) directly

Call with Explicit Signal

Class

Sequential Call*

procedure PROC2 ( signal IN1: in <type> ;

OUT1: out <type> ;

BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

procedure PROC2 ( signal IN1: in <type> ;

OUT1: out <type> ;

BI_DIR1: inout <type> ) is

variable VAR2 ;

begin

(sequential statements .)

end procedure PROC2 ;

In this example, the keyword

signal before the parameter IN1 declaration changes it

from a constant to a signal

class

Explicit Input Parameter Class

subprogram is often helpful

– Can simplify usage and expand the capabilities of the subprogram

– The difference in use is that the actual signal is passed to the subprogram, rather than a “snapshot”—as in the case of the default constant This allows

VHDL signal attributes such as ’event to be applied

H_BYTE ‘left returns 7,

H_BYTE ‘right returns 0,

H_BYTE ‘low returns 0,

H_BYTE ‘range returns 7 downto 0,

WORD ‘left returns 0,

WORD ‘low returns 0,

WORD ‘length returns 4,

WORD ‘ascending returns true,

H-BYTE ‘reverse_range returns 0 to 7,

Range Attributes

attributes make subprograms more versatile and portable

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

procedure BIT_REV_32 ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

procedure to handle data of any length by using the VHDL range attributes

procedure BIT_REVERSE ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

end procedure BIT_REVERSE ;

procedure BIT_REVERSE ( IN_VEC : in std_logic_vector ;

OUT_VEC : out std_logic_vector ) is

procedure to handle data of any length by using the VHDL range attributes

function FUNC1 ( parameters ) return <type> is

<declarative region>

begin

(sequential statements .)

end function FUNC1 ;

Return Specification

architecture RTL of Mod1 is

.

function PAR_GEN ( BV: in bit_vector ) return bit is

variable PAR : bit := ‘0’;

begin - - function

for I in BV’range loop

PAR := PAR xor BV (I) ;

function PAR_GEN ( BV: in bit_vector ) return bit is

variable PAR : bit := ‘0’;

begin - - function

for I in BV’range loop

PAR := PAR xor BV (I) ;

the parity for a given bit_vector

What Logic is Created?

dependent on the length of the array

package std_logic_1164 is

function rising_edge ( signal CLK : std_logic ) return boolean;

end rising edge ;

.

Common Subprogram Usage

function

– Note the explicit signal designation for the formal parameter

package std_logic_unsigned is

function "+" (A,B: bit_vector) return bit_vector;

function ”+" (A,B: bit_vector) return integer;

function ”-" (A,B: bit_vector) return bit_vector;

function "-" (A,B: bit_vector) return integer;

example, bit_vector ; std_logic_vector)

these operations

• Because most intended operations are similar, VHDL allows the same call name to be used for multiple functions and procedures

parameters must be different

package array_arith is function "+" (A,B: bit_vector) return bit_vector;

function ”+" (A,B: bit_vector) return integer;

function ”-" (A,B: bit_vector) return bit_vector;

function "-" (A,B: bit_vector) return integer;

Overloading Subprograms

Using an Overloaded

Operator

compiler will automatically pass the parameters and return the result

– Otherwise, it will indicate that the operation is undefined

procedure BIT_SHIFT ( IN_VEC : in BIT_ARRAY ; signal OUT_VEC : out BIT_ARRAY ) is begin

for i in IN_VEC'range loop

OUT_VEC(i) <= IN_VEC(i) rol(i + 1 ) ; end if;

end procedure BIT_SHIFT ;

procedure BIT_SHIFT ( IN_VEC : in BIT_ARRAY ; signal OUT_VEC : out BIT_ARRAY ) is begin

for i in IN_VEC'range loop

OUT_VEC(i) <= IN_VEC(i) rol(i + 1 ) ; end if;

end loop;

end procedure BIT_SHIFT ;

Testbench Subprogram(1)

the data is originally stored within a multi-dimensional array

type BIT_ARRAY is array ( 0 to 7 ) of bit_vector ( 7 downto 0 ) ;

signal PIXEL_ARRAY : BIT_ARRAY := ( 0 => "00000001" ,

type BIT_ARRAY is array ( 0 to 7 ) of bit_vector ( 7 downto 0 ) ;

signal PIXEL_ARRAY : BIT_ARRAY := ( 0 => "00000001" ,

procedure BIT_SHIFT ( IN_VEC : in BIT_ARRAY ; signal OUT_VEC : out BIT_ARRAY ) is

variable TEST_BIT : bit ;

variable TEST_SLICE : bit_vector ( IN_VEC'range);

TEST_BIT := TEST_SLICE(TEST_SLICE'length-1) ; end if;

if ( TEST_BIT = '0’ ) then OUT_VEC(i) <= IN_VEC(i) rol(i + 1 ) ;

else OUT_VEC(i) <= IN_VEC(i) sra(i - 4 ) ; end if;

procedure BIT_SHIFT ( IN_VEC : in BIT_ARRAY ; signal OUT_VEC : out BIT_ARRAY ) is

variable TEST_BIT : bit ;

variable TEST_SLICE : bit_vector ( IN_VEC'range);

TEST_BIT := TEST_SLICE(TEST_SLICE'length-1) ; end if;

if ( TEST_BIT = '0’ ) then OUT_VEC(i) <= IN_VEC(i) rol(i + 1 ) ;

else OUT_VEC(i) <= IN_VEC(i) sra(i - 4 ) ; end if;

Testbench Subprogram(2)

and uses that result in a conditional expression

procedure COMPARE_SIG ( signal ACTUAL , EXPECTED in : std_logic ) is

begin

loop

wait until rising_edge ( SIM_CLK ) ;

assert ACTUAL = EXPECTED

report "ERROR: SIMULATION OUTPUT is INCORRECT"

severity warning ;

end loop;

end procedure COMPARE_SIG ;

procedure COMPARE_SIG ( signal ACTUAL , EXPECTED in : std_logic ) is

begin

loop

wait until rising_edge ( SIM_CLK ) ;

assert ACTUAL = EXPECTED

report "ERROR: SIMULATION OUTPUT is INCORRECT"

• Group exercise: Write a function to convert the following std_logic_vector to

0

Knowledge Check

1 1 0 1 0 0 1 0

function VEC2INT ( VEC : in std_logic_vector) return integer is

variable RESULT : integer := 0 ;

architecture TEST of VECT2INT_TB is

function VEC2INT - - declare subprogram signal IN_VEC : std_logic_vector ( 7 downto 0) := “01101001” ; signal OUTPUT : integer range 0 to 255 ;

.

begin

operations

functions