DSpace at VNU: Eliminated Common-Mode Voltage Pulsewidth Modulation to Reduce Output Current Ripple for Multilevel Inver...
Trang 1Abstract— The paper presents an analysis on the output
current-ripple in zero Common Mode Voltage (ZCMV) PWM
control of multilevel inverters The modulation strategy for
Common Mode Voltage (CMV) elimination in multilevel
inverters is based on the “three zero common mode vectors”
principle The space vector diagram, which consists of vectors of
zero common mode voltage, is fully explored by properly
depicting the base voltage vectors and their corresponding active
switching vectors The switching patterns are limited to those of
three switching states each of which is symmetrically distributed
Based on the PWM process simplified to that of a two-level
inverter with three allowable switching states and the degree of
freedom existing in the switching states arrangement, a novel
carrier-based PWM method with optimized output current
ripple is proposed Compared to the existing PWM methods
which utilize the same kind of switching patterns, the proposed
PWM method has reduced considerably the RMS current ripple
and total harmonic distortion (THD) of the output-current in a
wide region of the modulation index The effectiveness of the
proposed method is validated by both simulation and
experimental results
voltage, Current-ripple, Harmonic distortion, Pulse Width
Modulation (PWM), PWM inverters.
ommon-mode voltages are associated with excessive
bearing currents, which may cause premature motor
bearing failure and electromagnetic interference [1-2]
There are a number of approaches to cope with the CMV
issue, including the use of extra hardware with passive and/or
active devices [3-4] However, the extra hardware causes a
significant increase in the system’s volume or creates much
more complex methods of control
The multi-level inverters [5-6], as shown in Fig.1, have a
high number of switching states that can either reduce or
eliminate the CMV Based on this advantage, many studies of
CMV mitigation have been conducted using multi-level
inverters [7-17] The PWM methods with partial CMV
elimination are presented in [7-10] while PWM methods with
Tam.-K.T Nguyen and Nho.-V Nguyen are with the Department of
Electrical Engineering, Ho Chi Minh city University of Technology, Ho Chi
Minh City, Viet Nam (e-mail: nkttam@hcmut.edu.vn; nvnho@hcmut.edu.vn)
Nadipuram (Ram) R Prasad is with the Klipsch Scool of Electrical and
Computer Engineering, New Mexico State University, Las Cruces, NM,
88003-8001, USA (e-mail: ramprasad@msn.com)
complete CMV elimination can be found in [11-17]
In previously reported works [11-12], the ZCMV PWM is applied to a three-level Neutral Point Clamped (NPC) Inverter
In [13], the PWM strategies for CMV reduction/elimination are developed for a five-level NPC inverter Work reported in [14] proposes PWM strategies for partial and complete CMV elimination in cascaded multilevel inverters However, the degree of freedom in the switching states arrangement is not investigated in the mentioned works In [16], a PWM strategy that utilizes one nearest vector of ZCMV with respect to the desired output voltage vector during one carrier cycle is presented The method, however, is suitable for a high number of inverter levels at which the existing voltage error can be ignored A solution for ZCMV PWM in multilevel that takes into account the degree of freedom in the switching sequence arrangement is recently reported in [17] The work has proposed a simple carrier based PWM method for
Eliminated Common-Mode Voltage Pulsewidth
Modulation to Reduce Output Current Ripple
for Multilevel Inverters
Tam-Khanh Tu Nguyen, Nho-Van Nguyen, Member, IEEE, and Nadipuram (Ram) R Prasad, Member, IEEE
C
dc
V
A
O
A
SW1
A
g
B
C N
g
dc
V
a) dc
V
A
A
SW1
A
SW2
A
SW3
A
SW4
dc
V
dc
V
B
dc
V
dc
V
C
N O
AC motor
g
g
dc
V
b) Fig 1 Multilevel Inverter system: a) three-level NPC inverter; b) five-level cascaded inverter
Trang 2multilevel inverter using the three ZCMV vectors principle
The resultant switching patterns are limited to those of a
minimum number of switching states, which helps to globally
reduce the switching loss By using a proposed current-based
mapping technique, the switching loss can be locally reduced
up to 25% as compared to the non-optimized algorithms
The current ripple reduction is significant in practice
Reducing the current ripple can result in a lower torque
pulsation of motor drive [24-25], reduction in motor acoustic
noise [27], and also a reduction in motor heating The PWM
techniques for a reduced current ripple are specifically useful
for high power applications, where the switching frequency is
quite low [25],[39] For these reasons, the current ripple has
been the subject of extensive research for decades [18-39]
The current ripple analysis of a two-level inverter can be
found in many works [18-33] The work reported in [18]
analyzed the impact of zero space vector distribution on the
output current ripple In [19], the switching sequence
arrangement of the space vector PWM (SVPWM) is
considered for the purpose of reducing the output current
ripple It has been shown in [20-21] that the discontinuous
PWM strategy (DPWM) can be properly applied so that the
output current ripple is reduced compared to PWM methods
with the same average switching frequency In the work [24],
the geometrical analysis of the current ripple vector
corresponding to a conventional SVPWM pattern is presented
and the CMV is utilized as a degree of freedom to minimize
the RMS output-current The latter works [25-27] proposed a
more generalized method of output current ripple analysis
The switching patterns can be extended for division of active
vector time [25],[27] and an effective hybrid PWM technique
which combines multiple switching sequences to reduce the
current ripple is further suggested [26] Recently, the output
current ripple analysis and optimized control methods have
been developed for the multi-phase two-level systems [28-31]
Also, current ripple analysis in term of the peak-to-peak value
has been reported in the works [32-33]
The current ripple analysis is further extended to high level
inverters as can be found in [33-37] The works [36-37]
present investigations on the current ripple for the three-level
operation based on dual two-level VSI The DPWM method is
also employed in [37] to reduce the switching loss as well as
the current ripple The work [34] introduces novel switching
sequences of the three-level NPC inverter with corresponding
current ripple investigations Based on [34], a hybrid PWM
technique [35] is proposed that helps reduce the current ripple
In ZCMV PWM control, greater distances between the three
active vectors lead to increased current ripple and higher THD
compared to the conventional PWM control [12],[22]
Although the ZCMV PWM for multilevel inverters has been
the main subject of many aforementioned works [12-17], no
study has considered the ZCMV PWM technique for current
ripple reduction thus far The Switching loss optimizing PWM
[17] that considers using the degree of freedom in the
switching states arrangement, however, results in higher
output current ripple than other PWMs with non-optimized
algorithms
In this paper, an output current ripple analysis of multi-level inverters under condition of ZCMV is presented The designed switching patterns satisfy the “three ZCMV vectors” principle with a minimum number of commutations The current ripple is theoretically investigated using the notion of harmonic flux Based on the degree of freedom in the switching states arrangement, a PWM strategy is proposed to optimize output current ripple The rules to select the optimum switching sequence deduced from the current ripple analysis are simple for an online implementation Also, the proposed PWM method can be simply applied to a high level inverter without losing the generality
The proposed ZCMV PWM method is developed and simulated for the three-level NPC inverter and the five-level cascaded inverter The harmonic flux characteristics obtained from simulated data of the proposed ZCMV PWM method and existing ZCMV PWM methods characterized by the same kind of patterns in [17] are presented to highlight the improved performance of the RMS current ripple Also, comparisons of the weighted total harmonic distortion (WTHD) factor characteristics of the line voltage are shown to demonstrate the improved THD of the proposed PWM method In experiment, the proposed PWM method is verified
on a five-level cascaded inverter fed constant volt-per-hertz (V/f) drive Comparative results of the RMS current ripple characteristics as well as the current THD characteristics are shown for experimental validation
VOLTAGE The ZCMV PWM in multi-level inverters has been analyzed in detail in the previous work [17] For the sake of clarity of the proposed PWM method development, the analytical method is briefly summarized in this section
In the systems of multi-level inverter fed AC motor drive as described in Fig 1, the CMV is defined as the voltage difference between the stator winding neutral N and the mid-point O of the DC-link [13] The CMV in Fig 1 can also be expressed in terms of the pole voltages (each of which measured from one output terminal to the mid-point O of the DC-link voltage) as:
CO BO AO NO CM
V V V V
The condition of ZCMV defines the space vector diagram
of a five-level inverter with 19 switching combinations of (VAO, VBO, VCO) of ZCMV as shown in Fig 2
Assume that each DC-link voltage defined as
dc
V in Fig 1 is ideal DC voltage For a three phase n-level inverter, the modulation index can be defined as:
d c
V n
v m
3 1
1
(2) wherev1is the peak value of the fundamental component of the actual phase voltage and (n1)V dc/ 3is the maximum
Trang 3peak value of the fundamental voltage in linear control that the
inverter can produce In linear modulation of ZCMV PWMs
control, the maximum value of the modulation index defined
by (2) is 0.866 [12-17]
The analytical process for the diode-clamped inverter and
cascaded inverter is unified by a simple voltage modeling For
an n-level inverter of the two topologies, the pole-voltage
) , , (X A B C
dc dc
n
j jX
V
2
1 )
(
1
1
(3)
C , B , A X
; s s
s
s1X 2X n2X n1X (for the diode
clamp inverter topology ) (4)
where s1X, s3X,…, sn-1X represent the switching states of
switches SW1X , SW2X ,…, SWn-1X which, for example, are
designated in Fig 1 for the A-phase of the two topologies; s1X
is 1 if SW1X is on, otherwise its value is 0
1
1
C B A X s
n
j
in (3) is called the
normalized switching voltage which is denoted asVXn:
) , , (
1
1
C B A X s V
n
j jX
(5)
Xn
V can be decomposed into two components L X ands X:
X X
V (6) whereL Xis a constant integer value that represents the base
component of VXn and s Xis the active component of VXn,
which value can be 0 or 1
The average value of
Xn
V can be expressed in terms of X- the average active component of s X in a carrier cycle as:
) 1 1
, 1 0
(
The value of the base voltage and the active voltage can be
deduced as follow:
n v if n
n v if v Int
Xn
Xn Xn
1 2
1 )
(
(8)
X v XnL X;XA,B,C (9) where,Int(v Xn) denotes a function that returns a nearest lower
integer value ofv Xn The condition of zero average CMV leads to:
FF LF e3(n1)/2 (10)
where,F L L AL BL C and F eABC The functionsF,F L,F eare termed the total switching
voltage, total base voltage, and total active voltage, respectively The values of F L and F e which are available for ZCMV PWM control, are limited to two specific cases as:
-The case of F L 3(n1)/22,F e2, which is realized with three active switching states of (1,1,0), (0,1,1), and (1,0,1) in the active voltage hexagonal diagram as shown in Fig 3(a)
- The case of F L 3(n1)/21,F e 1, which is realized with three active switching states of (1,0,0), (0,1,0), and (0,0,1) in the active voltage hexagonal diagram as shown in Fig 3(b)
In the space vector diagram with ZCMV of a five-level inverter as shown in Fig 2, considers for example the case when the tip of the reference voltage vector is enclosed by the medium triangle defined by tips of three vectors corresponding to normalized switching states of (3,2,1),(4,1,1),(4,2,0) The normalized state of the base voltage vector is determined as (L A,L B,L C)= (3,1,0) which yields
4
L
F , and the medium triangle active voltage vector diagram
is of the case in Fig 3(a) Using similar analysis, total 24 equilateral triangles defined by sets of three zero common mode vectors are obtained in Fig 2: twelve triangles meet the condition F L F L14(Fig 3(a)) and confine the light area;
the others satisfy F L F L15(Fig 3(b)) and cover the shaded area
140 340 440
041 130 230 430
031 131 220 320
043 032 121 221 310 410
044 022 122 211 311 400
034 023 112 212 301 401
013 113 202 302
014 103 203 403
104 304 404
240
231
204
axis
axis
a axis
040
b axis
004
c axis
Normalized switching state
of zero CMV
Normalized state
of the base voltage vector
Fig 2 Five-level space vector diagram with zero CMV states (bold letters)
110
101 011
010
100
001
110 010
100 011
101 001
L
F 3(n 1) / 2 2 e FL 3(n 1) / 2 1
the area meets the condition of F =2 the area meets the condition of F =1e
Medium
Fig 3 Medium triangle active voltage vector diagrams: a) active switching states for F e 2 (F L 3 (n 1 / 2 2 ); b) active switching states forF e 1 (F L 3 (n 1 / 2 1 )
Trang 4The PWM switching state sequence of the active voltage
vectors in the ZCMV PWM control can be then grouped into
two PWM patterns related to the total active voltage F e as
shown in Fig 4 For three-phase outputs with the use of the
two Patterns in Fig 4, Table I lists six possible mapping
functions Different mapping functions result in different
three-phase active switching sequences
Since a commutation of the d-sequence in Fig 4 happens
simultaneously with one from both sequences s1ands2, it is
sufficient to use two modulating voltages s1,s2 to deduce
the switching time diagram of the proposed PWM method
The modulating voltages 1,2 are determined based on the
mapping function as presented in Table I The switching time
diagram can be derived accordingly by comparing
2
1,1
with a unit carrier as in Fig 4 The duty cycles can be
obtained as follows:
) 11 (
3 1 2
1 3
2 1
I Pattern for T T T T
T T
T T
s
s s
s s
)
1 (
3 1 2
2 3
1 1
II Pattern for T T T T
T T
T T
s
s s
s s
voltages, the proposed ZCMV PWM method is described as in
Fig 5
A Simplification of output current ripple analysis in multilevel inverter with ZCMV PWM control
The approximate current ripples expression in the Nth carrier cycle can be described as follows [22]:
L i
S N
S NT
X XN
where,V XN (X A,B,C) is the output phase voltage measured from an output terminal to the load neutral N
voltageV XN(XA,B,C)is identical to the pole voltageV XOand
) , , (
*
C B A X
v X is equal to the average value ofV XO which is denoted asv XO Equation (13) is further derived as:
C B A X L dt v V L
S N
S NT
XO XO
The component Xin (14) is called the X-phase harmonic flux
in the Nth carrier cycle
Based on (3)-(7) as previously analyzed in Section
II,V XOandv XOboth consist of the same constant voltage component(L X(n1)/2)V dc during a carrier cycle The X-phase harmonic flux can be then expressed in terms of the instantaneous active switching voltage V d c s X and average active switching voltage V d c.Xas follows:
S N
S NT
X X dc
) 1 (
, ,
; )
Eq (15) shows that the output-currents ripple analysis of a multilevel inverter under condition of ZCMV can be simplified to that of a two level inverter
1
s s d
e
2
1 s 1
s s d
e
1
s
2
s
d
0
0
1
T 2
2
T
T T 2
2
1
T 2
1
T 2
2
T
T T 2
2
1
T 2
2
1 s
1
s
2
s
d
Fig 4 Two Standardized virtual PWM patterns from the three zero common
mode vectors
TABLE I POSSIBLE MAPPING FUNCTIONS AND MODULATING SIGNALS
DETERMINATION
1 2
2 1
1
2
2
1
1 2
2 1
s1 B
s2 C
s1 C
s2 B
s1 A
s2 C
s1 C
s2 A
s1 A
s2 B
s1 B
s2 A
s ,s ,s
Select Pattern I
n
Select Pattern II
Active switching states and time diagram Selected Mapping
function
Pulse Generator
* 1 2
X Xn dc
v V
*
X
v (X A, B, C)
1
e
F
e
F 2
L int(v )
X v Xn L X
F
y
Fig 5 Block diagram of the proposed PWM method to eliminate common-mode voltage
Trang 5Eq (15) can also be expressed in another form as:
S N
S NT
X X dcN
n
V ( 1)
, ,
; ) (
where,V dcN(n1)V dc
It should be noted that inverters of equal maximum linear
output voltage yield the same value ofV d cN Based on the
normalized (withV d cN) value of Xin (16), comparative results
of harmonic fluxes given by topologies of different levels are
obtained
B Proposed PWM strategy for reduced RMS output current
ripple
Considering the generalized PWM patterns described in
Fig 4, four types of active switching voltage waveform with
their corresponding harmonic fluxes can be classified as in
Fig 6 For both cases of the generalized switching pattern in
Fig 4, the active switching voltage waveform corresponding
to the output phase which is mapped to the s1sequence is
shown in Fig 6(a)
Since the switching frequency is much higher than the
reference, the average switching voltages during one carrier
cycle can be assumed to be constants Solving (16), the
normalized (withV dcN.T s) harmonic fluxes corresponding to
thes1,s2sequences are described, respectively, as:
4 ) 1 ( 3 ) 1 ( 4 ) 1 ( 1
3 ) 1 ( 1 ) 1 ( 2 ) 1 ( 1
1 ) 1 ( 0 ) 1 ( 0 ) 1 ( 1 1
);
.(
);
).(
1 (
);
).(
( ) 1 ( 1
s s
s s
s s
s
s s
s s
S n
s
t t t t t
t t t t t
t t t t
t T
n
4 ) 2 ( 3 ) 2 ( 4 ) 2 ( 2
3 ) 2 ( 1 ) 2 ( 2 ) 1 ( 2
1 ) 2 ( 0 ) 2 ( 0 ) 2 ( 2 2
);
).(
1 (
);
).(
(
);
).(
1 ( ) 1 ( 1
s s
s s
s s
s
s s
s s
S n
s
t t t t t
t t t t t
t t t t t T
n
The normalized harmonic flux of the phase of double switching is described as follows:
) 19 (
);
).(
(
);
).(
1 ( ) ).(
(
);
).(
(
);
).(
1 ( ) ).(
(
);
).(
(
) 1 ( 1
6 ) 5 ) 6
)
5 ) 4 ) 4 ) 3
) 4 )
4 ) 2 ) 3
)
2 ) 1 ) 1 ) 0
) 1 )
1 ) 0 ) 0
)
d d d
d
d d
d d d
d d
d d
d d
d d d d d
d d
d d d
d
S dn
t t t t
t
t t t t t t
t
t t t t
t
t t t t t t
t
t t t t
t
T n
for pattern I, and:
) 20 (
);
).(
1 (
);
).(
( ) ).(
1 (
);
).(
1 (
);
).(
( ) ).(
1 (
);
).(
1 (
) 1 ( 1
6 ) 5 ) 6
)
5 ) 4 ) 4 ) 3
) 4 )
4 ) 2 ) 3
)
2 ) 1 ) 1 ) 0
) 1 )
1 ) 0 ) 0
)
d d d
d
d d d d d d d
d d d
d
d d d d d d d
d d d
d
S dn
t t t t
t
t t t t t t
t
t t t t
t
t t t t t t
t
t t t t
t
T n
for pattern II
The mean-square values of the harmonic fluxes (over one carrier cycle) corresponding to thes1,s2,dsequences are determined as:
S s t
s t n s S rms n
T
0 ) 1 (
0 ) 1 (
2 1 2
1
(21)
S s t
s t n s S rms n
T
0 ) 2 (
0 ) 2 (
2 2 2
2
(22)
S d t
d t
d n S rms
T
0 )
0 )
2
(23)
Using (21)-(22) withs1 n,s 2 nexpressed in (17)-(18) , and Fig 4 taken into account, 2
1n rms
s
2n rms
s
can be obtained as:
2 1
2 1 2
2
) 1 ( 12
1
s s rms
n s
(24)
2 2
2 2 2
2
) 1 ( 12
1
s s rms
n s
Similarly, the value of 2dnrms for pattern I and pattern II can
be determined, respectively, by substituting d ndeduced from (19) and (20) into (23) The simple form of 2
rms
d n
is finally
obtained as:
) (
) 1 ( 12
1
2 1 2 2 2 1 2 2 2
s s s s d rms
dn
))
1 ).(
1 ( ) 1 ( ) 1 ((
) 1 (
) 1 ( 12
1
2 1 2 2 2
1 2 2
2
s s s
s d
rms dn
for Pattern II (27)
(s1)0
t t(s1)1 t(s1)2 t(s1)3 t(s1)4
dc
V
0 0
a)
(s2)0
t t(s2)1 t(s2)2 t(s2)3 t(s2)4
0
dc
V
dc
V
b)
dc
V
0
(d)0
t t (d)1 t (d)2 t (d)3 t (d)4 t (d)5 t (d)6
c)
dc
V
0
dc
V
0
dc
(d)0
t t(d)1t(d)2 t(d)3 t(d)4t(d)5t(d)6
d)
Fig 6 Harmonic flux trajectories corresponding to phase of a) s 1 - sequence
b) s 2 - sequence c) d -sequence (Pattern I) and d) d -sequence (Pattern II)
Trang 6
The mean-squared normalized harmonic flux of X phase
(X=A,B,C) is defined as follows:
C B A X d X if
s X if
s X if F
rms
d n
rms n s
rms n s
2
2 2
2
1 2
1
(28)
The total mean-squared normalized harmonic flux of three
phases (over one carrier cycle) is expressed based on (28) as:
C B
F
F (29)
The problem of output current ripple minimization can be
solved by finding an available three-phase switching sequence
that is corresponding to the minimum value of the function
F in (29) in each carrier cycle As described in Table I, there
are six possible mapping functions that decide the three-phase
switching sequence However, it can be concluded from (24)
2 2
1n rms s n rms
s
where the role of sequencess1,s2are altered Therefore, the
RMS current ripple can be minimized by selecting a phase of
double pulses switching so that the resulting F is at a
minimum
We defineF(Ad),F(Bd)and F(Cd)the values ofF
corresponding to three cases ofAd,BdandCd,
respectively By using (24)-(29) and Table I, the values of
C B A X
F(Xd), , , for Pattern I are obtained as:
)) (
) 1 (
) 1 (
( ) 1 ( 12
2 )
n
F
(30)
)) (
) 1 (
) 1 (
( ) 1 ( 12
2 )
n
(31)
)) (
) 1 (
) 1 (
( ) 1 ( 12
2 )
n
F
(32)
The mapping rule (Ad) is selected when the value of
)
(A d
F satisfies:
C B A X F
F(Ad)min( (Xd)); , ,
(33)
By mean of (30)-(32), solving (33) leads to the following
conditions:
0 ) ) (
2 3 ).(
(
0 ) ) (
2 3 ).(
(
C A C A C
A
B A B A B
A
(34)
Since0X(XA,B,C)1andABC 1for Pattern I,
the components(32.(AB)A.B) and
) ) (
2 3 ( AC AC in (34) are always be negative As a result, the conditions expressed in (34) are further reduced to the simplest form as:
) , ,
(35) For the pattern II, the condition expressed in (33) leads to:
) , ,
(36)
Similarly, the conditions of using the mapping rules (Bd) ,(Cd) are derived, respectively, as:
II Pattern for Min
I Pattern for Max
C B A B
C B A B
) , , (
) , , (
(37)
II Pattern for Min
I Pattern for Max
C B A C
C B A C
) , , (
) , , (
(38)
The conditions expressed in (35)-(38) divide the two medium triangles in Fig 3 into three separate regions each of which is designed with a different mapping function As previously described in (16), the ripple analysis of the PWM method using three nearest ZCMV vectors can be simplified to the ripple analysis of a two-level inverter defined by the two medium triangles in Fig 3 Thus, the mapping algorithm designed for the whole vector diagram of the multilevel inverter can be derived based on Fig 7 For example, the space vector diagram with the proposed mapping technique for minimizing the output current ripple of a five-level inverter
is shown in Fig 8 It should be noted that each separate region
in the medium triangle defines the phase of double pulse distribution and the two other phases each of which can be set arbitrarily to the s1 or s2 sequence If one mapping rule in Table I is utilized during active time of one region, there is no additional commutations between two subsequent carrier cycles However, at the transition between two separate regions when the phase of double pulse is changed, additional commutations may arise The s1 or s2 sequence design is then constrained to the condition of minimized additional commutations caused by region transitions
110
101 011
010
100
110 010
100 011
101 001 001
A
B
C
B
A
C
L
F 3(n 1) / 2 2 FL 3(n 1) / 2 1
Fig 7 Proposed double pulse mapping regions for reducing output current ripple for a) Pattern I, and b) Pattern II
Trang 7
Based on (35)-(38) and Figs.7 and 8, a simple mapping
algorithm for ZCMV PWM with minimized output current
ripple is proposed as shown in Fig 9 The flow diagram in
Fig 9(a) is utilized to determine the active regions of the
medium triangles in Fig 7 Figure 9(b) specifically describes
the control algorithm to minimize the additional commutations
at the instant of transition to the new active region of
(Ad) The design of the s1 and s2 sequence is based on
information of the current normalized state of the three-phase
active voltages (sA,sB,sC) and phase of double pulses in the old
region The rule is set as (Bs2,Cs1) and
(Bs1,Cs2) when the active voltages are (sB=1, sC=0)
and ( sB=0, sC=1), respectively; in this case, no additional
commutations are required However, when the active
voltages are (sB=0, sC=0) or ( sB=1, sC=1), an additional
commutation is required regardless of the s1 and s2 sequence
design; in this case, the phase of double pulse in the previous
region is selected for non-commutation in order to distribute
the switching stress between the two phases In cases with the
transitions to the new regions ofBdandCd, s1,s2
sequences are designed in a similar way as for the case of
transition to the new regionAd
The proposed ZCMV PWM scheme with reduced output
current ripple is obtained by utilizing mapping results in Fig 9
as inputs to the block diagram of ZCMV PWM in Fig 5 The
online algorithm is simple and can be implemented on a
real-time microprocessor with small computational burden The
maximum computations needed for implementation of the
proposed algorithm are 3 multiplications, 4 additions, 3
subtractions, 3 int() operations and 16 comparisons The
measured execution time of the algorithm implemented on a
DSP28335 processor is less than 10 s
C Normalized harmonic flux evaluation
In theoretical analysis, the normalized harmonic flux over the full fundamental cycle (of A-phase, for example) is evaluated as follows:
0
) ( 2
d
F A
rmsF
An (39)
where,2o t, f o is the output fundamental frequency
The functionF A()in (39) is calculated using (28) It can be seen thatF A()is dependent on the mapping algorithm of each PWM method For the proposed ZCMV PWM method, the designed mapping algorithm is determined as in Fig 9
The normalized harmonic flux in (39) is evaluated over the entire range of the modulation index for the proposed PWM method and two existing PWM methods that are based on the same standardized patterns [17] These two existing ZCMV PWM methods include the Switching loss optimizing PWM (SLO PWM) and the Voltage-Based Mapping PWM (VBM PWM) It has been shown in [17] that characteristic of the SLO PWM corresponding to0is identical to one obtained
by the VBM PWM In this paper, comparative results of the evaluated normalized harmonic flux with those PWM methods would be shown to highlight the improved performance of the proposed PWM in RMS current ripple reduction
320
400
axis
axis
a axis
b axis
c axis
311
312
420
310 410
321
411
301 401
302 402
403
303
404 304
211
222
430 220
221
230
231
240
330
212
202
203
213
204
130
140 340 440 040
041 141
043 032 132 121
122 022
033
044
034 023 123 112
113 013
024
014 114 103
104 004
Fig 8 Illustration of the proposed double pulse mapping algorithm applied
to the whole space vector diagram the five-level inverter
(A, B,C)
MNMin
yes
no yes
no
B MX
Ad
Bd
Cd
A MX
yes
no yes
no
B MN
Ad
Bd
Cd
A MN
(A,B,C)
MXMax
1
A B C
no
yes
Pattern II
, ,
A B C
Pattern I
a) determination of phase of double pulses
( )
new zone A d
0
B
s
no
no yes
Bs Cs
:
old zone Bd no yes
Bs Cs
yes
no yes
Bs Cs
:
old zone Bd no yes
Bs Cs
0
C
b) s 1 and s 2 sequence design in case the transition to new zone
of (Ad) Fig 9 Block diagram of the proposed mapping algorithm for reduced RMS current ripple
Trang 8For a given n-level inverter, the normalized harmonic flux
with the proposed PWM method is only dependent on the
modulation index m, while one with the SLO PWM is
dependent on both m and.The characteristics of the
normalized RMS harmonic flux with SLO PWM method,
corresponding to the three-level inverter and the five-level
inverter, are illustrated in Fig 10 (a) and Fig 10(b),
respectively The normalized RMS harmonic flux
characteristic of the proposed PWM and some slices of the
characteristic with the SLO PWM in Fig 10(a) are shown in
Fig 11(a), for the three-level inverter A similar comparison is
shown in Fig 11(b) for the five-level inverter As observed
from each comparison, the normalized harmonic flux
characteristic of the SLO PWM corresponding to o
0
identical to one obtained by the VBM PWM method
It can be seen that the proposed PWM yields the optimum
curves in both comparisons For the three-level inverter, the
normalized harmonic flux characteristic of the proposed PWM
is nearly identical to one obtained by the SLO PWM
at90oin the region of (0 - 0.5) of the modulation index In
the region of m higher than 0.5, the proposed PWM method
yields better performance in the RMS harmonic flux, as
compared to the SLO PWM pertaining to all selected slices
For the five-level inverter, the normalized RMS harmonic flux
characteristic of the proposed PWM method is nearly identical
to the slices of o
0
90
, respectively, in the regions
of (0.45 - 0.53) and (0 - 0.25, 0.63 -0.69) of the modulation
index, while is significantly lower than all selected slices in
other regions
D Switching loss
In [20], the average value of the local (per carrier cycle) switching loss over the fundamental (for instance, for phase A) can be calculated:
d f T
t t V
s
off on dc
2
) ( 2
0
where, t o nand t o ff represent the turn-on and turn-off times of the switching devices, respectively, and f iA() is the switching current function, the instantaneous value of which is defined as a product of the number of commutations on the A-phase in a switching period and the absolute value of its corresponding current i A()
else
d A if k
i k
f iA A
1
2
; ) ( ) ( (41)
The switching loss function (SLF) is defined as:
0
P
P SLF swa ve (42)
where,P0is the maximum value of the switching loss
attainable for the defined load currents
The Switching Loss Function (SLF) of the proposed PWM
is dependent on both the modulation index and the phase
a) Three-level NPC inverter
b) Five-level cascaded inverter Fig 10 Normalized RMS harmonic flux with the SLO PWM method of the
three-level NPC inverter and the five-level cascaded inverter
a) Three-level NPC inverter
b) Five-level cascaded inverter Fig 11 The Normalized RMS harmonic flux characteristics with the VBM PWM method (1), the SLO PWM method pertaining to different phase displacements (2) and the proposed PWM method (3) of the three-level NPC inverter and the five-three-level cascaded inverter
Trang 9displacement The SLF surfaces of the proposed PWM method
for the three-level inverter and the five-level inverter are
shown in Fig 12(a) and Fig 12(b), respectively
Comparisons of several slices of the SLF with the proposed
PWM and the two SLF characteristics pertaining to the VBM
PWM and the SLO PWM, are shown in Fig 13(a) and Fig
13(b) for the three-level inverter and the five-level inverter,
respectively In both comparisons, the SLF corresponding to
the SLO PWM is a minimum constant value of 0.756 [17],
while the characteristic corresponding to the VBM PWM and
those pertaining to the proposed PWM with different
displacements are varied in the range (0.756 - 1) depending on
the modulation index
A SIMULATION RESULTS
In order to confirm the analytical evaluation obtained for the normalized RMS harmonic flux of the proposed PWM method as well as of other existing PWM methods in [17], numerical evaluation based on the simulated data is performed The output frequency is kept at 50 Hz while the modulation index is increased from 0 with step size of 0.05 The switching frequency is set to 2 kHz The DC-link voltages are set to Vdc =311 Vfor the three-level NPC inverter, and to
Vdc =155.5 V for the five-level cascaded inverter, so that the maximum output line voltage of both topologies in the linear range of the ZCMV PWM control is 380V RMS
Figs 14(a) and 14(b) present the normalized RMS harmonic flux characteristics pertaining to the three ZCMV PWMs of the three-level NPC inverter and the five-level cascaded inverter, respectively The comparisons show good agreement between the numerical results and the analytical results evaluated in Fig 11
a) Three-level NPC inverter
b) Five-level cascaded inverter Fig 12 SLF characteristic of the proposed PWM method of the
three-level NPC inverter and the five-three-level cascaded inverter
a) Three-level NPC inverter b) Five-level cascaded inverter
Fig 13 Slices of the SLF function of the proposed PWM method (3) versus
SLF characteristics of the VBM PWM method (1) and SLO PWM method (2)
of the three-level NPC inverter and the five-level cascaded inverter
% 18 1
% 33 142
L L
v v
WTHD THD
% 03 1
% 07 142
L L
v v
WTHD THD
% 02 1
% 03 142
L L
v v
WTHD THD
Fig 15 Output line voltage spectra of the three-level NPC inverter with the three ZCMV PWM methods for m = 0.346 at 20Hz
a) Three-level NPC inverter
b) Five-level cascaded inverter Fig 14 The normalized RMS harmonic flux characteristics pertaining to the VBM PWM method (1), the SLO PWM method with different phase displacements (2) and the proposed PWM method (3) of the three-level NPC inverter and the five-level cascaded inverter
Trang 10Fig 15 and Fig 16 show the line voltage spectra of the
three-level NPC inverter with the three ZCMV PWMs,
corresponding to cases of (m=0.346, fo= 20Hz) and (m=0.866,
fo= 50Hz) The designed phase displacements for the SLO
PWM control are set at o
82 and84o, respectively, in cases of
fo = 20Hz and fo =50Hz, similar to the measured phase
displacements in the later experiment of V/f induction motor
control
As seen from the line voltage harmonic spectra in Figs
15(a)-15(c) of the three-level NPC inverter, the harmonic
component magnitudes in the sideband harmonics around 2
kHz with the proposed PWM are slightly lower than those
with the SLO PWM, while are significantly reduced as
compared to those with the VBM PWM Figs 16(a)-16(c)
shows reduced harmonic component magnitudes of around 2
kHz with the proposed PWM over both of the VBM PWM and
SLO PWM Similar comparisons are performed for a
five-level cascaded inverter as shown in Figs 17-18 Similar to the
case of the three-level NPC inverter, the harmonic component
magnitudes around 2 kHz with the proposed PWM method are
substantially lower than those of the two other ZCMV PWM methods in both comparisons
The THD and WTHD values of the output line voltage are defined, respectively, as in [25]:
2 2
1
n
Ln Lfund
V
THD
L (43)
2
2 ) ( 1
n
Ln Lfund
V
n
V V
whereV Lfu n dandV Lnare, respectively, the RMS value of the fundamental component and the RMS value of the th
n
harmonic component of the output line voltage
In order to analyze the THD of the current with no dependence on the load parameters, the WTHD factor of the output line voltage in (44) can be utilized In Figs 15-18, THDs and WTHDs of the output line voltage of the three-level NPC inverter and five-level cascaded inverter with the three
% 02 1
% 92 49
L L
v v
WTHD THD
% 03 1
% 18 50
L L
v v
WTHD THD
% 97 0
% 03 50
L L
v v
WTHD THD
Fig 16 Output line voltage spectra of the three-level NPC inverter with the three ZCMV PWM methods for m = 0.866 at 50Hz
% 59 0
% 21 74
L L
v v
WTHD THD
% 58 0
% 11 74
L L
v v
WTHD THD
% 52 0
% 15 74
L L
v v
WTHD THD
Fig 17 Output line voltage spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.346 at 20Hz
% 51 0
% 06 26
L L
v v
WTHD THD
% 53 0
% 12 26
L L
v v
WTHD THD
% 48 0
% 08 26
L L
v v
WTHD THD
Fig 18 Output line voltage spectra of the five-level cascaded inverter with the three ZCMV PWM methods for m = 0.866 at 50Hz