Khanh Tu, Hai Quach Thanh Department of Electrical and Electronics Engineering Hochiminh City University of Technology Hochiminh City, Vietnam nvnho@hcmut.edu.vn Hong-Hee Lee Departmen
Trang 1A Reduced Switching Loss PWM Strategy to Eliminate
Common Mode Voltage In Multilevel Inverters
Nho-Van Ng., Tam Ng Khanh Tu, Hai Quach Thanh
Department of Electrical and Electronics Engineering
Hochiminh City University of Technology
Hochiminh City, Vietnam nvnho@hcmut.edu.vn
Hong-Hee Lee Department of Electrical Engineering
University of Ulsan Ulsan, Korea hhlee@ulsan.mail.ac.kr
Abstract— This paper introduces a novel PWM technique to
eliminate common mode voltage (CMV) in multilevel inverters
using the three zero common mode vectors Similarly, as in
conventional PWM for multilevel inverters, this PWM can be
properly depicted in an active two-level voltage inverter With
the help of two standardized PWM patterns, the
characteristics of the PWM process, as a switching time
diagram and switching state sequence, can be fully explored in
that active inverter Due to the existence of an unequal number
of commutations of three-phases in each sampling period, the
optimization of the switching loss is achieved by a proposed
current mapping algorithm The switching loss reduction can
be up to 25% as compared to the same PWM technique with
non-optimized algorithms The theoretical analysis is verified
by simulation and experimental results
I INTRODUCTION
In recent year, great progress has been made in the
development of multilevel inverters in electric drives and
other applications Two basic circuits are commonly used in
practice: diode clamped multilevel inverters, cascaded
multilevel inverters as shown in Fig 1 Three main PWM
schemes are commonly used are the space vector PWM, the
carrier-based PWM, and the selective harmonic elimination
PWM techniques [1-3]
It has been well-known that the common-mode voltages
are associated to the excessive bearing currents which may
cause premature motor bearing failure and electromagnetic
interference [4-6] There have been a number of approaches
to cope with the CMV issue including the use of extra
hardware with passive and/or active devices However, the
extra hardware utilization causes a significant increase in
the system’s volume or much more complex control
methods The multi-level inverters have high a number of
switching states that can either reduce or eliminate the
CMV Based on this advantage, many researches for the
CMV mitigation have been made using multi-level
inverters [7-8]
In partial PWM methods to eliminate common mode
voltage, the output voltage can be obtained normally by a
conventional Discontinuous PWM technique (DPWM) [9]
In order to attain reduced common mode voltage at a high modulation index, a new DPWM pattern from three non-nearest vectors was proposed [10] In another work, a trade-off in the THD factor and switching loss for reducing the number of common mode current pulses (dv/dt) could be managed with a change in sequence of the non-nearest vectors [11]
In order to avoid the common mode influence, in another trend, researchers have tried to fully eliminate the common mode voltage The idea of complete CMV elimination that restricts the inverter switching states to those states of zero CMV was first proposed by K Ratnayake and Y Murai in [12] for a three level NPC inverter In [13], the modulation of selected zero CMV states has been applied to the three level NPC using both carrier based and space vector modulation scheme Similar
to [12], the method utilizes three zero CMV vectors in three level NPC inverter to synthesize the reference output voltages However, the rule of distribution of these vectors
in each switching sequence is not mentioned Furthermore, the symmetrical double sided pattern which consists up to twelve commutations causes a considerable switching loss
dc
v
dc
v
dc
v
dc
v
O
A
SW1
A
SW2
A
SW3
A
SW4
dc v
dc v
dc v
dc v
dc v
dc v
O
A
SW1
A
SW2
A
SW3
A
SW4
Fig 1 Multilevel Inverter circuits: a) five-level Diode clamped inverter and b) five-level cascade inverter
Trang 2In this paper, a simple carrier based method to cope with
this problem is presented Its main contributions are
clarified in the following points:
- As a general principle for an n-level inverter, all
switching sequences and corresponding switching time
diagrams will be derived from two generalized PWM
patterns The two patterns represent switching state
sequence of corresponding active two level inverter The
algorithm to select the PWM pattern can be applied to
arbitrary number of levels without losing the generality
- The number of commutations per sampling period are
reduced to eight Besides, the switching state sequence is
locally optimized within the standardized PWM patterns,
which helps to reduce switching loss
The experimental results obtained with five-level
cascaded inverter are used for verifying the performance of
the proposed PWM strategy
II PROPOSEDPWMMETHODTOELIMINATE
A Voltage modeling of multilevel inverter and offset
condition for eliminating common mode voltage
Due to the difference in structure of the diode clamped
inverter and cascade inverter, as illustrated in Fig 1 for
five-level inverter, established rules of switching
combinations for a same reference output voltage are
completely different In this paper, the analytical process for
the two topologies can be unified by a simple voltage
modeling With selected neutral point ‘O’ and designated
switches of A-phase represented as
SW ,SW ,SW ,SW for the two topologies in Fig
1, the pole voltage v is generally determined as AO
V = (s + s + s + s ) V − 2V (1)
where s ,s ,s ,s1A 2A 3A 4Arepresent the switching states of
SW ,SW ,SW ,SW respectively, s is ‘1’ if 1A SW is 1A
on otherwise its value is ‘0’
It should be noting that s ,s ,s ,s1A 2A 3A 4Acan be selected
randomly in the five level cascaded inverter while are
further restricted in five level diode clamp inverter due to
the limit of its switching combinations The constraint is
simply expressed as
s ≤ s ≤ s ≤ s (2)
For an n-level inverter of the two topologies, (1) and (2)
can be generalized as, X=A,B,C :
n 1
j 1
(n 1)
2 (n 1)
2
−
=
−
−
and
s ≤ s ≤ s ≤ − ≤ s − ,X=A,B,C ( for diode clamp inverter topology) (4)
The component n 1 jX dc
j 1 ( s )V
−
=
∑ (X=A,B,C) in (3) is called
the switching voltages We define V =Xn n 1 jX
j 1 s
−
=
∑ (*) as the normalized switching voltage which, for further analysis, can be used to represent V Relationship between XO V Xn and V is described as XO
XO Xn dc
V
−
= + (5) The normalized switching voltage V (*) can be Xn
decomposed into two components L X and sX:
V = L + s (6) During a sampling period, LXis a constant integer
value which represents the base component of VXn and sX
is the active component of VXn which can be changed between 0 and 1 during a sampling time period Taking (5) and (6) into account, the equivalent circuit of the instantaneous voltage of VXO is derived as in Fig 2(a)
(L L L A, B, C) is named as the normalized three phase base voltages and (s ,s ,s )A B C the normalized three phase active voltages in Fig 2a
If ξ Xis defined as the average active component of sX
in a sampling period, the average value of V defined as Xn
Xn
v can be derived as follows:
;0v Xn=L X +ξ X ≤ξ X ≤ (7) 1 and the equivalent circuit of the average voltage of VXO
can now be described as in Fig 2(b)
Let define v*X1(X=A,B,C) the reference output fundamental voltages, v Xnin (6) can also be expressed as
*
* 1
X
dc
v
V
= + (8) The offset voltage v*off of the circuit in Fig 2(c), for any
PWM method can be designed to have any value in the limits as:
*
= − ≤ ≤ = − − (9)
Trang 3where MAX and MIN are the highest and the smallest
of the three fundamental voltages (v*A1,v*B1,v C*1) and n is the
number of levels
The equivalent circuit of the average voltage of VXO
following (5),(8) is described in Fig 2c
Fig 2 a) Equivalent circuit of instantaneous three-leg voltages of
n-level voltage source inverter; b) Average voltages modeling of three-leg
voltages; c) Average voltages modeling from reference fundamental
voltage and offset voltage components; d) Total switching voltage and its
components (F e =ξA+ξB +ξC, F L =L A+L B+L C)
The offset for eliminating CMV v0ff,ZCMV
The common mode voltage defined for n-level inverter
in Fig 1 is described as :
3
AO BO CO
cm
V = + + (10)
The instantaneous value of V following Fig 2(a) is cm
derived as
( An Bn Cn 3( 1) / 2 )
3
dc cm
V = + + − − (11)
The combinations of (V ,V ,V ) which do not AO BO CO
contribute any common-mode voltage, represent the zero
CMV vectors in the vector diagram of n-level inverter
which result in zero value of V cm
We define f as n
f =V +V +V (12)
It can be seen from (11) that under the condition of the eliminating CMV PWM control:
fn = fZCMV = 3 ( n − 1 ) / 2 (13) For example, considering the cascaded five level
inverter in Fig 3, among 125 possible combinations, there are 19 switching combinations which produce zero CMV
All zero CMV vectors satisfy (13) with f = n 6 With a normalized switching state of ZCMV described as (V An,V V Bn, Cn)= (4,1,1), for example, the pole leg voltages are derived using (5) asVAO=2Vdc, VBO = −Vdc ,
dc
CO
V = −V
Fig 3 Five-level space vector diagram with zero CMV state (bold letters)
In case of the equivalent circuits described in terms of average voltages in a sampling period as shown in Fig 2(b) and Fig 2(c), with a note that (v*A1+v*B1+v*C1)=0, the condition of zero average CMV results in:
voff* = voff,ZCMV = ( n − 1 ) / 2 ( 14) and the sum of the average values of V (X=A,B,C) Xn
defined as F=v An+v Bn+v Cn is obtained with the following value:
2 / ) 1 (
= +
=
F ZCMV L e (15) where FL and Fe are determined respectively as:
FL = LA + LB + LC (16)
C B A e
F = ξ + ξ + ξ ;;0 ≤ Fe ≤ 3 (17) The functions F,FL,Fe determine respectively the total switching voltage, total base voltage and total active voltage as described in Fig 2(d)
Trang 4B Medium Triangle active voltage vector diagram of
the Two-level active voltage Inverter under eliminating
common mode voltage PWM control
In space vector diagram of a multi-level inverter, a
discrete vector can be decomposed into two components as
follows:
S
VG =L sG G+
(18)
where LGis the pointing vector formed by the three
phase base voltages and sGis the active vector formed by the
three phase active voltages in Fig 2(a) Following (18), any
discrete vector in the space vector diagram of an n-level
inverter can be represented by ( ,sLGJJG) Its worth noting that
the three zero common mode vectors (ZCMV) in the space
vector diagram have the same base voltage vector LGwhich
tip locates at center of the equilateral medium triangle
formed by tips of the three vectors
A simple carrier based ZCMV PWM control method is
established under the consideration of (6), (13) for
instantaneous voltage modeling in Fig 2(a) and (7), (8),
(14)-(17) for average voltage modeling in Fig 2(b), 2(c),
2(d) It has been shown that the function FLin (16) is
determined by the base voltage vector which tip is located at
the center of the active triangle and the function Fe is
related to the active voltage vectors of the medium triangle
vector diagram as illustrated in Fig 4 A general analysis
has been shown that, for an n-level inverter, the ZCMV
condition confines the possible values of FL,Fe to those
expressed as:
3( 1) / 2 2; 2 (a)
3( 1) / 2 1; 1 (b)
3( 1) / 2 ; 0 (c)
e L
e L
e L
(19)
The proposed CMV elimination PWM in multi-level
inverters can be obtained by solving (19) With exception of
case (19.c) related to several pivot vectors, the two
remaining available values of FL,Fe are further limited to
(19.a), (19.b)
In case F L=3(n−1) / 2 2− and F e =2(19.a), the
condition of F e=2 will be realized with three active
switching states as (1,1,0), (0,1,1) and (1,0,1) in the active
voltage hexagonal diagram as illustrated in Fig 4(a)
Similar to the previous case, in case
3( 1) / 2 1
L
F = n− − and F =e 1(19.b), the condition of
1
e
F = will be realized with three active switching states as
(1,0,0), (0,1,0) and (0,0,1) in the active voltage hexagonal
diagram as in Fig 4(b)
Fig.4: Medium triangle active voltage vector diagrams: a) switching states for F e=2(F L=3(n 1) / 2 2)− − and b) switching states for 1( L 3(n 1) / 2 1)
e
For space vector diagram with ZCMV of a five-level inverter as shown in Fig 3, 24 equilateral medium triangles defined by three zero common mode vectors can be found:
twelve triangles, which corresponding base vectors meet the condition F L=F L1= , confine the light area; the others, 4 satisfy F L=F L2= , cover the shaded area 5
The value of the base voltage and the active voltage can
be deduced from (20), (21):
X
Xn
L
⎧⎪
⎨
⎪⎩
< −
=
− = − ;0≤L X ≤ −n 2 (20) ( ,ξ ξ ξ A B, C)=(vAn−L A,vBn−L B,vCn−L C) (21) The values vXn under the conditions of ZCMV are
defined by (8) and (14) and Int v( Xn) denotes a function that returns a nearest lower integer value of vXn
C ZCMV PWM patterns and ZCMV PWM control algorithm
Based on the medium triangle active vector diagrams generalized for an n-level inverter as described in Fig 4, the PWM switching state sequence of the active voltage vectors
in the ZCMV PWM control can be grouped into two PWM patterns related to the F evalues
In caseF =e 1, the active switching state sequence forms PWM pattern 1 as described in Fig 5(a) Two from three ABC phases are mapped to s and 1 s that the 2 s -level 1
varies as 0-1-0 in a sampling period and the s -level 2
varies as 1-0-1 in a sampling time period All of them have
a single pulse waveform The remaining phase is mapped to the d-phase that the d-level will vary as 0-1-0-1-0 and has a double pulse waveform in a sampling time period
In case F =e 2, the active switching state sequence corresponds to PWM pattern 2 as described in Fig 5(b)
Two from ABC phases are mapped to s and 1 s that the 2 s -1
Trang 5level varies as 0-1-0 in a sampling period and the s -level 2
varies as 1-0-1 in a sampling time period All of them have
a single pulse waveform The remaining phase is mapped to
the d-phase that the d-level will vary as 1-0-1-0-1 and has a
double pulse waveform in a sampling time period
1
s
ξ
e
F = ξ + ξ + = ξ
2
1 − ξs
1
s
ξ
e
F = ξ + ξ + = ξ
0 0 1 1 0 0
0 1 1 1 1 0
1 1 0 0 1
1 0 1 1 0 1
1
2
d
1 2
d
0
0
1
T
2
2
T
T T 2 T 1
2
1
T 2
2
T T3 T 2
2 1 T 2
2
1 − ξs
Fig 5: Two Standardized virtual PWM patterns from three-nearest
vectors of zero common mode voltage
Table I:
Possible Mapping functions and modulating signals determination
1
2
→
→
→
2
1
→
→
→
1
2
→
→
→
2
1
→
→
→
1
2
→
→
→
2
1
→
→
→
s1 B
ξ = ξ
s2 C
ξ = ξ
s1 C
ξ = ξ
s2 B
ξ = ξ
s1 A
ξ = ξ
s2 C
ξ = ξ
s1 C
ξ = ξ
s2 A
ξ = ξ
s1 A
s2 B
ξ = ξ
s1 B
ξ = ξ s2 A
ξ = ξ
For three phase outputs with the use of the two Patterns
in Fig 5, six possible Mapping functions are listed in Table
I Different Mapping functions result in different three phase
active switching sequences For example, when using the
Mapping function(A→d,B→s1,C→s2) for the Pattern I,
three phases A,B,C will be mapped to s ,s ,d1 2
-sequence respectively Hence the three-phase active
switching sequence expressed as (s ,s ,s )A B C is
(0,0,1)→(1,0,0)→(0,1,0)→(1,0,0)→(0,0,1) If the mapping
function, in another example, is selected as
(A→s,B→s ,C→d), the three-phase active switching
sequence will be (0,1,0)→(0,0,1)→(1,0,0)→(0,0,1)
(0,1,0)
→
III SWITCHING LOSSES OPTIMIZATION
The switching losses linearly increase with the
magnitude of the commutating phase current The average
value of the local (per carrier cycle) switching loss over the
fundamental (for instance, for the phase A) can be
calculated as [14]:
2
0
1
( )
dc on off
s
V
T
π
θ θ π
+
= ∫ (22)
where t on and t off represent the turn-on and turn-off time of the switching devices respectively, and f θ iA( ) is the
switching current function which instantaneous value is defined as product of the number of commutations on A-phase in a switching period and the absolute value of its corresponding current i ( )A θ
( ) k i ( )
f θ = θ (23) The switching loss function (SLF) is defined as:
0
swave P SLF
P
= (24) where P0is the maximum value of the switching loss
attainable for the defined load currents
When using the proposed PWM method with two standardized PWM patterns in Fig 5, the distribution of commutations in a switching period is unequal on each
phase It can be seen that the d-sequence contains a double
number of commutations compared to the other s ,s1 2
-sequences The factor k is thus determined as follows:
2 1
k else
⎧⎪⎪⎪
⎨⎪
⎪⎪⎩
→
= (25)
By substituting (25) into (23), it can be concluded that
iA
corresponding phase current in the interval that the A-phase
is mapped into the d-sequence (A→d)and equals the absolute value of the current in other cases
The Mapping function, as described in Table I, can be altered between six possible cases so that an arbitrary output phase can be mapped into the d-sequence If all the selected Mapping functions satisfy the constraint that only output phase of minimum absolute current is mapped to the d-sequence, the switching current function described in (23) will always be obtained with minimized value Hereby, the switching loss function in (24) can be optimized Based on this idea, a current-based Mapping PWM algorithm which optimizes the switching loss is proposed
A B C
A B C
A B C
mx max( k , k , k )
md mid( k , k , k )
mn min( k , k , k )
=
=
=
A
k = mn
B
k = mn
y k B > k C
y n
n
A C
k > k
A B
k > k
y n
n y
y n
X X X A, B,C
k = i ; =
=
C
k mn
Selected Mapping function
A
i i B i C
1 2
A → d, B → s ,C → s
2 1
A → d,B → s ,C → s
A → s , B → d,C → s
2 1
A → s , B → d,C → s
1 2
A → s , B → s ,C → d
2 1
A → s ,B → s ,C → d
Fig.5b- Block diagram of the proposed Current-Based Mapping PWM
Trang 6Fig 6: Current-based mapping PWM method (a) and switching
current functions of three phase: (b) f ( )iA θ (c) f ( )iBθ (d) f ( )iCθ
In the proposed Mapping PWM algorithm with
optimized switching loss, the feedback currents , ,i A i i are B C
utilized as inputs of the flow diagrams kX=i (X A,B,C)X =
, ,
mx md mnare determined, respectively, as the maximum,
medium and minimum of the absolute values of , ,i i i A B C
The Mapping function is chosen so that the phase with
minimum absolute current is mapped to the d-sequence The
selected Mapping function is then utilized to complete the
proposed PWM scheme of zero CMV
Figure 6(a) illustrates the operation of the proposed
current-based mapping method in Fig.5b following the
feedback waveforms of the output currents By using (23),
(25), the A-phase switching current function waveform
( )
iA
f θ is derived as illustrated in Fig 6(b) Since the
A-phase is set to the d-sequence during the interval that its
current attains a minimum absolute value, the waveform of
( )
iA
f θ always confines a minimized Ampere-second area
regardless of the load displacement factor Hence the
waveform f θ corresponds to a minimum value iA( ) PswOpt of
the switching loss Pswave defined by (22):
1
4
s
T
+
=
π (26)
8 2 3 4.5359
opt
Similarly, the optimized waveforms of the B and
C-phase switching current functions are shown in Fig 6(c) and
6(d) respectively
To evaluate the improvement of the switching loss
when using the proposed Current-based Mapping PWM, it
is necessary to determine the range of the switching loss function This can be done by an analysis of a so-called voltage-based mapping algorithm under different phase displacement factors The voltage-based mapping algorithm can be simply implemented by replacing i X(X A,B,C)= with the reference output voltages *
vX = as inputs of the flow diagram in Fig.5b mx md mn, , are then, respectively, the maximum, medium and minimum of the absolute values of *
vX = The voltage-based mapping algorithm which operation following the waveforms of the reference output voltages is illustrated in Fig 7(a) Since the rule of switches distribution of the voltage-based mapping PWM is based on information of reference voltage (offline), the waveform of f θ is iA( ) changed differently depending on the current phase displacement angle ϕ For example, three cases of phase displacement angle: ϕ= 0,ϕ = π/ 6,ϕ = π/ 2in Fig 7(b), 7(c), 7(d) will result in three different waveforms of f θ iA( )
as shown in Fig 8(a),8(b),8(c)
Fig 7: Voltage-based mapping PWM method with different current phase displacement b ϕ = 0 c.
/ 6
ϕ = π d ϕ = π / 2
Fig 8: Waveforms of switching current function using voltage-based PWM method a ϕ = 0 b ϕ = π / 6 c ϕ = π / 2
In the case ϕ= 0, the A-phase output current, as illustrated in Fig 7(b), is in phase with its corresponding
0
Im
0
Im
0
Im
-Im
0
Im
-Im
Im
π/6 π/2 5π/6 7π/6 3π/2 11π/6 13π/6 15π/6
iB
Im
0
Im
0
Im
0
0
0
fiA
fiB
fiC
ωt
ωt ωt
ωt
iABC
s1 d d s2 s2 d s1 s2 d d s1 s1 d s2 s1
d
d
s2
a)
A B
b)
c)
-Vm
Im
-Im Im
-Im
-Im Im
0
0
0
0
π/6 π/2 0 Vm
5π/6 7π/6 3π/2 11π/6 13π/6 15π/6
ωt
ωt
ωt ωt
A B s1 d d s2 s2 d s1 s2 d d s1 s1 d s2 s1 d d s2
iA(ϕ=0)
iA(ϕ=π/2)
iA(ϕ=π/6) ϕ=0
ϕ=π/6
ϕ=π/2
a)
b)
c)
d)
v* A1 v* B1 v* C1
0 Im 2Im 0 Im 2Im 0 Im
0
0
0
Im
2Im Im
Im 2Im
0
ωt
ωt ωt
13π/6 11π/6 7π/6 5π/6
fiA(ϕ = 0)
fiA(ϕ=π/6)
fiA(ϕ=π/2)
a)
b)
c)
Trang 7reference voltage *
1
vA As can be seen from Fig 8(a), the waveform of the A-phase switching current function is
identical to one obtained by using the Current-based
Mapping algorithm in Fig 6(b) The switching loss Pswave
is thus corresponding to the minimum value P swOpt
expressed in (26) A general evaluation using (22), (23),
(25) has been shown that the switching loss Pswave
increases from its optimum value P swOpt to its maximum
value P0 attainable for the defined load current if the phase
displacement ϕ increases from 0 to / 2π As can be seen
from Fig 7(d), at ϕ = π/ 2, the A-phase is set to the
d-sequence of double commutations during the interval its
current attains maximum absolute value P0can be
computed as:
0
m on
s
T
+
π (27)
As a result, the SLF characteristics of the Voltage-based
mapping algorithm along with the Current-based mapping
algorithm (optimizing algorithm) analyzed in the region
0≤ϕ≤π are illustrated in Fig 9
Fig 9: Characteristic of Switching Loss Function SLF( ) ϕ of the
Voltage-based mapping PWM method (1) and Optimizing method (2)
By applying the optimizing algorithm at the power
factor of 0.85, in comparison with the voltage-based
mapping PWM algorithm, the switching loss function
decreases by about 10% For PF<0.55, the reduction can be
more than 20% Figure 9 shows that the switching loss
function can be reduced by 25% at the phase displacement
of 90 degrees Since the number of commutations in a
switching period of the proposed PWM method, as
compared to [12,15], is reduce to two third, the switching
loss function can be then reduced by 43% compared to the
two mentioned methods
IV EXPERIMENTALVERIFICATION
In order to verify the validation of the proposed PWM
strategy, experimental results were obtained by applying the
proposed schemes to a five-level cascaded inverter Each
H-Bridge is made up of IGBTs using FGL-60N100-BNTD
The DC voltage on each H-Bridge is held constant at 100V
The rating of each DC-link capacitor used for the
experimental setup is 4700μ F The load is R-L load which,
in each experiment, can be set at different value to create
different phase displacement factors The fundamental
frequency f is selected as 50 Hz The frequency of the o
triangle carrier waveform f is 2.31 kHz In online s
algorithm for switching loss optimization, two additional Hall sensors LA55-P are used to measure two output currents Since the three phase load is balanced, the third current can be deduced from the two measured currents For comparison, the conventional sinusoidal PWM method
is also realized
Figure 10 depicts the obtained waveforms and FFT analysis of phase voltagevAN(N is the load neutral), phase current i Aand CMV v NOof the conventional sinusoidal PWM method As a comparison, the same quantities are given in Fig 11 for the proposed PWM method with CMV elimination and switching loss optimization There are different of levels of line-to-line voltage when the inverter operates with and without CMV elimination scheme, as shown in Fig 10(a) and Fig 11(a) Also, it can be noted from the FFT analysis in Fig 10(d), 10(e) and Fig 11(d), 11(e) that the conventional method yields better results of output voltage and current THD These difference can be explained based on the limited number of switching states under condition of zero CMV compared to the conventional PWM method
Fig 10: Experimental results when using conventional Sinusoidal PWM method at modulation index 0.866
m =
Fig 11: Experimental results when using proposed PWM method with CMV elimination (Current-based Mapping), at modulation index m =0.866
A
i
Fig 12: Experimental results when using proposed PWM method with CMV elimination (Voltage-Based Mapping), at modulation index 0.866
m = (f o= 50Hz,R= 40 , Ω =L 180mH) Because of this, a greater distance among the closet active switching states in the vector diagram causes a greater harmonic distortion Figure 10(c), 10(f) and Figure 11(c), 11(f) illustrate the CMV waveform and its FFT analysis in the two PWM methods The CMV which is represented with large magnitude in Fig 10(c) has been
0 π /6 π /3 π /2 2π/3 5π/6 π
0.756
0.9
1
ϕ
0
SLF(ϕ)
(1)
(2)
Trang 8eliminated in Fig 11(c) The existence of switching spikes
in the CMV waveform in Fig 11(c) are on account of the
dead-time intervals during switching transitions
A i
Fig 13: Experimental results when using proposed PWM method
with CMV elimination (Switching loss optimizing Mapping), at modulation
index m =0.866 (f o= 50Hz,R= 40 , Ω =L 180mH )
Experimental results including waveforms of three phase
currents (Xi X =A B C, , ) and A-phase output voltage vAN
are shown in Fig 12 for voltage-based mapping algorithm
and in Fig 13 for switching loss optimizing mapping
algorithm In Fig 12, the load is R= Ω =40 ,L 180mHwhich
corresponds to ϕ = 55 degree A double commutation on
A-phase doesn’t occur around its zero current value By
using the same experiment configuration in Fig 12 and
applying the current-based mapping algorithm (switching
loss optimizing algorithm), the experimental results are
obtained as depicted in Fig.13 A double commutations on
A-phase, as observed from Fig 13, are confined to
intervals of minimum absolute value of its current
V CONCLUSION
In this paper, a novel PWM strategy to eliminate
common mode voltage for multi-level inverter using three
zero common mode vectors has been proposed By using a
proper coordinate transformation, modulation of a n-level
inverter with common mode voltage elimination is
simplified to that of a active two level inverter with three
available switching states Based on a general analysis of a
n-level inverter, two generalized virtual patterns are
proposed to cover the whole space vector diagram The two
proposed patterns result in switching sequences with a
minimum number of commutations among those in which
each switching state is symmetrically distributed Using the
optimizing PWM algorithm, the local reduction of switching
loss can be up to 25% as compared to non-optimized
algorithms
ACKNOWLEDGMENT
This research is funded by Vietnam National Foundation for
Science and Technology Development (NAFOSTED) under
grant number 103.01-2011.67 and partly funded by
Minister of Science and Technology under grant project
number KC.03.17/11-15
REFERENCES
1 J.Rodriguez, J S Lai and F Z Peng, ”Multilevel
inverters: a survey of topologies, controls and
applications”, IEEE Trans Industrial Electronics, Vol
49, No 4, pp.724-738, August 2002
2 G Carrara, S.Gardella,M Marchesoni,R Salutari, and
G Sciutto, ”A New multilevel PWM Method- A Theoretical Analysis,” IEEE Trans.On Power Electronics, Vol.7, No.3, July 1992, pp.497-505
3 S Wei, B.Wu, F L and C Liu,” A general space vector PWM control algorithm for multilevel inverters” pp.562-568, IEEE conf APEC 2003
4 Fei Wang, “Motor shaft voltages and bearing currents and their reduction in multilevel medium-voltage PWM voltage-source-inverter drive applications”, IEEE Transactions on Industry Applications, Vol 36, No 5,
September/October 2000, pp.1336-1341
5 J M Erdman, R J Kerkman, D.W Schlegel, and G L Skibinski, “Effect Of PWM inverters on AC motor bearing currents and shaft voltages,” IEEE Trans Ind
Applicat., vol 32,pp.250-259, Mar./Apr 1996
6 S Chen, T A Lipo, and D Fitzegrald, “Modeling of motor bearing currents in PWM inverter drives,” IEEE Trans Ind Applicat., vol 32, pp 1365-1370,Nov./Dec
1996
7 Annette von Jouanne, and Haoran Zhang,”A dual-bridge inverter approach to eliminating common-mode voltages and bearing and leakage currents”, IEEE Trans On Power Electronics, Vol 14, No 1, January
1999, pp.43-48
8 H.Zhang, A.V Jouanne, S Dai,A.K Wallace, and Fei Wang, , “Multilevel Inverter Modulation Schemes to Eliminate Common-Mode Voltages”, IEEE Transactions on Industry Applications, Vol 36, No 6, November/December 2000, pp.1645-1653
9 H Kim, H Lee, and S Sul, “A new PWM strategy for common mode voltage reduction in neutral-point-clamped inverter-fed AC motor drives,” IEEE Trans Ind Applicat., vol 37, pp 1840–1845, Nov./Dec 2001
10 Gupta, A.K.; Khambadkone, A.M.A, “Space Vector Modulation Scheme to Reduce Common Mode Voltage for Cascaded Multilevel Inverters”, Power Electronics, IEEE Transactions on, Vol 22, No.5, pp 1672 – 1681
11 Arnaud Videt, Philippe Le Moigne, Nadir Idir, Philippe Baudesson, and Xavier Cimetière, “A New Carrier-Based PWM Providing Common-Mode-Current Reduction and DC-Bus Balancing for Three-Level Inverters”, IEEE Trans On Industrial Electronics, Vol
54, No 6, December 2007,pp.3001-3011
12 K Ratnayake and Y Murai, “A novel PWM scheme to eliminate common-mode voltage in three-level voltage source inverter,” in Proc IEEE PESC’98,1998, pp
269–274
13 Shaotang Chen, Thomas A Lipo, and Dennis Fitzgerald , “Modeling of motor bearing currents in PWM inverter drives”, IEEE Transactions on Industry Applications, VOL 32, NO 6, November/December
1996, pp.1365-1370
14 A.M Hava,R.J Kerkman, T.A.Lipo “A high performance generalized discontinuous PWM algorithm”, IEEE Trans On Industrial Applications, Vol 34, No 5, 1998, pp.1059-1071
15 P.C.Loh, D.G.Holmes, Y.Fukuta, and T A Lipo,” Reduced Common-Mode Modulation Strategies for Cascaded Multilevel Inverters”, IEEE Transactions on Industry Applications, Vol 39, No.5, September/October 2003, pp.1386-1395