Quick study academic electronics part 2 600dpi

IDEAL OP-AMP CHARACTERISTICS - Nominal voltage gain, A -Input impedance at both inputs, Zln 00 -Output impedance, Zo ~0 -Both transistors are idcntical.. 4 modes ofoperational characte

~ -~ LINEAR VOLTAGE-TO-CURRENT

CONVERTERS

~

ELE

PART 2 of FUNDAMENTALS OF ELECTRONIC DEVICES & BASIC ELECTRONIC CIRCUITS

OPERATIONAL AMPLIFIERS

DEFINITIONS

- A basic ditlerential amplifier (see Electronics I Part

can be modified to perform addition, integration and

differentiation Hence, the differential amplitier is also

designated as an Operational Amplifier (Op-Amp)

111 essence, a hIgh-gam "" ­

electrol1lc cIrcuIt mtended A

to amphfy the dlflerence 111 + Vo ~ vom

the sIgnal voltages apphed v,,,, v

to its two input terminals, namely, inverting (-) and

non-inverting (+) inputs (Fig 1)

an Op-Amp constitutes a Differential Pair

differential amplifier made output

Up of, for example, a pair of + ~ ­

BJTs driven by a constant Non­

current source (I) JFETs inverting I

and MOSFETs can also be IOput

used as differential pairs

IDEAL OP-AMP CHARACTERISTICS

- Nominal voltage gain, A

-Input impedance (at both inputs), Zln 00

-Output impedance, Zo ~0

-Both transistors are idcntical

·Vo = -AVint = AVin2; or, if Vinl = Vin2, Vo = 0

- Bandwidth (BW) ~ ~

- With bipolar transistors, it may be difficult to

achieve a very high-input impedance

-JFET and MOSFET provide high-input impedance

capabilities

OP-AMP OPERATIONAL PARAMETERS

In reference to typical inverting (Fig 3, above right) andnon­

inverting (Fig 4) modes ofoperational characteristics:

-INPUT BIAS CURRENT: This is the emitter current

in the differential amplifier for active region operation

of the pair of BJTs (e.g 0.0511A for 741 OP-AMP)

which comes through R2 so that Vou' = (0.05 X 10-6

x R 2)volts This could be large enough to saturate the

output Saturation is overcome by introducing R, =

RdlR2 and made adjustable to compensate for input

offset current due to any dissimilarities in the differ­

ential pair configuration (Fig 3)

-INPUT OFFSET VOLTAGE (= ± 60mV): It is

required at the input as a counter voltage to offset the

tinite unbalance voltage due to unequal current flowing

through the differential pair devices in the OP-AMP, so _

that this balancing gives zero output voltage

-CMRR: When the OP-AMP is ideally balanced at

the input, the output voltage = 0 i.e Vlnt = Vin2, and

this circuit can reject common-mode signals due to its

common-mode gain (Ae) = O For differential mode

signals (Vln' - Vin2), the gain (Ad) ~~.The ratio Ad/Ae

common-mode rejection ratio (CMRR) In practical

OP-AMPs, Ae > 0 and Ad < 00; or, CMRR is finite

and indicates the extent of balance in the OP-AMP (A

Igure of merit parameter)

-OUTPUT VOLTAGE SWING: This is the peak

output swing with reference to zero at the output

It is limited by power supply voltages used (= 80

percent of power supply voltage ±V)

-INPUT VOLTAGE SWING: Input common-mode

voltage swing is limited by the saturation of the differ­

ential amplifier at the input: (= 30 percent of power

supply voltage ±V)

-SLEW RATE: Maximum rate at which the output voltage can change (volts/microsecond) In ideal OP­

AMPs, slew-rate ~ 00

-OTHER PARAMETERS: (I) Bandwidth; (2) Maximum output current available when the output terminal is set to ground; (3) PSRR: Power supply rejection ratio: Change in input offset voltage to corresponding change in one of the power supply voltages (±V) Ideally, PSRR = 0; in practice, it is of the order of a few 11VIV

FREQUENCY ROLL-OFF

It is the fall-off of the voltage gain at high frequencies This

is indicated by gain-bandwidth product Roll-off to higher frequencies is achieved by frequency compensation

INVERTING AMPLIFIER (VIRTUAL GROUND AMPLIFIER)

a: Virtual R ,

Fig 3

VOU(

i nput

R , ~ R J

-Output impedance with feedback =' Output impedance of the OP-AMPxClosed-loop gain

(Open-loop gain)

- Node a is almost at ground potential

-Closed-loop voltage gain Vout / Vin = -R2/RI -Input impedance = RI

- Output impedance = Ro NON-INVERTING AMPLIFIER Fig 4

R2

inp ut

Zout ~Low

INTEGRATOR (LOW-PASS FILTER)

feedback for low­

output impedance needs, but it also distorts the output

DIFFERENTIATOR (HIGH-PASS FILTER)

RR , +A - "" -Inverse operatIOn 0

the integrator circuit

LEVEL CLAMPING

- The output is clamped to Zener

voltage V,

1

Source Circuit Sink Circuit

LOGARITHMIC AMPLIFIER

V =-I-In _'_n_

V O ! R~vcr sc sa turation current or E8 Juncti on

: Tran s i slO r a

k : l30hzmann Const ant

CHARGE AMPLIFIER

Fig 10

Input (from a

capac iti ve transducer); Vin Cr: Nominal capaci tan

of the transduc charged by a voltage

V

out = In R,

PRECISION RECTIFIER &

PEAK DETECTOR

Fig 11

Precision Recti fier Peak Detector

VOLTAGE FOLLOWER (UNITY GAIN AMPLIFIER)

Zill =A X (Rill (Device)(

[Ro (Device)]

Unity Gain Amplifier The output voltage "follows" the input voltage Used

as a buffer amplifier with high-input/low-output impedance realization

REGULATED POWER SUPPLY The Zener diode offers a constant reference voltage

(Vz) Bias derived from the unregulated voltage (VII),

via potential division by RI and Rl and the Zener reference voltage, are compared by an inverting amplifier to provide a stable output Voltage

Vou' = V, (t + R./ R2) and I, = (vou,- V,) / R3

Fig 13

DEFINITIONS

• The device current is decided by one type of current

carrier only (unipolar)

• The device interior current is controlled by an electric

field applicd in the path of the current carriers

FET TYPES

·JFET (Junction Field Effect Transistor): In the

JFET, the resistance of the current path is modulated

by the application of bias voltages to PN junctions

adjacent to it

• MOSFET (Metal-Oxide Semiconductor FET): In

MOSFET, there arc no junctions The controlling

electric field is applied via an insulating layer to

regulate the resistance of' a main conducting path

FET OPERATION MODES

• Depletion mode operation: The controlling electric field

reduces the number of carriers available for conduction

• Enhancement mode operation: Application of electric

field causes an increase in the majority-carrier density

in the conducting regions of the transistor

JFET: DEVICE OPERATION

Fig 14a r - , Source ate G I

x-direction

-

VI)

c- = E l ec tron s

Due to the appl ication of the voltage across source

(S)-to-drain (D), electrons flow from S to 0 (majority

carrier flow) Thc path between S-to-O has an ohmic

resistance Therefore, flow of electron current would

cause a voltage drop and the potential at any point

along this path (x-direction) increases from the source

to drain (becoming more positive towards the drain

end) Since the gates (tied together) are connected to

the source, the N-region ofthe channel and the regions

of the gate would form a reverse-biased PN junction

The extent of reverse bias increases progressively from the

source side to drain side Correspondingly, the depletion

layers formcd will be wider near the drain side as shown

Normally, the P-type gates (G I and G z) are heavily

doped relativc to the N-channel region Therefore,

channel has (relatively) high resistance Hence, the

depletion laycr widens predominantly into the channel

region Suppose Vo is increased Consequently, the

depletion layer into the channel widens more As a

result, eventually the two (top and bottom) depletion

layers meet each other Therefore, the channel is

closed, not permitting the flow of electrons through it

This condition is known as pinch-off

OUTPUT CHARACTERISTICS OF JFET

Suppose an additional bias V G is applied between the

gates and the source terminals (Fig 14b):

• Suppose, V G = O In the absence of drain current, the

depletion layer is uniform along the channel As VI)

increases, II) increases Corresponding voltage drop

along the channel causes a wedge-shaped path due to

reasons discussed before Upon pinch-ofl~ the drain

current remains constant at a saturated value

• When V G is applied: This provides additional reverse-bias Therefore, pinch-off will occur at lower VI) and the corresponding VI)(s.') will also

be smaller Hence, application of V G modulates the channel dimension and reduces In This is a depletion mode operation Channel current decreases

as the gate voltage is increased

LINEAR OPERATION OF JFET

Fig 15 Pinch-off locus

Slope: Go

Slope: Go

Suppose channel is lightly doped relative to the gates,

i.e Na(ga'e) » Nd(ch.nnel)' : Thickness of depletion

layer 111 the N-channells d n == 2E eN

As V G changes, d n changes D

[Yo: Contact potential, Na and Nd are acceptor and donor concentrations; €: Permittivity of the channel]

Let V PO be the value of V G at which pinch-off occurs

The corresponding change in In = O For V G < Vpo,

where Go = channel conductance with zero bias (VG=O) condition:

Go = (eNd~.) x

IArea of cross-section of the channell Length of the channell

e: electronic charge; ~c: electron mobility

JFET OPERATION

Upon pinch-off:

I os =1 0" l] - 3VG+2(VG)Vp Vp ~ 1 Transfer Characteristics:

_dlnsl _ 3VJ)l (VG)il

m dV 0" VZ V

gm ~ Mutual/transfer conductance

= Max g =g I =g _ -31

_ Il,_, - G

= Conductance of the channel with zero bias

g ==g ll-(VG )}l

MOSFET

DEFINITIONS

~ Induced channel devicellnsulated Gate FET (IG FET)

·The gate is totally insulatcd rrom the semiconductor by

a thin layer or Si02

• The voltage applied at the gate induces a conducting channel within the semiconductor and modulates its conductivity

ENHANCEMENT TYPE MOSFET

Fig 16

Si02 layer

N+ source N+ drain Polysilicon P-typc cpitaxial substrate

Si02~1 00 to 300 A' (Thermally grown insulation layer)

MOSFET OPERATION

Fig 17

No gate bias

P- ( 'pi )

~

-+1 +VG

N+ Induce

n eg at ive

Suppose no gate voltagc is applied Then, N+P junction

at the source, as well as PN+ junction at the drain,

are reverse-biased Thererore, no drain current flows Suppose a small +VG is applied at the gate The

positive voltage at the top of the Si02 dielectric would induce negativc charges below this layer These negative charges will deplete the holes of the P­ epilaycr, exposing ncgatively charged acceptor ions i.e a depletion layer will be tormed just below the gate as shown in Fig 17 A further increase in +VG

will induce more and more negative charges below the gate, with the result being a copious accumulation of negative charges below the gate forming an induced­ layer of negative charges constituting a "channel" (induced channel) between the source and thc drain as

shown in Fig 1

Fig 18

~

( \ •••• - D ep ! c t o n l a ye r r' ,cp i

N-type Induced Channel Once the channcl is induced between the Sand

0 , the electrons flow through this channel, with the result bcing a drain current Therefi.)re, the induced channcl constitutes an ohmic path The conductivity of this channel is dependcnt on the magnitUde of Ve In other words, the channel conduc­ tivity is modulated by VG Thcreforc, the morc the

VG , the more will be Il) Thus, the device operates in enhancement lllode

2

10

0

MOSFET OUTPUT CHARACTERISTICS

Fig 19

Saturation

locus region

Pinch-otT

lOS

~

IV d : Increasing

Vos

Vp VG- VT

Analysis: Let voltage at x along the channel be Vex)

I[)= V Ve- VT -Vo/2 Vo=>ThlsIoversus

VI) is valid as long as Vc; - Vex) > VT Note: L: Channel

length At some gate voltage VC;I with Vex) = VI), the

channel is turned open and the flow of charges along the

channel becomes constant, i.e at Vo = VC;I - VT ,

~cCg )2 VC;-VT

I =-' -"'O_L- _

_u_1I)_I => - C _V_o

uVe v gm -~ g L2

1>

~ Transconductance of the MOSFET

~cCg( )2 Vo

I

Il)s=Illv =V -v = - - VC;-VT =gm­

Fig 20

, VGs= VT

Region Region

VG

NMOS output

Ohmic Saturation

\

V DS characteristics

-Ohmic Region (Triode Region)

Here VOS S; V GS - VT and the V -I characteristic is

10 = Kn'2(VGS - V'r)VIlS - V20s), where

K = ~/'oEox W = ~.Cox (W) and II = surface

ox

mobility of electrons: ~c = 800cm2 I volt-sec (in Silo

Eo = permittivity of free space ( = 8.85 x 10 -14 F/cm)

Eox = dielectric constant of Si02 ('" 4);

tox = thickness of the oxide; Cox = EoEoxLW/tox

Co,: Capacitance of SiOz layer

Dividing locus between saturation and ohmic regions is

given by substituting Vos = (Ves - VT):

10 - Kn V os - - - - V os'

2L This locus is shown by the dotted line in Fig 20

-SATURATION REGION: Here, VI)S ;?: Ves - VT ,

and the current II) is approximately constant as shown

in Fig 20 The transfer characteristic is obtained by

replacing Vos by Ves - VT ; 10 = Kn (Ves - VT)2 A

plot of the transfer characteristic is shown in Fig 20

-CUTOFF REGION: Here, Vc;s < VT, and thus 10

= O The device is OFF in this region and is used in

switching applications in this mode

DIFFUSED-CHANNEL

(DEPLETION-TYPE) MOSFET

-Diffused-channel MOSFET can be operated both as

depletion mode or as enhancement mode device

-The device has a thin N-type layer of the same

conductivity as source or drain and is diffused

below the gate

- When the gate has a small negative bias, the resulting

positive charges in this diffused region cause the depletion

layer (channel conductance) to be reduced Thus, negative

bias on gate enables depletion mode operation

G ? VG

+++1+++

DifTuscd N-typc layer: Chanllel

P-cpitaxial s ubstrate

Depletion mode

- When a positive bias is applied, more electrons are drawn into the channel causing more carrier population, i.e

channel conductance is increased Hence, more current would now; or, an increase in +Ve would increase [0 => enhancement mode operation V-I character­

istics indicate that circuit operations of diffused-channel MOSFET are similar to thosc of JFET

MOSFETs are shown in Fig 22

Fig 22

D D

G ~ G ~ G o19 G o19

Fig 23

Approximate Low Frequency Equivalent Circuits

s~s

Fig 24

High Frequency Equivalent Circuit of a JFET

t

f s

G

Cd : t

~ ' c " g",v , +

drifting under the influence of an electric field, whereas

in the bipolar transistor, current is transported by means

of diffusing minority carriers Since drift velocities in semiconductors are usually very much higher than diffusion velocities, carrier transit times are much

reason, one might expect FETs to have a much more

A limitation to the high-frequency performance or the switching speed of a FET is the gate-channel capacitance, which must be charged via the channel resistance The

can be derived from the equivalent circuit and equals gm/21tCg, is normally taken as afigure ofmerit to indicate the high-frequency response of a particular device

-.!!! =Il ~;C g: Total gate capacitance

Cg e L2

3

COMMON-GATE AMPLIFIER

Vo (1l+ I )RL •

Av = '- ",gmRLfor

vin rd +RL

~ = gmrd» I, rd RL

V RI +rd 1

Rj =_1_11 = _ _ ~ _ _ " ' _ for rd» RL ;

il 11+1 gm

Vo

Ro = -:- = rd + (~+ I)Re '" rtl + ~RG

'2

Fig 25 Common-Gate Amplifier

(;

(~ : Amplitication factor) i···

i

Note: For CG configuration, the output resistance is

resistance is relatively low Voltage gain is dependent on

RL , and its maximum value is about~ CG configuration

in FET is the counterpart orCB configuration in BJTs

COMMON-SOURCE AMPLIFIER

A common-source (CS) FET amplilier (with the dc biasing circuitry) and its small signal equivalent circuit are shown in Fig 26

Fig 26 , - _ , -+"VI) D +.,.- + o

COMMON-DRAIN AMPLIFIER

A common-drain (CD) FET amplifier (with the biasing circuitry) and its small-signal equivalent circuit are shown in Fig 27

Ro=

Av=

(I+~)RL +rd l+gmR L For gmRL » I, the voltage gain is close to unity The CD configuration is thererore called the sour ce follower (SF), since the source voltage follows the input gate signal The CS conl1guration in FET is the counterpart of the CC configuration in 8.IT

C,

> - +- -o VQ

COMPARISON OF FET AMPLIFIERS

~ Fig 28 Fig 31

Ra + I

c=o I D V,,'" in;\;, V DD *SF=Sourcc Follower

Olher N-~~l ~~ ~el

Yin R D

~ ,t :!: YVA + MOSFET

I"

G o j <> 8

-Output impedance of the differential amplifier tends

-Application: To amplify ditferential signal(s) from

transducers / sensors

- Satration Region: Vus ~ VGS - VT (b) When substratelbody "8"

- RI can be adjusted to achieve null-offset

, -_._ -.

- VA: A

Fig 32

Common-Source Parameters Amplifier

~pC,,~ W

2-L-Symbol

Go -,l' 0 8

V;n = VGS

(b) 0

A = tl(Voutl =-g R

v i1(V;nl - m I)

-AC-COUPLED NON-INVERTING AMPLIFIE R:

(b) When substratelbody "8" dc offset considerably

connected to source - Provision of R3 is mandated to facilitate continuous

-Satration Region: VOS ~ VGS - VT

Note: Different states and regions of operation: dc path for each of the input terminals

io = K(VGS - VT)2(l + AVos)

=> Same as for P-channel JFET -Triode Region: Vos ~ VGS - VT

iu =

P-CHANNEL ENHANCEMENT MOSFET

Fig 33

N-CHANNEL DEPLETION MOSFET

Common-Source Parameters

Fig 30

T

Common-Source Parameters ­

Amplifier

-vDU

As for r=' -H ~_ ov OUI

P-Channel Other -OP-AMPS in practical circuits offer performance

RD Parameters D e i ction

Iln Co~ W

K 2L MOSFET matching theoretical estimations

-An OP-AMP consists of:

Others N-C h nncl

As for

(a) An inverting input terminal;

(b) A non-inverting input terminal;

A = i1(Vout l "'-g R

v ~(Vin) - m 0

v tl(V;nl - m 0 G<>-l~ - V;n2) ; A is known as open-loop gain, which is very

( b) S

large (Ideally A ~ ~; in practice, A - 104 to 1 6) (a) Conventional

~ (a) Conventional (b) When substratelbody "B" - An ideal OP-AMP has an infinite input impedance (at

connected to source

Note: Different states and regions of

Z Note: Different states and regions of operation: => Same as for P-channel JFET - For inverting input, V,,IV;III =

W

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P-CHANNEL JFET

Fig 29

Common-Source

Amplifier

-On-State: VGS ~ VT

Parameters

'0

V ns Symbol

i Differential Amplifier i

L O

V OUl