Large signal modeling of gaas MESFET device 1

List of Tables Table 3.1 Parasitic Capacitances Calculated from the Model Proposed in [94] for A 2*100µm and A 2*150µm MESFET Devices ...53 Table 3.2 The RMS Variation of Calculated Cpd

DEVICE

MA JINGYI

(M.Eng, BEIJING INSTITUTE OF TECHNOLOGY, P.R.CHINA)

A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2002

Special thanks go to Professor Xu QunJi and Dr Lin FuJiang for their encouragement and helpful discussions in circuit design, device physics and measurement techniques

I also wish to thank Teo T C., Sing C H., Wu Bin and Madam Lee in microwave and MMIC lab, for their kind helps and assistances in using the test facilities, conducting device and circuit measurement, and kindly providing me with useful documents

My gratitude also goes to all the friends in microwave division, for their kind help, and for the wonderful time we shared together

Finally, I would like to thank my family, for their endless support and encouragement

Table of Contents

Summary vi

List of Tables viii

List of Figures x

List of Symbols xvii

List of Publications Arising from Present Thesis Research Work xix

Chapter 1 Introduction 1

1.1 History 1

1.2 Device Model 4

1.3 Objectives 5

1.4 Scope of this work 6

Chapter 2 Basic Operation and Device Models 11

2.1 Device Description 12

2.2 Physical Meaning of Small-Signal Equivalent Circuit Elements 14

2.2.1 Parasitic Inductances Lg, Ld and Ls 16

2.2.2 Parasitic Resistances Rs, Rd and Rg 16

2.2.3 Parasitic Capacitances Cpg and Cpd 16

2.2.4 Capacitances Cgs, Cgd and Cds 17

2.2.5 Transconductance gm 17

2.2.6 Output Conductance gds 18

2.2.7 Charging Resistance Ri 18

2.2.8 Transconductance Delay 19

2.3 Nonlinear Properties in Large Signal Models 19

2.4 Second Order Effects 20

2.4.1 Frequency Dispersion 20

2.4.2 Self-heating Effect 21

2.4.3 Sub-threshold Effect 23

2.5 Existing Small Signal Modeling Approaches 24

2.6 Existing Nonlinear MESFET Models 26

2.6.1 Physical Model 27

2.6.2 Empirical Model 29

2.6.3 Table-base Model 33

2.6.4 Other Approaches 34

Chapter 3 Small Signal Modeling of GaAs MESFET 36

3.1 Introduction 36

3.2 De-embedding Technique 37

3.2.1 De-embedding of Series Parasitics 38

3.2.2 De-embedding of Parallel Parasitics 40

3.2.3 De-embedding Procedure of A Typical MESFET Device Parasitics 41

3.3 Objective Function 43

3.4 Cold-FET Techniques 44

3.4.1 Extraction of Parasitic Resistances and Inductances 45

3.4.2 Extraction of Parasitic Capacitances 52

3.5 An Improved Model for MESFET Parasitic Capacitance Extraction 57

3.5.1 Introduction 57

3.5.2 The Improved Model 59

3.5.3 Numerical Results 63

3.5.4 Conclusion 65

3.6 Hot-FET Techniques 65

3.6.1 Analytical Method and Optimization Method 66

3.6.2 Multi-Plane Data Fitting Approach 67

3.7 Comparison of Small Signal Equivalent Circuit 70

3.8 Numerical Results and Discussions 72

3.8.1 Equivalent Circuit Elements Determination 73

3.8.2 Cold-FET Extraction Results 74

3.8.3 Multi-Plane Data Fitting Extraction Results 77

3.9 Conclusion 86

Chapter 4 A New Drain Current Model for GaAs MESFET 89

4.1 Introduction 89

4.2 An Examination of the Existing Empirical Drain Current Models 91

4.3 The New Model 98

4.4 Numerical Results and Discussions 107

4.4.1 Model Parameter Extraction 107

4.4.2 Modeling Results and Discussions 109

4.4.3 Amplifier Design Result 114

Chapter 5 A New Charge Model for GaAs MESFET 119

5.1 Introduction 119

5.2 A Study of Some Existing Empirical Gate Capacitance Models 121

5.2.1 Diode Junction Capacitance Model 122

5.2.2 Statz Model 123

5.2.3 Discussions 125

5.3 The New Model 130

5.4 Numerical Results and Discussions 133

5.4.1 Model Parameter Extraction 133

5.4.2 Modeling Results and Discussions 135

Chapter 6 Model Verification 146

6.1 S-Parameter at Multi-Bias Points 146

6.2 Large Signal Performance Verification 150

6.3 A GaAs MESFET MMIC Power Amplifier 152

6.3.1 MMIC Power Amplifier Circuit 152

6.3.2 Device Modeling Result 155

6.3.3 Comparison of Simulation and Measurement Amplifier Results .162

6.4 Conclusion 167

Chapter 7 Conclusions 169

Bibliography 174

Appendix A Large Signal Empirical MESFET Models 183

A.1 Curtice-Quadratic GaAs MESFET Model 183

A.2 Curtice-Ettenberg GaAs MESFET Model 184

A.3 Advanced Curtice Quadratic GaAs MESFET Model 184

A.4 Statz Model 185

A.5 Materka-Kacprazk GaAs MESFET Model 187

A.6 Chalmers Model 188

A.7 Rodriguez Model 188

A.8 TriQuint’s Own Model 189

A.9 TOM-2 GaAs MESFET Model 189

A.10 Model Proposed by V.I Cojocaru and Brazil 191

A.11 Tajima MESFET Model 191

A.12 Parker MESFET Model 192

Appendix B TEE Network and PI Network Conversion 195

B.1 TEE Network to PI Network Conversion 195

B.2 PI Network to TEE Network Conversion 195

Appendix C Small Signal Parameter Extraction Formulation 197

C.1 Circuit Topology with Seven Intrinsic Elements 197

C.1.1 Analytical Method 197

C.1.2 Least-Square Error Function with Frequency as the Weighting Factor 199 C.2 Circuit Topology of Eight Intrinsic Elements with Cdc Introduced

200 C.2.1 Analytical Method 201 C.2.2 Least-Square Error Function with Frequency as the Weighting Factor 202 C.3 Circuit Topology of Eight Intrinsic Elements with Rgd Introduced

204 C.3.1 Analytical Method 205 C.3.2 Least-Square Error Function with Frequency as the Weighting Factor 206

Summary

GaAs MESFET is the most widely used GaAs device GaAs ICs and MMICs using MESFET technology have found a wide range of applications in wireless, optical, broadband data and satellite communication, as well as in industrial, automotive and military market GaAs MESFET dominates in such applications as power amplifiers, low noise amplifiers and switches It is also widely used in both analog and digital ICs The accuracy of high speed, RF and microwave circuit design

is mainly determined by the accuracy of the device model Therefore, reliable modeling methodology and accurate device models are important and in great demand Extensive works have been done in the field of GaAs MESFET modeling Many models have been proposed However, experience shows that they are generally only capable of modeling device performance under certain specific condition In this work, a detailed study of GaAs MESFET large signal models for nonlinear microwave circuit design is carried out Although the main focus of the study is on nonlinear modeling, the small signal modeling methodology is also investigated An improved model for parasitic capacitances extraction is proposed Unlike the conventional parasitic capacitance model, the resulting Cpd remains the same for different bias voltage, which is in agreement with theory Different methods for extracting small-signal equivalent circuit parameters were studied, and a reliable extraction procedure is proposed A new empirical model is developed to more accurately model drain current I-V characteristics of GaAs MESFET transistor The newly proposed model expressions are original Moreover, unlike some commonly used models that have a conditional pinch-off and are not continuous over the entire

device operation region, the new model and its derivatives are continuous under all bias conditions It is capable of accurately modeling the device current-voltage behavior at different operating regions Most specially, device operation around the pinch-off region is more accurately described, and the sub-threshold effect is modeled A new gate terminal charge model for Cgs and Cgd description is also proposed The resultant model is very accurate in describing device operation Its accuracy in linear region, saturation knee region, and near Vds=0 is greatly improved The model expressions and its derivatives are continuous over the entire device bias range And most importantly, gate charge conservation law is observed for the new model The new nonlinear current and charge models are implemented into circuit simulator for various MESFET devices An MMIC power amplifier was designed and fabricated with the aid of the new models Simulated and measured results are employed to evaluate the new model Detailed model verification is discussed

List of Tables

Table 3.1 Parasitic Capacitances Calculated from the Model Proposed in [94] for A

2*100µm and A 2*150µm MESFET Devices 53

Table 3.2 The RMS Variation of Calculated Cpd under Three Different Vgs Bias Using Dambrine’s Model, White’s Model and the Improved Model (1-10GHz) 65

Table 3.3 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use White’s Model 74

Table 3.4 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use Dambrine’s Model 74

Table 3.5 Parasitic Elements Extracted from Procedure 1, Cpg and Cpd Use the Improved Model 74

Table 3.6 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use White’s Model, Vgs=0.4V, Vds=5.0V 75

Table 3.7 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use Dambrine’s Model, Vgs=0.4V, Vds=5.0V 75

Table 3.8 Intrinsic Elements Calculated from Procedure 1, Cpg and Cpd Use the Improved Model, Vgs=0.4V, Vds=5.0V 75

Table 3.9 Parasitic Elements Extracted from Procedure 3, Equivalent Circuit

Table 3.12 RMS Error of Modeled S-parameter, Equivalent Circuit Elements

Extracted from Procedure 3, Calculation Made for Three Small Signal Equivalent Circuit Topology Vgs=-2.0-0.5V, Vds=0.0-4.0V, f=1-30GHz 79

Table 4.1 The Drain Current Expressions of Some Existing GaAs MESFET Models

Table 4.4 Parasitic Element Values of the Small-signal Equivalent Circuit (Fujitsu

Table 4.7 Comparison of the Maximum Fitting Error and RMS Error of the New

Model with Curtice Model, Chalmers Model and Parker Model (2*150μm Wafer device) 113

Table 5.1 Comparison of Cgs Accuracies of Diode Junction Capacitance Model and Statz Model for a 2*150μm GaAs MESFET 129

Table 5.2 Comparison of Cgd Accuracies of Diode Junction Capacitance Model and Statz Model for a 2*150μm GaAs MESFET 129

Table 5.3 Model Parameters for the New Gate Charge Model (2*150µm Wafer Device) 134

Table 5.4 Comparison of Cgs Accuracies of Diode Junction Capacitance Model, Statz Model and the New Model for a 2*150μm GaAs MESFET 143

Table 5.5 Comparison of Cgd Accuracies of Diode Junction Capacitance Model, Statz Model and the New Model for a 2*150μm GaAs MESFET 144

Table 6.1 MMIC Power Amplifier Design Specification 153 Table 6.2 List of the Equipments Used during the MMIC Power Amplifier

Measurement 163

Table 6.3 Measured and Simulated MMIC Power Amplifier dB(S11) Response at 8.5GHz, 9.5GHz and 10.5GHz Respectively 167

List of Figures

Figure 2.1 Cross-sectional view of a MESFET .12

Figure 2.2 Basic current-voltage characteristics of a MESFET 13

Figure 2.3 MESFET small-signal equivalent circuit including parasitic elements 15

Figure 2.4 Physical origin of the MESFET small signal model .15

Figure 2.5 Equivalent circuit for MESFET large-signal model .19

Figure 2.6 Measured DC drain current as a function of Vds for a 16*125µm GaAs MESFET, Vgs=-2.7V-0.5V 22

Figure 2.7 Output conductance as a function of Vds for a 16*125µm GaAs MESFET, Vgs=-1.1V-0.5V (● Vgs=-1.1V,   Vgs=-0.7V —— Vgs=-0.3V,

-Vgs=0.1V, ο Vgs=0.5V) 22

Figure 2.8 Measured drain current characteristics around pinch-off region, Vpinchoff = -1.21V 24

Figure 3.1 Adding of device parameter and the series parasitic elements Z-matrices .38

Figure 3.2 The Z matrices of the parasitic components Zparas1 and Zparas2 .39

Figure 3.3 The matrix of a TEE structure 39

Figure 3.4 Adding of device parameter and the parallel parasitic elements Y-matrix .40

Figure 3.5 The matrix of a PI structure 41

Figure 3.6 De-embedding method for extracting intrinsic Y matrix 42

Figure 3.7 Circuit topologies showing parasitic elements location 44

Figure 3.8 Small-signal equivalent circuit with floating drain at Vgs>Vbi>0 46

Figure 3.9 Real and imaginary parts of Z parameters versus frequency, 4*50μm MESFET (Vgs>Vbi, floating drain, Z11, —— Z12, ○○○ Z21, ●●● Z22) (a) Real parts, and (b) Imaginary parts 49

Figure 3.10 Real and imaginary parts of Z parameters versus frequency, 16*125μm MESFET (Vgs>Vbi, floating drain, Z11, —— Z12, ○○○ Z21, ●●● Z22) (a) Real parts, and (b) Imaginary parts 50

Figure 3.11 Real and imaginary parts of Z parameters versus frequency, 2*100μm

MESFET (Vgs>Vbi, floating drain, Z11, —— Z12, ○○○ Z21, ●●● Z22) (a) Real parts, and (b) Imaginary parts 51

Figure 3.12 Real part of Z11 versus 1/Igs for a 2*100μm MESFET (Vgs>Vbi>0,

floating drain) .51

Figure 3.13 Imaginary parts of Y parameters against frequency Measured at Vds=0,

Vgs=-5.0V<Vp, 0.5μm gate length ( Y11, —— Y12, ○○○ Y21, ● Y22) (a) 2*150μm MESFET, and (b) 2*100 μm MESFET 54

Figure 3.14 Parasitic capacitance extraction using Dambrine’s and White’s model (—

—Vgs=-5.0, Vgs=-2.0, ● Vgs=-1.7) (a) 2*100μm MESFET, and (b) 2*150μm MESFET 56

Figure 3.15 Measurement results for Im(Y22)+Im(Y12), Im(Y22)+2*Im(Y12), and

Im(Y22)+(1+α)*Im(Y12) under three different Vgs biasing, with α=0.3 (

Vgs=-5.0V, •••• Vgs=-2.0V, - Vgs=-1.7V) .58

Figure 3.16 Equivalent circuit of the improved model for MESFET biasing at Vgs<Vp

and Vds=0 59

Figure 3.17 Cross section view of MESFET at Vgs<Vp and Vds=0, showing physical

origin of the improved model, PI network .60

Figure 3.18 Equivalent circuit of the improved model for MESFET biasing at Vgs<Vp

and Vds=0, intrinsic elements in TEE topology 61

Figure 3.19 Cross section view of MESFET at Vgs<Vp and Vds=0, showing physical

origin of the improved model, TEE network .61

Figure 3.20 Calculated α under different Vgs (Vgs<Vp) value ( α calculated with

cold-FET S-parameter of Vgs=-5.0V and Vgs=-2.0V, —— α calculated with cold-FET S-parameter of Vgs=-5.0V and Vgs=-1.7V) 62

Figure 3.21 Calculated Cpd by the improved model with three different biasing

conditions (Vds=0, —— Vgs=-5.0, -Vgs=-2.0V, ● Vgs=-1.7V) (a) 2*100μm MESFET, and (b) 2*150 μm MESFET 64

Figure 3.22 FET model under passive pinch-off condition used for generating initial

values of extrinsic elements .68

Figure 3.23 Typical 15-elements FET model for hot-FET optimization .68 Figure 3.24 Flow chart of small-signal extraction with multi-plane data-fitting

Figure 3.27 Small signal equivalent circuit topologies of eight intrinsic elements,

Figure 3.32 Calculated results for gm (a) small signal equivalent circuit as in Figure

3.25, (b) small signal equivalent circuit as in Figure 3.26, and (c) small signal equivalent circuit as in Figure 3.27 86

Figure 4.1 Equivalent circuit for MESFET large-signal model .89 Figure 4.2 Measured and simulated drain current characteristics for a 2*150μm GaAs

MESFET using Curtice Quadratic model, Advanced Curtice model, and Curtice Cubic model (Vgs=-1.4V – 0.5V, •••• Curtice Quadratic model, οοοοAdvanced Curtice model, Curtice Cubic model,  Measurement data) (a) Ids vs Vgs characteristics, and (b) Ids vs Vds characteristics .93

Figure 4.3 Measured and simulated drain current characteristics for a 2*150μm GaAs

MESFET using Materka model, TriQuint Own model, and Chalmers model (Vgs=-1.4V – 0.5V, •••• Materka model, οοοο TriQuint Own model, Chalmers model,  Measurement data) (a) Ids vs Vgs characteristics, and (b) Ids vs Vds characteristics .95

Figure 4.4 Measured and simulated drain current characteristics for a 2*150μm GaAs

MESFET using Rodriguez model, Parker model, and Statz model (Vgs=-1.4V – 0.5V, •••• Rodriguez model, οοοο Parker model, Statz model, Measurement data) (a) Ids vs.Vgs characteristics, and (b) Ids vs Vds

Figure 4.7 Ids and gds described by the new model ( modeled Ids, οοοο measured

Ids, - modeled gds, •••• measured gds) 103

Figure 4.8 Comparison between gds predicted by the new model based on DC Ids

measurement, and gds from high frequency measurement ( modeled gds,

•••• measured gds) .104

Figure 4.9 Second order derivative with respect to Vds described by the new model

104

Figure 4.10 Comparison of measured and simulated Ids vs Vgs and gm vs Vgs

characteristic based on the new model (2*150μm wafer device) 105

Figure 4.13 Comparison of measured and modeled drain current characteristics by the

new model, 16*125μm MESFET wafer device, Vgs=-3.1 V – 0.5V 109

Figure 4.14 Comparison of measured and modeled drain current characteristics by the

new model, 4*25μm MESFET wafer device, Vgs=-3.0V – 0.5V 110

Figure 4.15 Comparison of measured and modeled drain current characteristics of the

new model, Parker model, Chalmers model and Curtice model, 2*150μm wafer device .111

Figure 4.16 Comparison of measured and modeled drain current characteristics

around pinch-off region Calculations are based on the new model, Vpinchoff = 1.21V, 2*150μm wafer device .112

-Figure 4.17 Comparison of measured and simulated gm characteristic close to

pinch-off based on the new model (2*150μm wafer device) 113

Figure 4.18 Comparison of measured and simulated I-V characteristic of Fujitsu

FLC103WG based on the new model .115

Figure 4.19 Comparison of measured and simulated S21 of the amplifier 115

Figure 4.20 The measured third order inter-modulation distortion of the amplifier,

(Pin=10 dBm) .116

Figure 4.21 The simulated third order inter-modulation distortion of the amplifier,

(Pin=10 dBm) .116

Figure 4.22 The measured third order inter-modulation distortion of the amplifier,

(Pin=–10 dBm) .117

Figure 4.23 The simulated third order inter-modulation distortion of the amplifier,

(Pin=–10 dBm) .117

Figure 5.1 Measured and simulated Cgs characteristics using diode junction

capacitance model for a 2*150μm GaAs MESFET (——modeled, Measured Vgs=0.0V, οοοο Measured Vgs=-0.5V, ×××× Measured Vgs=-1.0V,

●●● ● Measured Vgs=-1.2V, +++ Measured Vgs=-1.4V, ∗∗∗∗ Measured Vgs2.0V, Vds=0-4.0V) .126

=-Figure 5.2 Measured and simulated Cgs characteristics using Statz capacitance model

Measured Vgs=-0.5V, ×××× Measured Vgs=-1.0V, ●●● ● Measured Vgs1.2V, +++ Measured Vgs=-1.4V, ∗∗∗∗ Measured Vgs=-2.0V, Vds=0-4.0V) .127

=-Figure 5.3 Measured and simulated Cgd characteristics using diode junction

capacitance model for a 2*150μm GaAs MESFET (——modeled, ●●● ● Measured Vgs=0.0V, Measured Vgs=-0.5V, οοοο Measured Vgs=-1.0V,

∗∗∗∗ Measured Vgs=-1.4V, Vds=0-4.0V) .127

Figure 5.4 Measured and simulated Cgd characteristics using Statz capacitance model

Measured Vgs=-0.5V, οοοο Measured Vgs=-1.0V, ∗∗∗∗ Measured Vgs1.4V, Vds=0-4.0V) .128

=-Figure 5.5 Cgs extracted from S-parameter as a function of Vgs and Vds (Vgs

=-2.0-0.5V, Vds=0.0-4.0V) 133

Figure 5.6 Cgd extracted from S-parameter as a function of Vgs and Vds (Vgs

=-2.0-0.5V, Vds=0.0-4.0V) 134

Figure 5.7 Comparison between modeled Cgs using the new model and Cgs extracted

from S-parameter for a 2*150μm GaAs MESFET (——modeled, Measured Vgs=0.0V, οοοο Measured Vgs=-0.5V, ×××× Measured Vgs=-1.0V,

●●● ● Measured Vgs=-1.2V, +++ Measured Vgs=-1.4V, ∗∗∗∗ Measured Vgs2.0V, Vds=0-4.0V) .135

=-Figure 5.8 Comparison between modeled Cgd using the new model and Cgd extracted

from S-parameter for a 2*150μm GaAs MESFET (——modeled, ●●● ● Measured Vgs=0.0V, Measured Vgs=-0.5V, οοοο Measured Vgs=-1.0V,

∗∗∗∗ Measured Vgs=-1.4V, Vds=0-4.0V) .136

Figure 5.9 Cgs vs Vgs and ∂C gs /∂V gsvs Vgs characteristics for a 2*150μm wafer

device ( Cgs by the new model, - ∂C gs /∂V gs by the new model, ••••

Cgs measured) .137

Figure 5.10 Cgd vs Vgs and ∂C gd /∂V gs vs Vgs characteristics for a 2*150μm wafer

device ( Cgd by the new model, - ∂C gd /∂V gs by the new model, ••••

Cgd measured) .139

Figure 5.11 Cgs vs Vds and ∂C gs /∂V ds vs Vds characteristics for a 2*150μm wafer device ( Cgs by the new model, - ∂C gs /∂V ds by the new model, •••• Cgs measured) .140

Figure 5.12 Cgd vs Vds and ∂C gd /∂V ds vs Vds characteristics for a 2*150μm wafer device ( Cgd by the new model, - ∂C gd /∂V ds by the new model, •••• Cgd measured) .141

Figure 5.13 Comparison of measured and modeled Cgs data (New model,

-Statz model, −−−− Diode junction capacitance model, •••• Measured data) 141

Figure 5.14 Comparison of measured and modeled Cgd data (New model,

-Statz model, −−−− Diode junction capacitance model, •••• Measured data) 142

Figure 5.15 Comparison between measured and simulated S-parameter, with Cgs and Cgd derived from the new model, Vgs=0.0V, Vds=2.0V .144

Figure 6.1 RMS errors of S-parameter calculated from the large signal model as a function of bias (a) S11, (b) S12, (c) S21, and (d) S22 148

Figure 6.2 RMS errors of S-parameter calculated from small signal equivalent circuit at different bias (a) S11, (b) S12, (c) S21, and (d) S22 149

Figure 6.3 Single-tone large signal test result for a 2*150µm MESFET ( Simulation, ••••Measurement) (a) Pout/Pin behavior for the first three harmonics, and (b) gain compression .152

Figure 6.4 Schematic of the MMIC power amplifier .153

Figure 6.5 Photo of the GaAs MMIC power amplifier layout 154

Figure 6.6 Large signal model for the GaAs MESFET 155

Figure 6.7 Comparison between modeled and measured DC I-V performance for the 10*100µm MESFET (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured,  modeled) 156

Figure 6.8 Comparison between modeled and measured DC I-V performance for the 12*100µm MESFET (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured,  modeled) 156

Figure 6.9 Comparison between modeled and measured DC I-V performance for the

16*100µm MESFET (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured, modeled) 157

Figure 6.10 Comparison of modeled and measured pulse I-V result for the 10*100µm

device (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured,  modeled) 158

Figure 6.11 Comparison of modeld and measured pulse I-V resultfor the 12*100µm

device (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured,  modeled) 158

Figure 6.12 Comparison of modeled and measured pulse I-V result for the 16*100µm

device (Vgs = –3.0-0.5V, Vds = 0-10V, •••• measured,  modeled) 159

Figure 6.13 Comparison of modeled and measured gate capacitances at Vds=8.0V for

the 12*100µm device (Vgs = –2.5-0.25V, •••• measured,  modeled) 159

Figure 6.14 Modeled and simulated S-parameter for the 10*100µm MESFET (Vgs

=-1.0V, Vds=8V, f=0.5-20GHz, •••• measured,  modeled) (a) S11, (b)

S12*10, (c) S21/15, and (d) S22 .160

Figure 6.15 Modeled and simulated S-parameter for the 12*100µm MESFET (Vgs

=-1.0V, Vds=8V, f=0.5-20GHz, •••• measured,  modeled) (a) S11, (b)

S12*10, (c) S21/15, and (d) S22 .161

Figure 6.16 Modeled and simulated S-parameter for the 16*100µm MESFET (Vgs

=-1.0V, Vds=8V, f=0.5-20GHz, •••• measured,  modeled) (a) S11, (b)

S12*10, (c) S21/15, and (d) S22 .162

Figure 6.17 Top view of the chip with DC bias circuit .162 Figure 6.18 The complete set-up for the amplifier measurement and testing .163 Figure 6.19 Measured and simulated Pout - Pin behavior of the MMIC power amplifier

Figure 6.22 Comparison between simulated and measured gain of the power

amplifier, Pin=10dBm, f=8.5-10.5GHz (•••• Measured,  Simulated) 166

Figure B.1 TEE network to PI network conversion .195 Figure B.2 PI network to TEE network conversion .195

List of Symbols

feedback current

each side of the gate in the improved gate capacitance model

the new gate charge model

device

device

gate-to-source bias applied

device

Rgd Resistor introduced in some small signal equivalent circuits to

fit the Y12

Pin Input power for device and amplifier measurement

S11,S12,S21,S22 S-parameter of the device

Vpinchoff,VT0, Vp Pinch-off or threshold voltage of a MESFET device

Z11,Z12,Z21,Z22 Z-parameter of the device

Y11,Y12,Y21,Y22 Y-parameter of the device

model

List of Publications Arising from Present Thesis Research Work

Journal Paper

[1] B.L Ooi, J.Y Ma, and M.S Leong, “An Improved But Reliable Model for MESFET Parastics Capacitance Extraction,” IEE Proceedings – Microwaves, Antennas and Propagation accepted

[2] Ban-Leong Ooi, J.Y Ma and M.S Leong, “A Novel Drain Current I-V Model for MESFET,” IEEE Transactions on Microwave Theory and Techniques, Vol.50, No.4, pp.1188-1192, April 2002

[3] B.L Ooi, J.Y Ma, and M.S Leong “A New MESFET Nonlinear Model,” Microwave and Optical Technology Letters, Vol.29, No 4, pp.226-230, May

20, 2001

[4] Q Xiao, B.L Ooi and J Ma, “A New Accurate Model for Drain-Gate Avalanche Current Source of GaAs MESFET,” Microwave and Optical Technology Letters, Vol.25, No.4, pp.269-271, May 20, 2000

[5] Q Xiao, B.L Ooi, and J Ma, “An Improved Chalmers Model for a GaAs MESFET,” Microwave and Optical Technology Letters, Vol.24, No.5, pp.311-

316, March 5, 2000

Conference Paper

[1] B.L Ooi and J.Y Ma, “An Improved But Reliable Model for MESFET Parastics Capacitance Extraction, ” 2003 IEEE MTT-S International Microwave Symposium Digest, pp A53-A56, Philadelphia, Pennsylvania, USA, June 8-13,

2003

[2] B.L Ooi and J.Y Ma, “An Improved But Reliable Model for MESFET Parastics Capacitance Extraction, ” 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp 567-570, Philadelphia, Pennsylvania, USA, June 8-10, 2003

[3] B.L Ooi, J.Y Ma, and M.S Leong, “A Robust and Accurate Drain Current I-V Model for MESFET,” Proceedings of 2001 Asia-Pacific Microwave Conference (APMC 2001), pp.236-239, Taipei, Taiwan, R.O.C

[4] J.Y Ma, B.L Ooi, M.S Leong, “ A Novel Nonlinear MESFET Model,”

Cambridge, Massachusetts, USA

[5] B.L Ooi, Ma Jingyi, P.S.Kooi and M.S.Leong, “Reliable Small-Signal GaAs FET Equivalent Circuit Extraction Based on DC and RF Measurements,”

Progress In Electromagnetics Research Symposium (PIERS 1999) Taipei, Taiwan

[6] J Ma, Q Xiao, B.L Ooi, X.D Zhou, S.T Chew, “GaAs FET Large-Signal Model for High Power Amplifier, ” Proceedings of 1999 Asia-Pacific Microwave Conference (APMC 1999), pp.642-645, Singapore

[7] T.H Ng, B.L Ooi, M.S Leong, J.Y Ma, H.S Ong, S.T Chew, “High Efficiency Power Amplifier Design Using a Simplified Approach,” Proceedings

of 1999 Asia-Pacific Microwave Conference (APMC 1999), pp.650-654, Singapore

[8] Zhang Jin, Jingyi Ma, Mahadevan K Iyer, Ban Leong Ooi, and Mook Seng Leong, “A Novel Electrical Performance Analysis for Leaded Packages, ” 7rd Topical Meeting, Electrical Performance of Electronic Packaging, New York, USA, October, 1998

Chapter 1

Introduction

GaAs MESFET is an important device for the microwave industry The device combines a relatively simple geometry with great versatility and excellent performance in many applications It is the key semiconductor device in MMIC technology and digital GaAs ICs In this introduction, the history of GaAs MESFET and the importance of MESFET nonlinear modeling are presented, followed by the objectives and the structure of this thesis

1.1 History

The first development of a prototype gallium arsenide field effect transistor (GaAs MESFET) using a Schottky gate was by Mead in 1966 [1] In 1967, a GaAs MESFET was first fabricated by Hopper and Lehrer [2] A significant step was made by Turner

et al in 1971 [3], when 1µm gate length GaAs MESFET was fabricated, giving fmax

equal to 50GHz and useful gain up to 18GHz With the development of the quality of GaAs materials and basic FET prototype technology, rapid progress was achieved for GaAs MESFET device in the direction of both low noise and high power applications The first low noise GaAs MESFET was reported by Leichti et al [4] in 1972 And later in 1973, the first high power GaAs MESFET was announced by FuKuta et al in Fujitsu [5] With the early progress of GaAs MESFET technology, this is followed by rapid improvement of the device performance Intensive studies have been done in increasing its output power, operating frequency, power added efficiency, as well as improving the distortion qualities and noise figure

In addition to the discrete FET area, there also has been rapid development in both monolithic microwave intergrated circuits (MMICs) and digital GaAs integrated circuits MMIC technology has become popular since middle 1970s, and the first GaAs digital IC was reported in 1974 [6]

In the late 70s and the 80s, the GaAs MESFET was developed mainly for low volume, high performance military and space based systems The manufacturing technology was not mature enough to support the cost and volume requirement for the consumer mass market By the early 1990s, however, GaAs MESFET manufacturing technology was maturing rapidly, cost was reduced As a result, GaAs technology became more competitive with other process technologies Since then, GaAs MESFET device and GaAs integrated circuits have found a wide range of applications, such as in wireless systems Now, the GaAs MESFET is widely used in different microwave and millimeter wave systems, and has become the most import active device in both hybrid and monolithic microwave integrated circuits (HMIC and MMIC) design Typical applications include both low noise and power amplifiers, as well as transfer switches, attenuators, oscillators, and mixers The demand for mobile and personal communication systems has increased the use of GaAs MESFET for high -speed digital and analog integrated circuits

Other transistor technologies have been developed to cover a variety of applications in high frequency application from 1GHz to more than 100GHz GaAs based heterojunction devices including high electron mobility transistor (HEMT) and heterojunction bipolar transistor (HBT) provide several performance advantages In the case of HEMT technology, it has the advantage of higher frequency performance (fT, fmax), and lower noise figure than that achievable by MESFET of similar gate length GaAs HBT technology has high transconductance, high power density, and

excellent matching of a bipolar transistor Also, the HBT transistor can operate from a single power supply GaAs HBTs are commonly used for high power amplification applications InP transistors (HBTs, HEMTs) will dominate at extremely high frequency where cost is of less importance Wide bandgap FETs will be used in high power amplifiers Their market share, however is small because SiC substrate is expensive, and SiC and GaN technology is still in an embryonic stage compare to GaAs Despite the superior performance of these technologies mentioned above, GaAs MESFET technology remains competitive for various applications Its performance is adequate for many areas, and has a lower cost

In recent years, GaAs MESFET technology is also facing serious competition from silicon and silicon-germanium technologies in RF and microwave applications CMOS continues to advance to smaller geometries SiGe BiCMOS gives good performance for RF and high speed Compared to silicon, GaAs has a higher electron mobility and peak drift velocity The electron velocity at low field is sufficiently high

so that high switch speed and therefore high cutoff frequency can be achieved The primary advantages for using GaAs over silicon are large transconductance, low ON resistance, and fast switching speed Unlike Silicon, semi-insulting GaAs substrate can be formed This contributes to the simple structure of the GaAs MESFET, and the high resistivity of the GaAs substrate results in very small parasitic capacitance GaAs technology also has the strength of integrating RF functions in stripline and coplanar design into MMICs The drawback of MESFET technology is a limitation related to the voltage swing limited by the gate-leakage current, this reduces the noise margin of the circuit On the other hand, silicon technologies have been more matured, and provide a higher level of integration Silicon technologies also have the advantage of integrating analog design with digital design This makes it possible to design single

chip ICs for mixed signal systems For SiGe devices, the low breakdown voltage limits their usage in power applications Compare to SiGe devices, the GaAs FET give more efficient power amplification In summary, Si and SiGe RF, high speed ICs are assuming an increasing portion of RF front-end for many wireless applications below 5GHz Their applications also cover highly integrated digital data transceivers and optical communications GaAs devices normally dominate when higher frequency and increased power requirement are addressed

GaAs MESFET is the workhorse of GaAs Technology Its gate length on the market ranges from 0.8µm to 0.25µm GaAs MESFET has wide applications even though it is facing strong competition from other device technologies

1.2 Device Model

Equally important as the device itself, is the circuit simulation approach With the development of GaAs FET and MMIC techniques, MMICs are widely available for commercial and military application Since MMICs are fabricated using very sophisticated process technology, they require a long process cycle to complete and the development cost is high In addition, due to hardware prototype limitations, it is usually impossible to access internal circuit points to make alterations when circuit performance is not satisfactory Due to the above reasons, it is very important to accurately design the circuit during the design stage, so as to closely correlate the design result with the achieved performance, thus facilitating circuit design and reducing the overall cost Commercially available computer-aided-design (CAD) software such as Agilent-ADS and Cadence SpectreRF are widely employed in microwave system design The operation of these CAD tools is largely based on an accurate prediction of the device involved in the circuit As a result, accurate models

for both active and passive devices and elements are needed Since GaAs MESFETs are the building blocks for many circuits, it is absolutely necessary to develop accurate GaAs FET models for circuit performance prediction

A number of different GaAs FET models exist, and each of them can be classified among several different categories When models are classified according to how they are derived, they can be grouped into physically based model, empirical model and experimental model When FET models are classified according to the type of performance predicted by them, they can be grouped into small-signal model, large-signal model

The empirical model can be easily implemented into circuit simulators Thus, they are most widely used by circuit designers and in device libraries Both small-signal and large-signal models are important for nonlinear MESFET modeling As mentioned earlier, power amplifiers are the main applications of GaAs MESFETs MESFET devices exhibit nonlinear behavior in power amplifiers Thus, accurate large signal MESFET models are particularly critical for the performance prediction of nonlinear microwave circuits Although much work has been done in large signal modeling of GaAs MESFET, accurate linear and nonlinear models are still in great demand

1.3 Objectives

The purpose of this study was to develop a new empirical large signal model for accurate description of the most important GaAs MESFET nonlinear behavior, including drain current I-V and gate capacitance characteristics The model should give an accurate representation of device operation under different bias conditions It

should be easily implemented into a circuit simulator, and the model parameters should be extracted with reasonable effort

Although the main focus of this work lies in large signal modeling, small signal modeling methodology is also studied This is because the small signal model is the basis of large signal modeling The goal of the investigation is to find a reliable procedure by which the small signal equivalent circuit element values can be accurately extracted Improvement is also made over some existing models for parasitic element extraction

1.4 Scope of this work

Chapter 2 provides a brief discussion of the operation of GaAs MESFET and a review of the existing models First, a basic description of the MESFET device is presented Topics addressed are the MESFET physical structure and different MESFET operation regions After examining the basic device operations, the small signal equivalent circuit and the physical original of the equivalent circuit elements are introduced This is followed by nonlinear properties in MESFET and some second order effects Finally, existing MESFET modeling approaches are discussed, including small signal models and nonlinear models An overview of the small-signal parameter extraction method, physical model, empirical model, and experimental model are presented Model advantage and disadvantage are also investigated and compared

Small signal modeling methodology and reliable model parameter extraction technique are the subject of Chapter 3 The main aim of this chapter is to provide an improved and more accurate small signal equivalent circuit parameter extraction process First, some important concepts for parameter extraction are addressed,

including de-embedding technique and the selection of an objective function This is followed by a discussion of small signal model parameter determination methodologies Both cold-FET and hot-FET techniques are covered Normally, parasitic capacitances are evaluated from cold-FET S-parameter measurement with

Vgs biased beyond pinch-off region Numerical results show that with most conventional parasitic capacitance extraction models, the calculated value for Cpd

varies with the Vgs value at which the capacitance is extracted This violates the assumption that Cpd is parasitic capacitance and should be independent of biasing voltage Based on this observation, an improved model for parasitic capacitance extraction was proposed This improved model effectively eliminates the dispersion

of Cpd on bias voltage, and provides a simple method for capacitor calculation The resulting parasitic capacitances are independent of bias, which is in agreement with theory Based on the discussions in the earlier sections, the following sections in Chapter 3 focus on the investigation and comparison of different small signal parameter extraction methods The discussion is supported by both cold and hot FET device S-parameter measurement In addition, three commonly used small signal equivalent circuit topologies are also employed in the investigation Parameter extraction is carried out for three different extraction procedures and for the three equivalent circuit topologies Numerical results are collected and compared As a result of the investigation, a reliable small signal parameter extraction process is proposed

The drain current I-V characteristic is one of the most important MESFET nonlinear properties Its accuracy is critical for the overall performance of the device model Chapter 4 focuses on GaAs MESFET drain current I-V models A discussion

on the most commonly used drain current models is first presented The performance

of these models is explored in terms of both accuracy and complexity Model parameters are extracted for all these models Numerical results are presented to illustrate their advantages and deficiencies A new drain current model and its formulation are described in the following section The new model has several advantages over the conventional models It provides a smooth transition to the pinch-off region The model formulations and their derivatives are continuous The sub-threshold effect is included, and is shown to be very accurate For those normal device operating regions, the new model also gives a better accuracy in predicting device behavior After introducing the new model, the remaining section of Chapter 4 focuses on the verification of the new model by numerical results Model parameters are extracted for various MESFET devices The performance of the new model is compared with the measured device response as well as with the modeling results using other available models In addition, the simulation and measurement result of a class AB amplifier designed with the new model are presented The proposed new drain current model is found to be very accurate, and it can be easily implemented into commercially available circuit simulators

Another important MESFET nonlinear characteristic is the nonlinear gate capacitance Cgs and Cgd The accuracy of the nonlinear capacitance model affects the simulation result for frequency dependent characteristics like S-parameter, as well as nonlinear properties such as distortion, harmonic analysis, third order inter-modulation product (TOI), and adjacent channel power ratio (ACPR) The MESFET charge model is the subject of Chapter 5 The chapter originates with a discussion of the most commonly used gate capacitance models The model formulation, its advantage and deficiency are explored The model accuracy is examined with the help

of measurement data Following the discussion of existing models, a new gate charge

model is proposed The new model is very accurate in describing device junction capacitances under various device operating conditions The performance prediction

in the linear region, saturation knee region, sub-threshold region and at Vds=0 is greatly improved over the conventional models The new model formulation and its derivatives are continuous Moreover, it obeys the terminal charge conservation law, which helps to solve the non-convergence problem in simulation Finally, device measurement data is employed to verify the accuracy of the new gate charge model The performance of the new model is also compared with other models

Chapter 6 focuses on the verification of the proposed new drain current I-V model and the new gate charge model As mentioned before, these are the most important nonlinear characteristics of MESFET The small signal modeling methodology outlined in Chapter 3, including the improved parasitic capacitance model and the reliable extraction procedure is employed to get the small signal equivalent circuit elements at multi-bias points The new nonlinear drain current I-V model and gate capacitance model are implemented into a circuit simulator The model evaluation includes S-parameter analysis at multi-bias points, gain compression and harmonic output response A MMIC power amplifier design result Measurement and simulation results are presented and compared

Chapter 7 is a summary of the work of this thesis Appendix A provides a full description of some existing empirical models The small signal parameter extraction formulations are presented in Appendix C These formulas are given for three different small signal equivalent circuits, and two different extraction methods

To summarize, a new MESFET empirical model with novel drain I-V characteristic equation and new capacitance-voltage expression is proposed Also,

improved small signal modeling methodology is demonstrated It is hoped that the study will lead to a more accurate large signal model for power amplifier design

Chapter 2

Basic Operation and Device Models

The overall electrical characteristics of the GaAs MESFET are mainly determined

by the electrical property of the semiconductor material and the nature of the physical contact to the material A knowledge of the device physical structure and properties is helpful for both device modeling and circuit design In the first part of this chapter, a brief description of MESFET operation is presented It covers the basic construction

of the device, the major operating regions, the small signal equivalent circuit, important nonlinear properties, and some second order effects

A variety of models have been proposed for the GaAs MESFET For small signal models, the difference of various models lies in the equivalent circuit topology selection and the way the equivalent circuit parameters are extracted For nonlinear models, according to how these models are derived, they can be classified into physical model, empirical model, experimental model and the more recently developed black-box model Various MESFET models have been used by both device and circuit designers Different applications and designs place different requirements

on the model Therefore, an understanding of the features of various modeling approaches is helpful for choosing the right model, and constructing new models for different application The second part of this chapter gives an overview of GaAs MESFET models, including the nonlinear and the small signal models

2.1 Device Description

A cross-section view of a MESFET is shown in Figure 2.1 [7], which illustrates its basic structure Three metal electrode contacts are shown to be formed onto a thin semiconductor active channel layer Source and drain are ohmic contacts, while gate

is a Schottky contact The gate metal forms a Schottky barrier diode, which gives a depletion region between the source and the drain The gate depletion region and the semi-insulating substrate form the boundary of the conducting channel A potential applied to the drain causes electrons to flow from the source to the drain Any potential applied on the gate causes a change in the shape of depletion region, and a subsequent change in current flow

+ + +

n - type active channel

Semi-insulating GaAs

Figure 2.1 Cross-sectional view of a MESFET

For microwave operations, the most critical dimension is the “length” of the gate along the carrier path The shorter the gate length, the higher becomes the signal frequency If the FET is to handle a large amount of signal current, the gate width must be increased appropriately

Linear region

Saturation region

Breakdown region

Figure 2.2 Basic current-voltage characteristics of a MESFET

The current-voltage relationships of a MESFET are illustrated in Figure 2.2 The channel current is plotted as a function of applied drain-source potential for different gate-source voltage levels Three regions of operation can be identified from the figure They are the linear region, the saturation region and the breakdown region In the linear region, current flow is approximately linear with drain voltage As drain potential increases, the depletion region at the drain end of the gate becomes larger than at the source end Since the device is taking constant current through the channel region, the electrical field increases as the channel region narrows, and therefore a related increase in electron velocity occur Increasing the drain voltage results in the electrons reaching their maximum limiting velocity at the drain end of the gate At this point, the current no longer increases with increasing drain bias, the device is said

to be saturated, and its operation enters saturation region Finally, when gate and drain

bias becomes very large, the device enters the breakdown region, where the drain current increases sharply

The Schottky barrier of the gate contact creates a layer beneath the gate that is completely depleted of free charge carriers No current can flow through this region since there are no free carriers exist in it Moreover, the existence of the depletion layer reduces the available cross-section area for current flow between the source and drain The depletion layer penetrates deeper into the active channel when reverse bias

is applied to the gate If the gate is made sufficiently negative, the depletion region will extend across the entire active channel and the conduction channel is closed This essentially allows no current to flow The gate potential to accomplish this phenomenon is known as the pinch-off voltage Vpinchoff And at this point, the device operates in pinch-off region

2.2 Physical Meaning of Small-Signal Equivalent Circuit Elements

Figure 2.3 shows a commonly used MESFET small-signal equivalent circuit topology This equivalent circuit has been served as an accurate small-signal model for virtually all GaAs MESFETs It has been shown to provide an accurate match to measured S-parameters through 26GHz, and could be used at higher frequency by adding some parasitic elements in the equivalent circuit The components inside the dashed line box are intrinsic device elements, while those outside the box are extrinsic device elements (parasitics)

The same equivalent circuit is shown in Figure 2.4, superimposed on a device cross section, indicating the physical origin of each equivalent circuit element

I ds =g m Ve -jωτ

Intrinsic Device

Figure 2.3 MESFET small-signal equivalent circuit including parasitic elements

Figure 2.4 Physical origin of the MESFET small signal model

Source

+

- V

2.2.1 Parasitic Inductances Lg, Ld and Ls

These parasitic elements are introduced to account for the inductances arising from metal contact pads deposited on the device surface and bonding wires on the package Parasitic inductances have an important impact on device performance especially at high frequency They must be accurately characterized Among Lg, Ld

and Ls, gate inductance Lg is usually the largest The typical values of Lg and Ld are

on the order of 5 to 10pH, source inductance Ls is often small, around 1pH for wafer and chip devices Bond wire and package will add additional parasitic inductances that in many cases dominate the device parasitics, and they must be accounted for in the circuit model

on-2.2.2 Parasitic Resistances Rs, Rd and Rg

Gate resistance Rg physically arises from the metallization resistance of the gate Schottky contact Resistances Rs and Rd are introduced to represent the contact resistances of drain and source ohm contacts as well as any bulk resistance leading to the active channel The values of these resistors are on the order of 1Ω [7] Investigation and measurements show a slight bias dependent behavior of these resistances However, they are normally considered to be constant in commonly used large-signal models

2.2.3 Parasitic Capacitances Cpg and Cpd

Parasitic capacitances arise primarily from metal contact deposited on the device surface and bonding wires on the package Like parasitic inductances, parasitic capacitances are related to the device structure For devices on wafer, Cpg and Cpd

could be ignored without introducing significant error to the equivalent circuit due to their small values (on the order of 1pF)

2.2.4 Capacitances Cgs, Cgd and Cds

The behavior of the depletion region beneath the gate of a MESFET is determined

by the bias applied to the device terminals The variation of the space charge region is caused by both gate-to-source potential and gate-to-drain potential Gate charge Qg is considered to be the space charge beneath the gate that varies with gate bias and drain bias

The gate-source capacitance Cgs is the derivative of the space charge with respect

to the gate-source bias Vgs, when the gate-drain voltage is constant:

const V

The incremental change in the output current Ids of a MESFET for a given change

in input voltage Vgs is measured by the device transconductance gm

Transconductance gm provides the intrinsic gain mechanism of the device Mathematically, it is defined as the derivative of drain current with respect to gate-source biasing voltage:

2.2.6 Output Conductance gds

The incremental change in output current Ids with the output voltage Vds is measured by the device output conductance gds Mathematically, the output conductance is defined as the derivative of drain current with respect to the drain-source biasing voltage:

2.2.7 Charging Resistance Ri

The charging resistance Ri is of questionable physical meaning, and its value is difficult to extract It is included in the equivalent circuit mainly to improve the fitting

of S11

2.2.8 Transconductance Delay

When gate biasing voltage changes, the drain current needs some time to respond

to this change The transconductance delay τ represents the delay inherent to this process The physically meaning of the transconductance delay is the time it takes for the charge to redistribute itself after a changing in gate voltage For microwave MESFET devices, τ is on the order of 1ps

2.3 Nonlinear Properties in Large Signal Models

Figure 2.5 Equivalent circuit for MESFET large-signal model

Large signal models are required for circuit simulation that is involved in predicting either large signal or nonlinear performance In Figure 2.5 a typical equivalent circuit for a MESFET large-signal model is shown The equivalent circuit

is divided into the extrinsic parasitic elements and the intrinsic device The extrinsic elements include Cpg, Cpd, Lg, Ld, Ls, Rg, Rd, and Rs, which are independent of biasing conditions The intrinsic device is enclosed by the dashed-line box All the nonlinear