Efficient modeling of power and signal integrity for semiconductors and advanced electronic package systems 1

90 4 Modeling for Multilayered Power-Ground Planes in Power Distri-bution Network 92 4.1 Modal Expansions and Boundary Conditions.. An accurate electromagnetic modeling of power distribu

EFFICIENT MODELING OF POWER AND SIGNAL INTEGRITY FOR SEMICONDUCTORS AND ADVANCED ELECTRONIC PACKAGE SYSTEMS

ZAW ZAW OO

(B.E.(Electronic),YTU; M.Eng.(ECE),NUS)

A THESIS SUBMITTEDFOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2008

super-I would also like to acknowledge the support and friendship super-I received from mycolleagues in Advanced Electronics and Electromagnetics Group at Institute of HighPerformance Computing, A*STAR, especially Dr Wei Xingchang, Dr Liu En-Xiaoand Dr Zhang Yaojiang for their valuable advice and discussions.

The sponsorship awarded for my PhD degree candidature by Institute of HighPerformance Computing (IHPC), A*STAR is gratefully acknowledged

Finally for all the support, love and understanding they have given me out the years, I wish to thank my wife, my parents and other family members

through-i

1.1 Background Information 1

1.2 Overview 3

1.3 Motivations 7

1.4 Outline of the Thesis 11

ii

Contents iii

1.5 Original Contributions and Innovations 14

2 Modeling of Interconnects, Transmission Lines, and Power-Ground Planes 15 2.1 Model of Multilayered Package 16

2.2 Inductance Extraction for the Interconnects in Chip and Package 17

2.2.1 Inductance and Reluctance Matrices 18

2.2.2 Stability Analysis for Reluctance K-Method 20

2.2.3 Efficient Inductance Extraction Method 22

2.3 Modeling of Signal Traces as Multiconductor Transmission Lines 26

2.3.1 Quasi-static Matrix Parameters for Multiconductor Transmis-sion Lines 26

2.3.2 Capacitance and Conductance Matrix Parameters 27

2.3.3 Inductance and Resistance Matrix Parameters 28

2.3.4 Examples for RLGC Parameters Extraction 29

2.4 Cavity-mode Resonator Model for Analysis of Parallel-Plate Power-Ground Planes 32

2.5 Summary 39

3 Electrical Performance Modeling of Power-Ground Layers with Mul-tiple Vias 41 3.1 Problem Statement for Modeling of Multiple Vias 42

3.2 Modal Expansion of Fields in a Parallel-Plate Waveguide 43

Contents iv

3.3 Multiple Scattering Coefficients among Cylindrical PEC and PMC Vias 46

3.4 Excitation Source and Network Parameter Extraction 53

3.5 Implementation of Effective Matrix-Vector Multiplication in Linear Equations 60

3.6 Numerical Examples for Single-layer Power-Ground Planes 63

3.6.1 Validation of the SMM Algorithm 63

3.6.2 Co-simulation Example 66

3.6.3 Simulation for Power-Ground Planes Decoupling 69

3.7 Novel Boundary Modeling Method for Simulation of Finite-Domain Power-Ground Planes 71

3.7.1 Perfect Magnetic Conductor (PMC) Boundary 71

3.7.2 Frequency-Dependent Cylinder Layer (FDCL) 72

3.8 Numerical Simulations of the Extended SMM Algorithm for Finite Power-Ground Planes 76

3.8.1 Validations of the Frequency-Dependent Cylinder Layer 76

3.8.2 Experimental Validations of the Extended SMM Algorithm 79

3.8.3 Irregular-shaped Power-Ground Planes and Cut-out Structure 87 3.9 Summary 90

4 Modeling for Multilayered Power-Ground Planes in Power Distri-bution Network 92 4.1 Modal Expansions and Boundary Conditions 93

4.2 Mode Matching in Parallel-plate Waveguides (PPWGs) 98

Contents v

4.3 Generalized T Matrix for Two-layer Problem 106

4.4 Formulas Summary for Two-layer Problem 111

4.5 Formulas Summary for Multi-layer Problem 115

4.6 Numerical Simulations for Multilayered Power-ground Planes withMultiple Vias 121

4.7 Summary 126

5 Hybrid Modeling of Signal Traces in Power Distribution Network

5.1 Methodology for Hybridization of SMM and Modal Decomposition 131

5.2 Modeling of Power-Ground Planes with Multiple Vias 134

5.3 Modeling of Multiconductor Signal Traces 135

5.3.1 Properties of the Per-Unit-Length Parameters 138

5.3.2 Mode Decoupling of the Parameters in Frequency Domain 139

5.3.3 Impedance Matrix of the MTLs with Same Length l 144

5.4 Modeling of Entire Signal Traces in Power Distribution Network 147

5.4.1 Modeling of Striplines between Power-Ground Planes 148

5.4.2 Equivalent Circuit Model of Through-Hole Signal Vias 153

5.4.3 Combination of Equivalent Networks for Modeling of Entire

Signal Trace 155

5.5 Numerical Simulations of Hybrid Modeling Algorithm for Signal Traces

in PDN 157

5.6 Summary 167

A Translational Addition Theorem in Cylindrical Coordinates 185

B Generalized Cascade ABCD Matrix for Entire System 188

An accurate electromagnetic modeling of power distribution network (PDN) in anadvanced electronic package together with efficient simulation of large-scale power-ground vias in multilayered structures has become of vital importance for optimizingthe electrical performance of high-speed digital circuits This thesis focuses ondeveloping accurate and efficient modeling and simulation methods for analyzingthe power distribution network for high-speed digital circuits and performing thesystem-level analysis of advanced electronic packages

Specifically, a systematic approach of efficient system-level simulation for anelectronic package is illustrated The electronic package is separated into two do-mains: the top/bottom domain and the inner domain The inner domain is theportion of the package confined by the top and bottom power-ground planes Theformer comprises signal traces (microstrip type), microstrip to via transitions, sol-der balls (for flip-chip packages) etc The latter mainly consists of parallel-platepower-ground planes and vias Those two domains are self-contained multiport net-works, and they are connected at the outmost anti-pad regions of the plate-throughvias Then, an accurate hybrid modeling approach of multiple scattering theoryfor coupling of power-ground (P-G) vias in the multilayered electronic package andmodal decomposition of the propagating modes in the package is implemented forthe power integrity (PI) and signal integrity (SI) analyzes of the signal traces in theelectronic package in the presence of large number of vias

The proposed semi-analytical approach of the scattering matrix method (SMM)

vii

Summary viii

is first developed for the analysis of multiple scattering of vias in the power bution network A novel boundary modeling method, that is, frequency-dependentcylinder layer (FDCL), is then proposed based on the factitious layer of PMC cylin-ders with frequency-dependent radii at the periphery of an electronic package tosimulate the finite power-ground planes of real world packages The formulation ofthe SMM algorithm with FDCL is extended to simulate multilayered structures ofthe P-G planes by using the modal expansions of parallel-plate waveguide and modematching in the anti-patch region of each via Numerical experiments are providedfor validation of the developed algorithm The results demonstrate that the pro-posed method is accurate and efficient to address the power integrity analysis of realworld electronic package with multilayered P-G planes and large-scale P-G vias

distri-Subsequently, an efficient modeling technique based on modal decomposition

of the electromagnetic fields is proposed for system-level analysis of the power tribution network in the package including the signal traces and the multilayeredpower-ground planes with multiple vias An analytical model is also introduced formodeling of the discontinuities of the signal traces at the through-hole via Then,

dis-a novel hybrid modeling dis-algorithm is developed to cdis-alculdis-ate the equivdis-alent work parameters for the entire power distribution Numerical simulations of thedeveloped hybrid algorithm are presented and validated with full-wave numericalmethod The hybrid modeling algorithm developed in this research work providesthe accurate and computationally efficient results

net-List of Figures

1.1 Power distribution noises coupling in system-on-package (SOP)

(Cour-tesy: M Swaminathan et al 2) 31.2 Chip, package and power distribution network (Courtesy: M Swami-

nathan et al 4) 91.3 Schematic diagram of a multilayered advanced electronic package 10

1.4 Illustration of the system-level modeling approach for advanced tronic packages 12

elec-2.1 A schematic of multilayered microprocessor package 16

2.2 A schematic of top-level metal for signal interconnects has an lying orthogonal interconnect array 23

under-2.3 Crosstalk noise on the center bus of 5 signal-lines system in Fig 2.2 25

2.4 Signal delay on the center bus of 5 signal-lines system in Fig 2.2 25

2.5 Sketch of coupled microstrips All dimensions are in mm 30

2.6 Sketch of multiconductor transmission lines on a multilayered board.All dimensions are in mm 30

2.7 Geometric structure of a rectangular power-ground planes 32

ix

List of Figures x

2.8 Illustration of port locations for the numerical examples of ground planes 34

power-2.9 Self-impedance of the port at the center of the power-ground plane 35

2.10 Input impedance of the port at the center of the power-ground plane 36

2.11 Self and mutual impedances of two ports shown in Fig 2.8(b) 37

2.12 Self and mutual impedances of two ports shown in Fig 2.8(c) 37

2.13 Self and mutual impedances of two ports shown in Fig 2.8(d) 38

2.14 Magnitude of input impedance of two-layered plate with a shorting pin 39

3.1 Schematic diagram of a multilayered advanced electronic package 43

3.2 A set of random cylindrical vias (2D view) 48

3.3 A schematic of cylindrical coordinates for translational addition orem 49

the-3.4 (a) Signal via passing through three P-G planes; (b) Equivalent modelfor the source via for calculation of entries in the admittance matrix:Port 1 and Port 2 are excited in the anti-pad region with an equivalentmagnetic current source, alternatively 53

3.5 A magnetic frill current on the bottom PEC plane of an infinite allel plate waveguide 54

par-3.6 Vias of a signal trace passing through two conductor planes The via

is enclosed by 12 shorting vias connecting the two planes 63

3.7 Comparison of the E z field distribution at 1 GHz: SMM simulationresult (left) vs HFSS simulation result (right) The vias are drawn

as white dots 63

List of Figures xi

3.8 Validation of the simulated results by SMM algorithm for E z withthose from the HFSS simulation 65

3.9 Y11 for the two-port network formed by the plate-through via 65

3.10 Field distribution of multiple scattering among the shorting vias 66

3.11 Schematic diagram of a signal trace packaging through two PEC planes 67

3.12 Schematic diagram of the equivalent circuit used for SPICE simulation 68

3.13 Voltage response at the far end of the signal trace in the presence oftwelve shorting vias and two PEC planes 68

3.14 Schematic diagram of a pair of power-ground planes with an SMTdecoupling capacitor close to an input SMA port 69

3.15 Comparison of the results of the input impedance: SMM algorithm,measurement and cavity-mode resonator model 70

3.16 Illustration of the implementation of the FDCL (Frequency-DependentCylinder Layer) boundary, where virtual PMC (Perfect MagneticConductor) cylinders (shaded) are contiguously placed at the pe-riphery of an electronic package to model the original finite-domainboundary 73

3.17 Implementation of the PMC cylinders placed at periphery of an tronic package in the boundary modeling method (2D view) 77

elec-3.18 Comparison of the extended SMM results with fixed and dynamicradii of the PMC cylinders in the FDCL and the reference solution 77

3.19 Effects of the different values of ζ on the accuracy of the simulation

results by the FDCL boundary modeling method 78

3.20 Test printed circuit board (PCB) for measurement 80

List of Figures xii

3.21 The scattering (S11) parameter for Port 1 of the test board in Fig 3.20.The simulated result by the SMM with FDCL method is comparedagainst the measurement data 80

3.22 The scattering (S21) parameter for Ports 1 and 2 of the test board inFig 3.20 The simulated result by the SMM with FDCL method iscompared against the measurement data 81

3.23 The scattering (S22) parameter for Port 2 of the test board in Fig 3.20.The simulated result by the SMM with FDCL method is comparedagainst the measurement data 81

3.24 Test printed circuit boards (PCBs) for analysis of the coupling effectbetween the signal vias 83

3.25 Comparison of the S11 parameters between the simulated results andmeasurement data for the test boards in Fig 3.24 84

3.26 Comparison of the S21 parameters between the simulated results andmeasurement data for the test boards in Fig 3.24 85

3.27 Experimental setup using Agilent HP 8510C Vector Network lyzer and HP 8517B S-parameter Test Set to measure the test vehicles

Ana-in Figs 3.20 and 3.24 86

3.28 An irregular-shaped power-ground planes and cut-out structure (unit:mm) 87

3.29 PMC cylinders formation in the FDCL at operation frequency of

1 GHz for the finite power-ground planes 88

3.30 PMC cylinders formation in the FDCL at operation frequency of

5 GHz for the finite power-ground planes 89

List of Figures xiii

3.31 Comparison of the transfer impedance by the SMM simulation withthe FDCL method against the measurement for the test board inFig 3.28 89

4.1 A though-hole via in two-layer structure and forming three PPWGs 93

4.2 A though-hole via in multi-layer structure and forming PPWGs 115

4.3 Example 1 - a multilayered parallel-plate structure with three ductor power-ground planes and 101 vias (unit: mm) 122

con-4.4 Comparison of the input impedance seen from the top end of theactive via in Example 1: SMM algorithm with FDCL vs HFSSsimulation 123

4.5 Example 2 - a multilayered parallel-plate structure with three ductor power-ground planes and 221 vias (unit: mm) 124

con-4.6 Input impedance seen from the top end of the active via in Example 2.125

4.7 Example 3 - a multilayered parallel-plate structure with six conductorpower-ground planes (unit: mm) 127

4.8 Comparison of the Z11 parameter simulated results for multilayeredstructure of Example 3: SMM algorithm with FDCL vs HFSS sim-ulation 128

4.9 Comparison of the Z21 parameter simulated results for multilayeredstructure of Example 3: SMM algorithm with FDCL vs HFSS sim-ulation 128

4.10 Comparison of the Z22 parameter simulated results for multilayeredstructure of Example 3: SMM algorithm with FDCL vs HFSS sim-ulation 129

List of Figures xiv

5.1 Signal trace route in power distribution network of an electronic age 132

pack-5.2 Three sub-domains applied in the modal decoupling; (a) multilayeredP-G planes, (b) signal traces, and (c) through signal vias 133

5.3 The per-unit-length equivalent circuit model for derivation of thetransmission line equations 135

5.4 The equivalent network for multiconductor transmission lines 144

5.5 Signal trace route in the power-ground planes of power distributionnetwork 147

5.6 Cross-section view of the stripline route 148

5.7 Transmission line representations of the stripline and its split model 149

5.8 Port voltages and currents defined for three equivalent networks 151

5.9 Combination for the equivalent Y-networks of the power-ground planesand the split stripline 151

5.10 Through-hole signal via and its equivalent circuit 153

5.11 PEC/PMC boundaries defined for analysis of the via region as abounded coaxial cavity 154

5.12 Overall equivalent network for the signal trace routed in the powerdistribution network 156

5.13 The dimensions of a signal trace routed between the power-groundplanes (top view and side view) (unit: mm) 158

5.14 Reflection and transmission characteristics of the signal trace shown

in Fig 5.13 159

List of Figures xv

5.15 The dimensions of a signal trace routed between the power-groundplanes (top view and side view) The black dots represent the decou-pling capacitors (unit: mm) 160

5.16 Reflection and transmission characteristics of the signal trace withthe decoupling capacitors shown in Fig 5.15 161

5.17 The dimensions of two coupled signal traces routed between the ground planes (top view and side view) - Case 1 All black dotsrepresent the P-G vias (unit: mm) 162

power-5.18 Reflection characteristic of the two coupled signal traces routed tween the power-ground planes shown in Fig 5.17 163

be-5.19 Transmission characteristic of the two coupled signal traces routedbetween the power-ground planes shown in Fig 5.17 164

5.20 Crosstalk characteristic of the two coupled signal traces routed tween the power-ground planes shown in Fig 5.17 164

be-5.21 The dimensions of two coupled signal traces routed between the ground planes - Case 2 All black dots represent the P-G vias (unit:mm) 165

5.22 The dimensions of two coupled signal traces routed between the ground planes - Case 3 All black dots represent the P-G vias (unit:mm) 166

power-5.23 Simulation results for crosstalk characteristic analysis of two coupledtraces - Case study 166

A.1 Translation in the cylindrical coordinate system 185

A.2 A schematic of the cylindrical coordinates in global expression for

cylinders p and q 186

List of Figures xvi

B.1 Definition for generalized cascade matrix of 2N -port network. 189

B.2 Total generalized matrix of cascaded networks 189

B.3 Cascade a 2N -port network with a two-port network 191

List of Tables

2.1 Geometry details for simulation of signal traces in Fig 2.2 23

2.2 Crosstalk analysis 24

2.3 Interconnect delay comparison 24

2.4 Comparison of results for the coupled microstrips in Fig 2.5 30

4.1 Comparison of memory usage and computing time for Example 1 123

4.2 Comparison of memory usage and computing time for Example 2 125

4.3 Comparison of memory usage and computing time for Example 3 129

xvii

List of Acronyms

FDCL Frequency-dependent Cylinder Layer

multi-The SOP has thus countless closely spaced metallic interconnection structuressuch as traces, vias, pads, leads, partial planes, and plane cavities in a small package.These densely spaced interconnection structures become sources of high-frequencynoise generation and noise coupling, imposing serious signal and power integrityissues as well as electromagnetic interference (EMI) / electromagnetic compatibility

1

Chapter 1 Introduction 2

(EMC) problems [3]

These noise problems are obviously crucial concerns when the SOP substrateand interconnections are designed Similar problems arise with high-speed and high-density multilayer printed circuit boards (PCBs), where many radio frequency (RF),analog, and digital devices are integrated into a densely populated PCB The noise atthe SOP or the PCB worsens noise and timing margin of digital and analog circuits,resulting in reduction of achievable jitter performance, bit error rate (BER), andsystem reliability The coupled noise from fast switching digital devices can alsoaffect phase noise and signal to noise ratio (SNR) performance in RF and wirelesscommunication circuits

In speed and density SOPs and PCBs, a major element of the frequency noise is simultaneous switching noise (SSN) from fast-switching digitalcircuits, as clock frequencies and the amount of switching current are significantlyincreased.1 There have been numerous studies of design and analysis methodologies

high-to reduce the SSN by using discrete on-chip and off-chip decoupling capacihigh-tors, and

by implementing embedded capacitors inside the multilayer PCB [4–10] There hasbeen always a tradeoff between the reduction effects and the necessary cost andmanufacturing complexity to realize the solution

The generated SSN could be transmitted to noise-sensitive circuits such as I/Ointerface interconnects, phase-locked loops (PLLs), and RF circuits through powerdelivery and ground return current paths as well as through signal traces and vias.Among the SSN coupling paths at signal interconnections, the signal via is the mostsignificant noise coupling structure, especially when the signal path is exchangingits reference planes Figure 1.12 illustrates the coupling mechanism between theSSN and a signal via with reference plane exchange through a power-ground planepair of the package [11–13] The signal via is the heavily utilized interconnection

IEEE, Istvan Novak, F ellow, IEEE, and James P Libous, Senior Member, IEEE.

Chapter 1 Introduction 3

structure in high-density SOPs and PCBs and enables complicated routing betweenmany active and passive devices mounted on, or embedded inside, the multilayerstructure To minimize radiated emission from such signal traces as microstriplines, strip lines are used and the signal via is necessary to make a transition fromthe microstrip line to the strip line Unless the two reference planes are tied togetherusing an electrically shorted circuit with minimal inductance, the signal interconnectencounters a very large signal reflection and the SSN noise coupling caused by thedisrupted return current path at the reference plane transition [14,15] When one ofthe reference planes is a power plane and the other reference plane is a ground plane,

it is not possible to connect them with a low-inductance via The signal reflectionand the noise coupling are maximal at resonance frequencies of the power-groundplanes

Figure 1.1: Power distribution noises coupling in system-on-package (SOP)

Chapter 1 Introduction 4

wireless communication and portable computing markets This challenges manyaspects of the design process With the trend in microprocessors toward higherpower and lower supply voltages, the power supply inductance has to continuouslydecrease In addition, the noise in the system is being generated by bouncing planesdue to the propagation of electromagnetic waves, resulting in significant couplingand radiation With increase in frequency and convergence toward mixed-signalsystems, supplying clean power to the integrated circuits and managing the noisecoupling in the system are very important and the power supply can be a majorbottleneck for the reliable functioning of the system [16, 17]

Modeling of power distribution networks represents an integral part of the powerdelivery design process In the last 15 years, the modeling methods have evolved

to a point where complex power distribution structures can be modeled accurately,with minimum CPU time This has led to design methodologies for the pre-layoutanalysis and post-layout verification of the packages, which has enabled the design

of multi-giga-hertz microprocessors and systems [18]

In the early 1990s, the partial element equivalent circuit (PEEC) based methodswere developed for analyzing power distribution structures These methods werebased on the seminal paper by Ruehli [19–24], which enabled the representation ofinterconnections using partial inductances The PEEC-based methods were used toanalyze Delta I or power supply noise in high-performance computers [25], packagedCMOS devices [26] and the first level packages [27,28] In [26], the effect of negativefeedback due to power supply noise on nonlinear CMOS inverters was discussed.Finally, Fast Henry, a multipole based PEEC method, was developed in [29] forspeeding computations

For the analysis of simultaneous switching noise as discussed in the previoussection, several papers have been published to analyze and accurately simulate theSSN on power-ground planes and noise in signal lines caused by the interactionbetween the power and the signal distribution systems [30–36] A general model

of interaction between currents in signal vias and SSN voltage was presented and

Chapter 1 Introduction 5

has been implemented in a full-wave simulation tool, Sigrity PowerSI [31, 32]3 ASPICE-type circuit model was proposed and compared with the full-wave simula-tion tool Further, various modeling methodologies have been proposed, includingnumerical approaches such as the method of moments and finite-difference time-domain method [31–37] The SSN coupling phenomena to signal via have also beenanalyzed by using the superposition principle and the transmission line theory in asimple equivalent circuit model [31] In [38], the similar approaches are used and asimple equation is further proposed to predict the amount of the SSN coupled tosignal via It is also a valuable research to develop efficient and practical methodsfor minimizing the SSN coupling to the signal via One suggested reduction method

is the use of a split power plane [35] The balanced TLM modeling approach wasalso reported to predict the SSN generation and PCB edge radiation excited by athrough-hole signal via, when the signal trace is exchanging reference planes [39,40]

With increase in clock frequencies, the frequency behavior of the power andground planes became important, and hence, their distributed modeling becamenecessary Distributed modeling of power distribution networks requires the de-scritization of Maxwell’s equations, which can be formulated in the frequency ortime domain by solving integral or differential equations Examples include thefinite-difference time-domain (FDTD) method [28,41–45], the finite element method(FEM) [46] and frequency domain methods such as the transmission line method[47], cavity resonator method [48, 49], transmission matrix method (TMM) [50],quasi-TEM analysis methods [51–53], and integral equation method [54] Since, elec-tronic package’s power distribution networks are resonant circuits with high qualityfactor, the frequency domain methods provide better accuracy and efficiency thanthe time domain methods Theoretically, those full-wave methods are versatile andable to solve any power-ground planes and via problems In reality, they have thedrawback due to large amount of memory usage and intensive CPU required

More recently, a cylindrical wave expansion method combined with Foldy-Lax

3SIGRITY PowerSI Sigrity, Inc [Online] Available: www.sigrity.com.

Chapter 1 Introduction 6

formula [55] was applied to the analysis of a large number of vias in PCB or packagestructures [56,57] The approach is very efficient in addressing the coupling of a largenumber of vias However, the structure studied by authors in [57] was assumed to

be infinitely large, which failed to model finite-sized structures In order to addressthe boundary modeling problem, a virtual circular cylinder was proposed in [58]

to approximate the rectangular boundary of an electronic package However, thesimulation results fail to correlate with measurement results, because such a crudeboundary approximation cannot accurately capture the interaction of the waveswith the periphery of packages The image theory [59, 60] has been utilized to dealwith the finite-sized boundary of the parallel-plate structures recently However, thedrawback of such an approach is obvious Firstly, the image theory is cumbersome indealing with arbitrarily shaped boundary Secondly, if the problem involves a largenumber of vias, then the total number of vias to be finally solved will greatly increasedue to the addition of a large number of image vias Although it can be used to tacklemultilayered parallel-plate structures, the cascaded microwave network approachmentioned in [57] is not efficient in analyzing a large number of ports due to a largenumber of vias For the analysis of multiple via coupling in multilayered parallel-plate structures of power distribution networks, a novel modeling method is required

to address the two open problems related to the modal expansion method [57, 58]

Among these proposed methodologies of equivalent circuit models, transmissionline theory based analysis, distributed modelings and full-wave numerical approaches

in literature, the cylindrical wave expansion method combined with Foldy-Lax mula is a very efficient technique in addressing the coupling of a large number ofvias in PCB or package structures since geometry meshing for problem domain isnot necessary The semi-analytical method [55, 56] was based on the modal waveexpansions of the vias and the multiple scattering formula of the vias After consid-ering the project requirements and the advantages of the cylindrical wave expansionmethod combined with Foldy-Lax formula (such as efficient modeling on coupling for

for-a lfor-arge number of vifor-as for-and no meshing required), we hfor-ave chosen the theory in [55]and further enhanced in the modeling efficiency and accuracy of multilayered and

a tightly integrated module By embedding functionality in the package (such asinductors, capacitors, resistors, waveguides, and filters), SOP provides for the co-design of the chip and the package for system integration.

A major problem with such a heterogeneous integration is the noise couplingbetween the various dissimilar blocks constituting the system The noise is primar-ily generated by the high-speed digital processor and coupled through the powerdistribution network, resulting in significant jitter for the phase-locked loop (PLL)and phase noise for the RF oscillator, resulting in the reduction of timing margin,noise margin, and degradation in the bit error rate (BER) The noise coupling isconceptually depicted in Fig 1.1 where the maximum power supply noise is trans-mitted through interconnections and vias at resonance in the power-ground planes

of the package Due to the low noise floor required for analog circuits, at frequenciesbelow the substrate resonance frequencies, considerable noise coupling occurs in theform of crosstalk and through the common inductive impedance of the power-groundreturn current path In addition, the resonance generates edge radiation, causingelectromagnetic interference in the system

The power distribution network consists of interconnections in the chip, packageand board, which together provide the required target impedance over a range offrequencies With the trend toward SOP, the power distribution network in the

Chapter 1 Introduction 8

chip and package has to be viewed as a single network, warranting a chip-packageco-design methodology for minimizing the resonance in the system This requires aclear understanding of the system blocks, design tools and technologies available forpower distribution

Figure 1.24shows schematic elements of the power distribution system from age regular module (VRM) to board, package and chip Since high-speed signalscoupling to the power distribution networks through parasitic mutual inductancescan cause voltage supply fluctuation, continuing efforts have been making to de-crease the inductance of power supply grids Power-ground structures are employed

volt-to reduce the power coupling noise in state of the art packages and boards ever, power-ground noise, also known as simultaneous switching noise (SSN), groundbounce or delta-I noise, can take place in multilayer printed circuit board (PCB),multi-chip module designs and package structures when high-speed transient cur-rents flow through a via The natural structure of a power-ground pair constructs

How-a pHow-arHow-allel plHow-ate wHow-aveguide, in which TEM mode excited by the current How-along How-a viHow-acan propagate and lead to strong coupling to other devices This coupling noise cancause serious signal integrity (SI) and electromagnetic compatibility (EMC) issues.Therefore, to ensure successful design of high-speed electronic products, it is impor-tant to accurately estimate the mutual coupling between a via and its surroundingdevices

Based on the extensive literature review, the problem was studied using severalapproaches; some analysis are only accurate for low frequency, some are only forthrough-hole vias instead of vias in a multilayer structure, and some are only lim-ited for few vias coupling simulation because of computational cost Even thoughthe signal integrity and power integrity problems have been addressed more andmore and some fast solutions can be found in literature, there is still lack of efficientsolutions for the radiation problems from multilayered packages (or PCB) Most ofprevious research works were still limited by computational efficiency and simplified

IEEE, Istvan Novak, F ellow, IEEE, and James P Libous, Senior Member, IEEE.

anal-The schematic of a multilayered advanced electronic package is shown in Fig 1.3.Besides the power and ground metal plates, there are a lot of buried vias to connectpower or ground planes in different layers [63–65] These shorting vias provideadditional return path and therefore, reduce the impedance of the power supplynetwork With the increase of signal frequency, more and more buried vias, includingpower and ground vias, are required nearby the high-speed signal via to restrictthe propagation of TEM waves excited by transient signal current The amount ofpower or the number of ground vias is continuously increased to shield signals within

a wider frequency band Another reason to install a lot of buried vias is to reducethe radiation from the surrounding edges of parallel power-ground planes [66]

A multilayered advanced electronic package consisting of signal traces, ground planes and plenty of vias (Fig 1.3) can be subdivided into two problem/designsets: the signal distribution network (SDN) and the power distribution network(PDN) For such a complex package, it is essential to consider the impact of thePDN on the electrical performance of the SDN in order to characterize the SDNmore accurately Due to the complexity of each network it is very difficult and

power-Chapter 1 Introduction 10

Figure 1.3: Schematic diagram of a multilayered advanced electronic package

time consuming to model both networks simultaneously The methodologies to beexplored in this research are intended to perform system-level simulation with anultimate goal to solve the electronic package

For efficient system-level simulation of an electronic package, the following out of modeling procedure is presented We separate an electronic package into twodomains: the top/bottom domain and the inner domain The inner domain is theportion of the package confined by the top and bottom power-ground planes Theformer comprises signal traces (microstrip type), microstrip to via transition, solderballs (for flip-chip packages) etc The latter mainly consists of parallel-plate power-ground planes and vias Those two domains are self-contained multiport networks,and they are connected at the outmost anti-pad regions of the plate-through vias.The integral equation method solved by the method of moments (MoM) [67, 68] is

lay-utilized to model the top/bottom domain As a result, the equivalent R, L, C, G

(re-sistance, inductance, capacitance and conductance) parameters of the top/bottomdomain are obtained An analytical method [69] is employed to derive the equiva-lent circuit of the microstrip to via transition in the top/bottom domain For theinner domain, a semi-analytical method is proposed to develop for extraction ofits admittance matrix parameters by using multiple scattering theory (a cylindricalwave expansion method with Foldy-Lax formula) The admittance matrix can beconverted to an equivalent circuit, e.g., using the approach presented in [45, 70]

An equivalent circuit of the original electronic package is generated by combiningthose for the top/bottom and inner domains It can then be used in a SPICE-like