Large signal modeling of gaas MESFET device 2

5.2 A Study of Some Existing Empirical Gate Capacitance Models Two of the most widely used MESFET capacitance models are the models based on pn junction depletion capacitance formula [

as nonlinear properties including distortion, harmonic analysis, third order modulation product (TOI), and ACPR (Adjacent-Channel Power Ratio) etc Therefore, charge (capacitance) modeling is very important for the design of nonlinear circuits using MESFETs, especially power amplifiers Accurate estimation

inter-of quantities inter-of interest for power amplifier at the design stage demands an accurate MESFET capacitance model

In Chapter 2, the basic operation of the MESFET is briefly discussed Physically, the depletion layer beneath the gate creates a continuous space-charge region under the gate that expands from the source region to the drain region The charge in this depletion region is balanced by an equal amount of charge on the gate electrode The gate charge changes with gate to source and drain to source voltage As a result, Cgs

and Cgd each depend on both Vgs and Vds, they are not two-terminal capacitors that

depend only on the voltage across them The gate drain capacitance Cgd is considerably smaller in magnitude than Cgs except in a certain transition region where both drain and source voltages are approximately equal

Charge is a constitutive relation that cannot be directly measured The nonlinear capacitances are usually extracted from S-parameter measurement in the whole transistor working domain There are different ways in modeling MESFET charge (capacitance) Physical models as proposed by Takada et al [102], Shur et al [103,104], Snowden et al [44,47,105] and D’Agostino and Beti-Beruto [106] require

a detailed knowledge of the device physical construction to fit measurement data Multi-dimensional spline functions are employed in table-based models The empirical model is the most commonly used approach in GaAs MESFET nonlinear modeling, it uses analytical functions to describe bias dependence of the capacitances Extensive work has been done in MESFET charge modeling, and several models have been proposed But, the number of models is less than that of DC I-V models for which a large variety of empirical formulations have been proposed The existing MESFET capacitance models can be classified into two groups In the first group of models, analytical equations are found to fit Cgd and Cgs separately, and the equations

do not satisfy terminal charge conservation These models may be difficult to implement in circuit simulators whose capacitance is always the derivative of an internal state variable (charge) In addition, the simulation may have convergence problems if charge conservation is not maintained These include the model proposed

by Scheinberg et al [107], Angelov et al [64], and Rodriguez et al [66] In the second group, analytical equations are proposed for terminal charge, and the capacitor values are derived from the partial derivatives of charge with respect to the

appropriate voltages, such as Statz model [58] and the model proposed by Parker and Skellern [70]

Modeling MESFET capacitance precisely is complicated Most existing models are capable of accurately describing capacitance performance in only certain device operation regions Modeling in the linear region and in the saturation knee region is difficult, and normally the inaccuracy is most significant Capacitance fitting at Vds=0 and in sub-threshold region are generally poor too Charge (capacitance) performance

is critical in predicting the nonlinear characteristics of MESFETs and circuits using them Thus, accurate capacitance modeling is important

In this chapter, some widely used gate capacitance models are first investigated A new gate charge model is subsequently proposed The model equation is unique, and

it is accurate under various device biasing conditions Most specially, the performance prediction in the linear region, saturation knee region, sub-threshold region and at

Vds=0 is greatly improved

A sub-micron MESFET device is adopted to verify the proposed model Gate capacitances Cgs and Cgd are extracted from measured S-parameters in the whole device working region under various biasing levels Terminal voltages at the intrinsic device are used in model parameter extraction of the nonlinear charge model Terminal voltages at the intrinsic device plane are obtained after de-embedding of the parasitic elements

5.2 A Study of Some Existing Empirical Gate Capacitance Models

Two of the most widely used MESFET capacitance models are the models based

on pn junction depletion capacitance formula [7] and Statz model [58] In this

section, these two models are compared and discussed A detailed model formulation

of each model can be found in Appendix A

5.2.1 Diode Junction Capacitance Model

In the diode junction capacitance model, both Cgs and Cgd are modeled as two terminal capacitors whose capacitances depend only on the voltage cross them Gate-source and gate-drain capacitance share the same expression which is given by equation 5.1, and is expressed as:

m

bi

gd gs

gd gs

gd

gs

V V

1

In equation 5.1, Cgs0 and Cgd0 represent gate–source and gate-drain capacitance at zero Vgs bias respectively, Vbi is the built-in voltage of the Schottky gate, and m is the capacitance gradient factor In some models like the Curtice model, m is assumed to

be 0.5, however, with m as model parameter allows C-V relationship to be more accurately modeled Equation 5.1 was originally developed for silicon devices, and it works well for silicon-based devices However, model accuracy is poor when equation 5.1 is applied to GaAs MESFET devices This is because of the linear approximation law, i.e (log(Cgs0,gd0/Cgs,gd)=mlog(Vbi-Vgs,gd)-mlog(Vbi)) Also, the model assumes Cgs and Cgd only depends on the voltage across them, drain-source voltage dependence is not included This assumption does not agree with real GaAs MESFET device operation and large fitting errors can be introduced into simulations, especially for operation at low drain to source voltage Equation 5.1 cannot be used to represent device capacitance when the device is forward biased

5.2.2 Statz Model

In the Statz model [58], a simple gate charge Qg expression was proposed The model was based on the observation of the measured Cgs and Cgd characteristic Gate source capacitance Cgs can be approximated by the diode junction capacitance model

in the normal bias range where Vds>>0 Gate drain capacitance Cgd is small in this same voltage range as compared to Cgs, Its value is approximately constant and nearly independent of Vgs or Vgd The Statz model gate charge expressions are given as follows

For Vn>Vmax,

2 0 max

max max

0

1

11

bi

n bi

bi

gs

V V

V V V

V V

1 2 0

1

K C V V

K K C V

1 3 0

1

K C V V

K K C V

02 1 1 gd eff

bi

n bi

gs

V

V V

1

K C V V

K K C V

Q

bi n gs

1

K C V V

K K C V

Q

bi n gs

+

=

2 2

1

1)(

2

1

α gd

gs gd

−

−+

=

2 2

2

12

1

α gd

gs gd

0 1 1

2

1

δ T eff

T eff

eff

n

V V

V V V

−

−+

2 1

2

1

121

α gd

gs

gd gs

gd eff

gs

eff

V V

V V V

V V

2 1

3

1

121

α gd

gs

gd gs

gs eff

gd

eff

V V

V V V

V V

V

Equations 5.9 and 5.10 are employed to achieve a gradual transition of capacitance values near Vds=0 Veff1 and Veff2 represent the bigger and the smaller value between Vgs and Vgd respectively Parameter α produces a smooth transition width of 1/α in the value of Veff1 and Veff2 as a function of Vgs and Vgd The transformation in equation 5.8 is employed to model capacitance beyond pinch-off In the pinch-off region, the gate-source capacitance drops to a small value, which is normally determined by the fringing capacitance of the depletion region The smooth transformation of equation 5.8 would set Vn to Veff1 before pinch-off, and to VT0 when

Veff1 is biased beyond pinch-off Parameter δ stands for the voltage range over which the transition between Veff1 and VT0 occurs, and is set to 0.2

From equations 5.2 and 5.5, we can see that charge Qg does not change if the values of Vgs and Vgd are inter-changed This is achieved through the transformation

of equations 5.9 and 5.10 Thus, the model yields a symmetry behavior of the transistor For positive Vds (normal operation model), Cgs shows diode capacitance behavior with Vgs, whereas in the reverse-biased direction (Vds<0), Cgs approaches

Cgd0 On the other hand, Cgd is close to Cgd0 when Vds>0, and exhibits diode capacitance behavior with Vgd when Vds<0 Thus, when Vds<0, the role of drain and source reversed, and the source becomes the effective drain, so Vgd not Vgs becomes the important gate voltage

Vmax is introduced to solve the singularity in junction capacitance when Veff1becomes positive and is equal or greater than Vbi The value of Veff1 is limited to a maximum value of Vmax when Veff1≥Vmax (Vmax sets to 0.5V) This limits the value of junction capacitance The choice of Vmax determines the maximum capacitance value, for voltage beyond Vmax, the junction capacitances are assumed to remain constant This is reflected by equations 5.2-5.4

5.2.3 Discussions

To compare the accuracy of the two capacitance models discussed above, model parameters are extracted for a 2*150μm GaAs MESFET device using the Statz model and diode junction capacitance model respectively The modeled results are then compared with the measured data

Figures 5.1 and 5.2 give the measured and modeled Cgs result by the diode junction capacitance model and the Statz model The calculation is made for the

following bias voltage, V gs =−2.0−0.0V and V ds =0.0−4.0V As can be seen from Figure 5.1, for the diode junction capacitance model, the difference between modeled and measured results is very big, especially in linear region where Vds is small This is expected because Cgs dependence on Vds is not considered in the diode junction capacitance model However, as observed from measurement device Cgs behavior, a fast change in Cgs is observed in the linear region As a result, Vds dependence must

be taken into account for accurate Cgs prediction Modeling result using the Statz model provides a great improvement over junction capacitance model by including

Vds dependence Model accuracy is greatly improved in linear region The Statz model does not offer much performance improvement over junction capacitance model in saturation region This is because in saturation region where Vds>>0, Statz model for Cgs expression approximates the simple junction capacitance model

The measured and calculated result for Cgd using the diode junction capacitance model and the Statz model are shown in Figures 5.3 and 5.4 respectively Cgd is plotted in the bias range of V gs =−1.4−0.0V and V ds =0.0−4.0V Both models show big error for Cgd as compared with measurement device Cgd result For the junction capacitance model, this inaccuracy arises from the fact that Cgd is modeled as

a two terminal capacitor whose capacitance depends on the voltage across it only On the other hand, for the Statz model, this inaccuracy may be caused by the symmetrical assumption where the same parameters need to fit both Cgs and Cgd simultaneously

The maximum fitting error and the RMS error are illustrated in Tables 5.1 and 5.2 for Cgs and Cgd respectively The comparisons are made for three different device operation regions, they are, (a) V gs =−2.0−0.0V, V ds =0.6V , which corresponds to

the linear region, (b) V ds =2.5V which is in saturation region, and (c) for the entire

Vds bias region from 0.0 to 4.0V

Table 5.1 Comparison of Cgs Accuracies of Diode Junction Capacitance Model and

Statz Model for a 2*150μm GaAs MESFET

Table 5.2 Comparison of Cgd Accuracies of Diode Junction Capacitance Model and

Statz Model for a 2*150μm GaAs MESFET

Comparatively speaking, the gate charge and capacitance expressions in the diode junction capacitance model and the Statz model are relatively simple, and the number

of fitting parameters is small But the accuracies of both models are limited Fitting error gets bigger in both linear and saturation region for Cgs as well as Cgd For the diode junction capacitance model, there is singularity in junction capacitance when

Vgs,gd becomes positive and is equal or greater than Vbi Thus, the model cannot be used in this operation condition

5.3 The New Model

The gate charge (capacitance) modeling is very important in accurately describing MESFET’s nonlinear behavior, and therefore is critical for predicting the performance

of nonlinear circuits like power amplifiers Accurate simulation of the voltage dependency of Cgs and Cgd is difficult to achieve In the linear region, both Cgs and Cgd

change fast with Vgs and Vds In the saturation region, Cgs is almost independent of

Vds, and Cgd shows little variation with Vgs When terminal charge conservation has to

be taken into consideration in the gate charge model to avoid possible convergence problem in simulation, more difficulty would be imposed to find a suitable gate charge expression

The following charge conservation law is chosen for the gate charge [77,108]

dt

dv v

dv v v C dt

dv v v C v

v

C

ds gs gd gs ds gs gd ds gs

gs

gd ds gs gd gs ds gs

gs

),()

ds ds

gs

g gd

(sec

2 1

1

eff

v c

*

* 2 1

1

1

2 4 2 3

eff eff

eff v

c v c

gs

dv c dv v

c e

c c

1 2 1 2 1

1 6

* 5 1 7

2

2

2 6

eff eff

eff eff

eff eff eff

eff v

c eff

dv v

v dv dv

v c e

c dv c

2 1

2

* 5 1

7

2

2 6

eff eff

eff v

c eff

v v

v e

c v

∗

2 1 11 2 3 2 10 9

3 c v gs c v eff c v eff

1 1 11 2

2 10

eff gs

dv v c dv

v c c

0 2

2

1

gst gst

0 1

2

1

δ gst

v

0 2

2

δ gst

is primarily developed to provide more accuracy Therefore, most of the model parameters do not convey any physical meaning

In the above equations, c1 to c11 and Cgd0 are model parameters for accurate curve fitting VTO is the pinch-off voltage which is also used to define drain current I-V characteristics, VTO can be kept the same as that used in DC I-V model, in doing so, a compromise is made between DC and AC modeling accuracy If VTO is extracted differently from DC I-V characteristics, improvements in CV modeling can be achieved δ is a parameter introduced to model the voltage range over which the transition to the sub-threshold and the pinch-off region occurs Finally, Vgs and Vds

are the intrinsic terminal voltages

2 2 ,

2

f c v c h f v

v v C v

v v C v v C v

ds gs gd ds

ds gs gd ds gs gs ds

5.4 Numerical Results and Discussions

5.4.1 Model Parameter Extraction

The same 2*150µm sub-micron gate-length MESFET device (wafer device) as in Chapter 4 is used to verify the new gate charge model The S-parameter data is measured at multi-bias conditions (totally 285 biasing points) The small-signal equivalent circuit models are extracted under multi-bias conditions using the cold-FET method combined with the multi-plane data fitting approach [26] All the parasitic element values are kept constant in the large-signal model The extracted parasitic element values are listed in Table 4.3 The nonlinear capacitances were acquired from S-parameter measurement in the frequency range of 1-30GHz They are represented in the whole working domain as shown in Figures 5.5 and 5.6 for Cgsand Cgd respectively (V gs =−2.0−0.5V, V ds =0.0−4.0V 0V)

extractions are performed by an in-house developed software running under MATLAB by MathWorks A simplex algorithm is used for the optimization

5.4.2 Modeling Results and Discussions

Figures 5.7 and 5.8 show the comparison between the modeled Cgs and Cgd using the new model and gate capacitances extracted from measured S-parameter for the 2*150µm sub-micron gate-length MESFET The pinch-off voltage of the device is -1.21V For clear display, only results under Vgs=-2.0V, -1.4V, -1.2V, -1.0V –0.5V, 0.0V and Vds=0.0-4.0V are plotted for Cgs For Cgd, the results are plotted for Vgs=-1.4V, -1.0V –0.5V, 0.0V and Vds=0.0-4.0V, this is because in the saturation region,

Cgd shows small variation with Vgs

Vgs The model is also capable of modeling nonlinear capacitances in the pinch-off region and for Vgs>Vbi

The new model gives a continuous transition over different operation conditions, and its derivatives are continuous Figures 5.9 to 5.12 give the derivatives of Cgs and

Cgd with respect to Vgs and Vgd for the 2*150μm wafer device

To illustrate the model continuity with respect to Vgs,

gs

gs V

C

∂

∂

vs Vgs characteristics is shown together with

modeled and measured Cgs vs Vgs performance Vds is fixed at 2.0V Under this Vds

bias, the device operates in the saturation region The Vgs biasing voltage covers the normal operating region as well as the pinch-off region It is noted that the modeled

Cgs result matches the measured result closely The

gs

gs V

C

∂

∂

vs Vgs curve by the new

model is continuous The transition between pinch-off and normal operation region is smooth

Figure 5.9 Cgs vs Vgs and ∂C gs /∂V gsvs Vgs characteristics for a 2*150μm wafer

device ( Cgs by the new model, - ∂C gs /∂V gs by the new model, •••• Cgs

measured)

The modeled

gs

gd V

C

∂

∂

vs Vgs characteristics are plotted together with the modeled

and measured Cgd vs Vgs characteristics in Figure 5.10 The measurement result has shown that device Cgd vs Vgs characteristic behaves differently in the linear and saturation regions This can be observed from Figure 5.6 In the linear region where

Vds is small, Cgd increases as Vgs increases.On the other hand, in the saturation region,

Cgd decreases as Vgs increases In Figure 5.10,

gs

gd V

C

∂

∂

performance is plotted under two

Vds biasings They are Vds=0.2V and Vds=2.0V Under these two Vds values, the device operates in the linear and saturation region respectively As can be seen, the modeled Cgd result by the new model matches perfectly to the measurement data The

vs Vgs curve is continuous and well behaved It accurately represents the

device behavior under various operation conditions For Vds=0.2V,

gs

gd V

∂

∂

vs Vds characteristics as well as the

modeled and measured Cgs vs Vds performance The plots are given for two Vgsbiasings, they are Vgs=-0.2V and Vgs=-2.0V Under these two Vgs values, the device operates in the normal and pinch-off region respectively As can be seen from Figure 5.5, the Cgs vs Vds property is different in the normal operating region and in the pinch-off region In the pinch-off region, Cgs shows little variation with Vds However,

in the normal operating region, Cgs changes fast with Vds in the linear and knee region

These properties are reflected in the

ds

gs V

C

∂

∂

vs Vds characteristics are plotted together with the modeled

and measured Cgd vs Vds characteristics in Figure 5.12 The Vgs is fixed at 0.0V As can be seen, the modeled Cgd result by the new model matches perfectly to the

measurement data The gd

transition among the linear region, the knee region and the saturation region is smooth

The measured and computed response achieved with the diode junction capacitance model, Statz model and the new model for Cgs when operating solely against Vgs (Vds at fixed value) are shown in Figure 5.13 As observed from the figure, the junction capacitance model provides very poor accuracy The Statz model provides noticeable improvement over junction capacitance model, however, the model accuracy is still poor at certain device bias points The new capacitance model provides the best accuracy, modeled and measurement data show close agreement

advantage over the other two models, the modeled result matching measurement data closely

The maximum fitting error and the RMS error of Cgs and Cgd obtained from the new model are listed in Tables 5.4 and 5.5 respectively together with the results for the diode junction capacitance model [7] and Statz capacitance model [58] for comparison The calculation is made under six bias levels for Vgs (Vgs=-2.0V, -1.4V, -1.2V, -1.0V –0.5V, 0.0V), while Vds changes from 0.0V to 4.0V (on-wafer 2*150μm device) The first two columns in the table represent the fitting error in the linear region The following two columns show the model error in the saturation region, and the last two columns give the error for the entire working region It can be seen from Tables 5.4 and 5.5 that the new model gives remarkable improvement in accuracy over the diode junction capacitance model and Statz model over the entire device working region, both maximum fitting error and RMS error are greatly reduced Especially, Cgs modeling in linear region is very accurate, whereas the other two models appear to give big error in this region Modeling error for Cgd by the new model appears to be a bit high However, it still shows great improvement over the other two models Considering measurement uncertainty, the model is very accurate

Table 5.4 Comparison of Cgs Accuracies of Diode Junction Capacitance Model, Statz

Model and the New Model for a 2*150μm GaAs MESFET

Table 5.5 Comparison of Cgd Accuracies of Diode Junction Capacitance Model, Statz

Model and the New Model for a 2*150μm GaAs MESFET

0 180

1 50

-15 0 120

1 50

-15 0 120

Figure 5.15 Comparison between measured and simulated S-parameter, with Cgs and

Cgd derived from the new model, Vgs=0.0V, Vds=2.0V

The newly proposed gate charge model is more complicated than the diode junction capacitance model and Statz model, and it contains more model parameters But it is very accurate in describing device junction capacitances, and it obeys the terminal charge conservation law which helps to solve non-convergence problem in simulation In addition, the model is continuous The above discussions show that the new model is capable of accurately representing the actual device behavior over an extended range of operation conditions The new model can be easily implemented in CAD software, and could be very useful in nonlinear circuit simulation

Chapter 6

Model Verification

In the previous chapters, small signal modeling methodology and a reliable parasitics extraction technique were discussed, also a new MESFET I-V model and new gate charge model were proposed In each chapter, the proposed methodology and the new model were verified by extensive measurement data and circuit design In this chapter, more work was done based on the proposed new model and extraction methodology to evaluate the new model The evaluation includes S-parameter analysis at multi-bias points, gain compression and harmonic output prediction, and a MMIC power amplifier design The MMIC power amplifier is designed and fabricated using 0.5µm GaAs MESFET technology Instead of foundry models, the new nonlinear model is used for the active MESFETs used in the design Measurement and simulation results are compared

6.1 S-Parameter at Multi-Bias Points

The nonlinear model should be able to predict the device ac behavior over a large frequency and bias range To demonstrate the nonlinear model’s ability to predict device small signal ac performance, the large signal model is used to simulate device S-parameter over a large frequency and bias range A 2*150µm device is used in the investigation, its large signal model was constructed and performance simulated following the procedure outlined below

1 Device S-parameters were measured from 1- 28GHz, over the following bias range: Vgs=-2.0 to 0.5V, Vds=0 to 4.0V Small signal equivalent circuit was

extracted over the entire bias range, device bias dependent elements values were obtained, the Cgs and Cgd results were then used to extract the gate charge model The intrinsic drain current model was extracted based on the measured

DC I-V drain current characteristics All the parameter extraction was done using Matlab

2 The nonlinear model was implemented in Agilent ADS Symbolic defined device (SDD) was employed to implement the nonlinear equation for intrinsic drain current and for Cgs and Cgd

3 The nonlinear model was used to calculate the small signal S-parameters from

1 - 28GHz, and repeated for each bias point in ADS

4 The simulated S-parameter data from ADS was compared with the measured S-parameter at each bias point, and the RMS fitting errors were plotted in Figures 6.1 (a), (b), (c), (d) for S11, S12, S21, S22, respectively

The definition of the RMS error is as in equation 6.1

N

f S

f S f S error

RMS

N

k

k mea ij

k mea ij k ij

)(

)()

(

where, i,j =1,2 N is the total number of frequency points, fk is the frequency at which

S-parameter were measured mod( )

0 1 2 3 4

-2 -1 0

-2 -1 0 1 0 5 10 15

V

ds (V) V

-2 -1 0

-2 -1 0 1 0 5 10 15

V

ds (V) V

Figure 6.1 RMS errors of S-parameter calculated from the large signal model as a

function of bias (a) S11, (b) S12, (c) S21, and (d) S22

The RMS error of S-parameter calculated from small signal equivalent circuit was plotted in Figure 6.2 for comparison The small signal equivalent circuit was extracted

at each bias point in the same Vgs and Vds range as the large signal model During model extraction, all parasitic element values are fixed, only intrinsic elements vary with bias voltage

0 1 2 3 4

-2 -1

-2 -1 0 1 2 4 6 8

-2 -1

-2 -1 0 1 2 4 6 8 10

Figure 6.2 RMS errors of S-parameter calculated from small signal equivalent circuit

at different bias (a) S11, (b) S12, (c) S21, and (d) S22

It can be seen from Figure 6.1 that the RMS error for all the four S-parameters are high in linear and near knee region, also the error increases as Vgs approach positive value The same trend is reflected in the S-parameter error calculated from small signal model as shown in Figure 6.2 Comparing Figures 6.1 and 6.2, it can be seen that the S-parameter error calculated from large signal model shows a 5-10% increase

at some bias points The reason for this increase is probably due to the fact that frequency dispersion effects of output resistance and transconductance were not modeled in the large signal model In addition, τ is neglected in the large signal

model Parasitic elements Rg, Rd, Rs, Lg, Ld, Ls, Cpg, Cpd, and Cds Ri also introduce error since they are assumed to be bias independent However, this assumption is not true for some of the above parameters, which are bias dependent especially at linear region That also explains why the error in the linear region is high Taking all these sources of errors into consideration, the large signal model gives reasonable accuracy

in predicting the device’s RF performance, with a relative error below 15%

6.2 Large Signal Performance Verification

Gain compression and harmonic measurements are commonly performed to verify the large signal performance of the nonlinear model at the device level This measurement is relatively simple to make and involves less expensive equipment configurations as compared to the load-pull measurement

Single-tone large signal test was performed for a 2*150µm GaAs MESFET device The device is biased at Vgs=-0.5V, Vds=3.0V, with a 2GHz fundamental frequency The input power level sweeps from a low level to a power level slightly higher than the 1-dB compression of the device gain The device model using the new drain current model and the new gate charge model is implemented in Agilent ADS The simulation and measurement large signal result is shown in Figure 6.3 Figure 6.3 (a) is the result of the output power versus the input power of the first three harmonics In Figure 6.3 (b), the simulated and measured gain compression performance of the device is presented

Figure 6.3 (a) shows that there is very good agreement between simulated and measured result of output power vs input power for the fundamental frequency The maximum deviation between simulated and measured result is below 0.7dBm This small discrepancy may be caused by the measurement uncertainty It is noted that the

simulated second harmonic power shows bigger deviation from the measurement result The difference gets bigger when input power is greater than the P1 dB input power, which is around 6dBm The maximum difference between the simulated and measured second harmonic power is below 4dBm For the third harmonic content, good agreement is shown in the linear region, and the difference increases when input power is above P1 dB input power The maximum deviation is 3.4dBm The error observed in the second and third harmonic content is due to fact that diode Dgd is not considered in our large signal device model The simulated gain of the device also agrees very well with the measurement result as can be seen from Figure 6.3 (b) The maximum difference is smaller than 0.6dB

Simulated single-tone large signal results by our new model show good agreement with the testing result This proves that the new model is capable of representing the device nonlinear behavior

Figure 6.3 Single-tone large signal test result for a 2*150µm MESFET (

Simulation, ••••Measurement) (a) Pout/Pin behavior for the first three harmonics, and (b) gain compression

6.3 A GaAs MESFET MMIC Power Amplifier

6.3.1 MMIC Power Amplifier Circuit

To verify the accuracy of the proposed nonlinear model at circuit level, a MMIC power amplifier was designed and fabricated using a 0.5µm GaAs MESFET process

In the amplifier design, models for the active MESFET devices were extracted from on-wafer device measurement data using the proposed new model, and implemented

in Agilent MDS using SDD For passive devices like capacitors and spiral inductors, foundry models were used The design specification of the amplifier is shown in Table 6.1

Table 6.1 MMIC Power Amplifier Design Specification

Output power (P1dB) 36dBm (Peak)

Input/Output return loss < -10dB

The schematic of the MMIC power amplifier is shown in Figure 6.4 In the design, power combining technique is used The amplifier was constructed from seven high power MESFETs The first FET drives two in parallel, and each of these two FETs drives another two in parallel The output power is the combined power output from four identical MESFET amplifier stages The active MESFETs are designed to operate in class AB mode

Figure 6.5 shows the actual layout of the designed GaAs MESFET MMIC power amplifier It has a size of 4mm*4mm

Figure 6.5 Photo of the GaAs MMIC power amplifier layout

6.3.2 Device Modeling Result

The sizes of the GaAs MESFETs used in the design are 10*100µm, 12*100µm and 16*100µm Figure 6.6 shows the large signal model used in device modeling The nonlinear model for Igd and Igs use the foundry model For Ids and capacitance Cgd and

Cgs, the new models are used Models for the three MESFETs are optimized to fit the measurement result On-wafer device measurement was made using HP 85124A pulse modeling system S-parameter data, DC characteristics and pulse I-V measurement data were collected

Figure 6.6 Large signal model for the GaAs MESFET

Figures 6.7 to 6.9 show the comparison of measured and modeled DC I-V characteristics of the three devices These nonlinear drain current modeling results were adopted in the amplifier design to find the DC operating point for the three MESFETs