Hafnium oxide based high k dielectric gate stack

TABLE OF CONTENTS ACKNOWLEDGEMENTS...i TABLE OF CONTENTS ...iii SUMMARY...v LIST OF FIGURES...vii LIST OF TABLES ...xi LIST OF PUBLICATIONS ...xii Chapter 1 Introduction ...1 1.1 Introdu

ACKNOWLEDGEMENTS

Firstly, I would like to express my deepest appreciation to my supervisors, Professor Ong Chong Kim (Department of Physics, National University of Singapore) and Professor Alfred, Huan Cheng Hon (Division of Physics & Applied Physics, Nanyang Technology University and Institute of Materials Research & Engineering), for their excellent guidance, constructive comments, and valuable support during my PhD candidacy Their profound knowledge and rigorous scientific approach have greatly inspired me in the research

Secondly, I would like to express my sincere gratitude to my co-supervisor, Dr Wang Shijie, research scientist from Institute of Materials Research & Engineering He has constantly provided me with excellent guidance and support for both of my professional and personal developments His kindness and integrity have always been a good example for me even in my future career Thanks for teaching me many experimental and analytical skills used in this research work I am truly grateful for all his help and encouragement during the course of this research

My thankfulness also extends to two great persons in our research group, Dr Dong Yufeng and Dr Mi Yanyu, for their self-giving help and kindly encouragement in the last few years Thanks for the happy time with them during my PhD study

This research would not have been possible without much assistance from scientists and researchers at NUS and IMRE as well as excellent research equipments provided by NUS and IMRE I would like to specially thank a few more persons here: Prof Feng Yuanping, Dr Pan Jisheng, Dr Chai Jianwei, Mr Lim Poh Chong, Ms Chow Shue Yin,

Mr Wang Weide, Dr Li Zhengwen, Dr Kong Lingbin, Dr Yan Lei, Dr Tan Chin Yaw, and Mr Liu Huajun Many thanks also go to Dr Ng Tsu Hau, and his supervisor, Associate Prof Chim Wai Kin, from Department of Electrical and Computer Engineering, NUS, for their technical supports to this work

Finally, I would like to dedicate this thesis to my parents, for their consistent encouragement, support and understanding during my study in Singapore Lastly but not least, I wish to express sincere gratefulness and indebtedness to my husband, Mr Guan Zhiyong, for his endless love and strong support

If I forgot anybody in this list, it was done by mistake rather than intention

TABLE OF CONTENTS

ACKNOWLEDGEMENTS i

TABLE OF CONTENTS iii

SUMMARY v

LIST OF FIGURES vii

LIST OF TABLES xi

LIST OF PUBLICATIONS xii

Chapter 1 Introduction 1

1.1 Introduction 1

1.2 An overview of device scaling 3

1.3 Limitations for gate oxide (SiO 2 ) scaling 5

1.4 Alternative high-k gate dielectrics candidates and materials properties considerations 9

1.5 Metal gate candidates and materials properties considerations 17

1.6 Band alignments at metal/high-k/semiconductor interfaces 19

1.7 Motivations and scope for present work 23

Reference .26

Chapter 2 Film Deposition, Characterization Techniques and Modeling Methods 33

2.1 Introduction 33

2.2 Film deposition techniques 34

2.3 Characterization techniques 39

2.4 First-principles calculation 46

Reference .49

Chapter 3 Thermodynamics and Thermal Stability Study of HfO 2 films in Contact with Si 51

3.1 Introduction 51

3.2 Thermodynamic study of HfO 2 films on SiO 2 -covered silicon 53

annealing 60

3.4 Conclusion 70

Reference .72

Chapter 4 Highly Thermal Stable (HfO 2 )1-x(Al 2 O 3 )x Films 75

4.1 Introduction 75

4.2 (HfO 2 )1-x(Al 2 O 3 )x films fabricated by dual-beam pulse laser deposition 76

4.3 Thermal stability of (HfO 2 )1-x(Al 2 O 3 )x/Si interface 77

4.4 (HfO 2 )1-x(Al 2 O 3 )x/Si interface structure at atomic scale 82

4.5 Electrical characterization of (HfO 2 )1-x(Al 2 O 3 )x/Si stacks 85

4.6 Stress testing of (HfO 2 )1-x(Al 2 O 3 )x films as gate dielectric 88

4.7 Frequency dependent properties of (HfO 2 )1-x(Al 2 O 3 )x films as gate dielectric 93

4.8 Conclusion 95

Reference .96

Chapter 5 Interfaces of Metal Gate/ HfO 2 /semiconductor System 98

5.1 Introduction 98

5.2 HfO 2 /Semiconductor interface 100

5.3 Metal gate/HfO 2 interface 110

5.4 Band alignments of RuOx on HfO 2 /Si system 116

5.5 Conclusion 121

Reference .122

Chapter 6 Evolution of Schottky Barrier Heights at Metal/HfO 2 Interfaces 126

6.1 Introduction 126

6.2 Evolution of Schottky barrier heights at metal/HfO 2 interfaces 127

6.3 Atomistic modeling of Ni/HfO 2 interfaces 134

6.4 Conclusion 148

Reference .150

Chapter 7 Conclusions and Future Work 152

7.1 Conclusions 152

7.2 Future work 154

Reference .156

SUMMARY

High-k dielectrics are proposed to replace traditional SiO2 as gate dielectric layer Meanwhile, conventional poly-silicon electrode should also be replaced by metal gates Metal/HfO2/semiconductor system is very promising to be used in future generation CMOS In this thesis, the physical, electrical and electronic properties of metal/HfO2/semiconductor systems have been systematically studied by combining film fabrication and characterization techniques and first-principles calculations

The thermodynamic stability of HfO2 film has been investigated by studying the reactions during the deposition of HfO2 thin films on SiO2-covered silicon substrates in oxygen-deficient conditions Thermodynamic analysis indicates that even if there is a layer of silicate forming at the initial stage of deposition, the silicate layer or the SiO2

layer will be decomposed by metal ions and oxygen in the interfacial layer will be absorbed by HfOx<2 to form fully oxidized metal oxide The thermal stability of HfO2film on silicon has been systematically investigated As a result of high temperature annealing, a SiO2-rich interface layer is formed after high temperature rapid thermal annealing and the phase change of HfO2 from amorphous to crystalline has been observed at about 700ºC Highly thermal stable thin films of (HfO2)1-x(Al2O3)x were

fabricated on p-type Si (100), which maintain an amorphous state even with rapid thermal

annealing at 1000ºC

The interfacial atomic structure and band discontinuity of metal/HfO /semiconductor

systems for the application in electronic devices have been studied using x-ray

photoemission spectroscopy (XPS) It was found that the band alignments are dependent Sufficient high valence-band and conduction-band offsets (>1.0 eV) were obtained for HfO2/semiconductor (Si, Si0.75Ge0.25 and Ge) interfaces, which guarantees HfO2 as an effective carrier barrier for the channels and the most promising high-k gate

substrate-dielectric candidate on Si and other high performance substrates (Si0.75Ge0.25 and Ge) For metal/HfO2 interfaces, in situ XPS methods were performed to accurately

determine the Schottky barrier heights for Ni(Co)/HfO2 stacks The band discontinuities for the vacuum level were found at the interfaces of metal/HfO2 It is believed that this is due to the dipole formed at the metal/oxide interface Detailed studies on the evolution of the band alignment during the formation of metal-dielectric contacts were conducted on Ni/HfO2 stacks to clarify how the interface dipole is formed even for the simple non-

reactive metal gate/high-k dielectric interface and how it influences the effective work function of metal gate by in situ XPS and first-principles calculations based on density

functional theory This work identified that the interface dipole was induced by the weak interaction of Ni thin film and HfO2 dielectric

The energy-band alignments for the RuOx/HfO2/Si stacks and the oxidation-state dependent barrier heights for RuOx in contact with HfO2 dielectrics have been investigated by XPS technique The results in this work imply that the ruthenium oxide, RuO2, is a promising alternative gate electrode to be integrated with high-k gate

dielectrics

LIST OF FIGURES

gate dielectric thickness .7

Figure 1.2 Schematic energy band diagram of direct tunneling of electron from the Si substrate to the gate in a turned on n-MOSFET (Si/SiO2 /poly-Si gate structure) .7

Figure 1.3 Band offset calculations for a number of potential high-k gate dielectric materials .12

Figure 1.4 Schematic band diagrams for metal/oxide/Si stacks Definitions of band offsets (VBO and CBO) and of SBHs (Φn and Φp) are shown .21

Figure 2.1 Schematic view of the pulse laser deposition system .35

Figure 2.2 Schematic view of e-beam evaporator .39

Figure 2.3 Schematic views of the main basic requirements for XPS system .40

Figure 2.4 Schematic view of photon induced electron emission (photoemission) in XPS (Carbon atom) .41

Figure 2.5 Schematic view of a transmission electron microscope 45

Figure 3.1 (a) Si 2p core-level; (b) O 1s core-level; (c) Hf 4f core-level XPS spectra at different stages of HfO 2 deposition on SiO 2 -covered silicon .55

Figure 3.2 TEM image of 8.75 nm HfO 2 film on silicon, free of underlying amorphous SiO 2 57

Figure 3.3 XPS depth profile for 8.75 nm HfO 2 film on silicon, the sputtering time of 30 s for each level (a) Si 2p; (b) Hf 4f; (c) O 1s core-level spectra .59

Figure 3.4 Si 2p core-level spectra of ~4 nm as-deposited HfO2 film .62

Figure 3.5 Si 2p core-level spectra of ~4 nm as-deposited HfO2 film .62

Figure 3.6 Cross-sectional HRTEM image of ~4 nm as-deposited HfO 2 film .63

Figure 3.7 (a) Si 2p (b) Hf 4f core-level spectra of ~4 nm as-deposited HfO2 film and the films with rapid thermal annealing at different temperatures 65

were labeled .66

Figure 3.9 Capacitance-voltage characteristics of ~4 nm as-deposited HfO 2 film and films with rapid thermal annealing at different temperature 67

Figure 3.10 EOT and effective dielectric constant for Al/HfO 2 /Si capacitors as a function of annealing temperature 69

Figure 3.11 Current-voltage characteristics of ~4 nm as-deposited HfO 2 film and films with rapid thermal annealing at different temperature 70

Figure 4.1 Si 2p, Hf 4f, Al 2p and O 1s XPS depth profiling spectra of 10.0 nm HAO film before (a) and after (b) RTA on p-type Si (100) substrate 80

Figure 4.2 SIMS analysis of Hf-Al-O film before RTA (a) and after RTA (b) (Analysis parameters: Ga Gun Energy: 25 KeV Current: 3.00 pA Area: 49.8×49.8 µm2 Sputter parameters: Ar Gun Energy: 0.50 KeV Current: 3.00 nA Area: 150×150 µm 2 ) 81

Figure 4.3 HRTEM images of 10.0 nm HAO film before RTA (a), and after RTA (b) Islands of Hf silicide are formed from interface reaction, and obviously reduced after RTA RTA temperature is 1000ºC in N 2 for 10 s The island is indicated by the circle in white .84

Figure 4.4 Capacitance-voltage and current-voltage characteristics of 10.0 nm HAO film before RTA (a) and after RTA (b) The driving frequency is 100 kHz The equivalent oxide thickness is 1.7 nm with dielectric constant at ~22.5 87

Figure 4.5 Flow chart showing the procedure of the measurement and stressing cycles in the developed program 89

Figure 4.6 Schematic diagrams showing the setup for the p-substrate capacitor biased in the (a) inversion and (b) accumulation mode .89

Figure 4.7 Energy band diagram of a capacitor when stressed in the (a) inversion and (b) accumulation mode 90

Figure 4.8 Constant voltage stress induced at accumulation (a) C-V curve, (b) I-V curve (Stress condition: 10 cycles at -0.01 mA followed by another 10 cycles at -1 mA) No major changes in C-V and I-V curves after 10 cycles stress .92

Figure 4.9 (a) Frequency dependence of C-V properties, the diameter of electrode is 200 µm (b) The leakage current density of the HAO film .94

Figure 5.1 Band alignments at HfO 2 /Si interface 101

Figure 5.2 The valence-band spectra of bulk silicon and HfO 2/Si system (left).The Si 2p core-level spectra of HfO 2 /Si system (right) .103

Figure 5.3 The valence-band and Hf 4f core-level spectra of HfO2 /Si system 104

Figure 5.4 The Hf 4f spectra of HfO2 /Si, HfO 2 /Si 0.75 Ge 0.25 and HfO 2 /Ge interfaces .105

Figure 5.5 The valence-band and Si 2p spectra of Si without and with HfO overlayer .107

Figure 5.6 The valence-band and Si 2p spectra of Si0.75 Ge 0.25 without and with HfO 2 overlayer .108

Figure 5.7 The valence-band and Ge 3p spectra of Ge without and with HfO2 overlayer .109

Figure 5.8 The Δ Gibbs free energy calculation of Co and HfO 2 reaction 112

Figure 5.9 Hf 4f (a) and Co 2p (b) core-level XPS spectra at different Co deposition time 113

Figure 5.10 Co 2p3/2 (a) and Co 2p1/2 (b) core-level XPS spectra at the first 5 minutes deposition 113

Figure 5.11 Co 2p3/2 and Hf 4f relative area ratio as a function of Co deposition time 114

Figure 5.12 (a) Valence-band spectra for HfO 2; (b) Hf 4f core-level spectra for HfO2 ; (c) Valence-band spectra for 20 Å Co/HfO 2; (d) Hf 4f core-level spectra for Co/HfO2 115

Figure 5.13 The Ru 3d core-level XPS spectra of RuO x/HfO 2 /Si system under different oxidation-state 118

Figure 5.14 The valence-band and Hf 4f core-level spectra of RuO x/HfO 2 /Si system 120

Figure 5.15 The schematic view of band alignment at RuO2/HfO 2 interface 120

Figure 6.1 Hf 4f and Si 2p core-level spectra for Ni/HfO2/n-Si stack as a function of Ni thickness (for 0.3, 0.6, 0.9, 1.3, 1.6, 1.9, and 2.5 nm Ni thickness) The shifts of the binding energy for Hf 4f 5/2 and Si 2p3/2 are indicated by discontinuity lines .129

Figure 6.2 Valence-band and Ni 2p spectra of the Ni/HfO2/n-Si stack as a function of Ni thickness For the clean HfO 2 surface, the VB edge is denoted at 3.80 eV The zero of binding energy corresponds to the Fermi level .129

Figure 6.3 The Fermi level positions with respect to the valence-band maximum of HfO 2 as a function of Ni and Co coverage on HfO 2/Si The n-type SBHs for Ni and Co on HfO2 are given 132 Figure 6.4 The band diagrams of Ni/HfO 2 stacks .133

Figure 6.5 Electronic band structures for c-HfO2 136

Figure 6.6 Total (solid line) and atom-projected (dotted line: O atom; dot-dashed: Hf) density of states (DOS) for c-HfO2 137

Figure 6.7 Relaxed interface structures for (a) 1L, (b) 2L, (c)3L, (d) 4L, and (e) 5L of Ni on HfO 2 (111) surface (Red atom: O; Deep blue: Ni; Light blue: Hf.) 139

Figure 6.8 PDOS for Ni atoms in different layer (from surface to interface) The Fermi level is at energy zero, denoted by the dotted line 141

Figure 6.9 PDOS for O atoms in different layer (from interface to surface) The Fermi level is at energy zero, denoted by the dotted line 143

Figure 6.10 PDOS for the O atom in the bulk region (O-5), calculated by Gaussian- based method (solid lines) and the tetrahedron method (the dotted lines) .143

supercell O-bulk: oxygen atom in the central layer of HfO 2 ; O-inter: oxygen atom at the interface; Ni-bulk: Ni atom in the central layer of Ni thin film; Ni-inter: Ni atom at the interface Accurate PDOS for O-bulk was also shown in dotted line to determine the VB edge of HfO 2 The Fermi level is at energy zero .144

function φm, eff , n(p)-type SBH Φn (Φp

), HfO 2 electron affinity χ, and the potential drop ΔE vac across the vacuum were shown The position zero is at the interface Values in the figure are in eV .148

LIST OF TABLES

Table 1.1 The dielectric constants and energy band gaps of various dielectric materials 11

Table 2.1 Reference binding energies (eV) .42

Table 4.1 Relationship of accumulation capacitance value with EOT 91

Table 5.1 Band alignments at HfO 2 /Si, HfO 2 /Si 0.75 Ge 0.25 and HfO 2 /Ge interfaces 110

Table 6.1 Comparison of experimental valence-band alignments for Ni on different dielectrics .134

Table 6.2 The rumpling parameters (%) for Ni layers in different thickness (from 1L to 5L) The number of layer was counted from the interface 140

Table 6.3 Calculated SBHs for Ni/HfO 2 interface with different thickness of Ni overlayer .144

LIST OF PUBLICATIONS

1 Q Li, Y F Dong, S J Wang, J W Chai, A C H Huan, Y P Feng, and C K

Ong, ”Evolution of Schottky barrier heights at Ni/HfO2 interfaces”, APPLIED PHYSICS

LETTERS, 88 (22), 222102 (2006)

2 Q Li, S J Wang, T H Ng, W K Chim, A C H Huan, and C K Ong,

“High-thermal-stability (HfO2)1-x (Al2O3)x film fabricated by dual-beam laser ablation”, THIN

SOLID FILMS, 504 (1-2), 45-49 (2006)

3 Q Li, S J Wang, W D Wang, D Z Chi, A C H Huan, and C K Ong, ”Growth

and characterization of UHV sputtering HfO2 film by plasma oxidation and low

temperature annealing”, JOURNAL OF ELECTROCERAMICS, 16 (4), 517-521 (2006)

4 Q Li, S J Wang, K B Li, A C H Huan, J W Chai, J S Pan, and C K Ong,

“Photoemission study of energy-band alignment for RuOx/HfO2/Si system”, APPLIED

PHYSICS LETTERS, 85 (25), 6155-6157 (2004)

5 Q Li, S J Wang, P C Lim, J W Chai, A C H Huan, and C K Ong, “The

decomposition mechanism of SiO2 with the deposition of oxygen-deficient M(Hf or Zr)Ox films”, THIN SOLID FILMS, 462, 106-109 (2004)

6 S J Wang, A C H Huan, Y L Foo, J W Chai, J S Pan, Q Li, Y F Dong, Y P

Feng, and C K Ong, “Energy-band alignments at ZrO2/Si, SiGe, and Ge interfaces”

APPLIED PHYSICS LETTERS, 85 (19), 4418-4420 (2004)

7 L Yan, L B Kong, Q Li, and C K Ong, “Amorphous (CeO2)0.67(Al2O3)0.33 high-k gate dielectric thin films on silicon”, SEMICONDUCTOR SCIENCE AND

TECHNOLOGY, 18, L39-L41 (2003)

8 S J Wang, P C Lim, A C H Huan， C L Liu, J W Chai, S Y Chow, J S Pan, Q

Li, and C K Ong, “Reaction of SiO2 with hafnium oxide in low oxygen pressure”,

APPLIED PHYSICS LETTERS, 82 (13), 2047-2049 (2003)

Chapter 1 Introduction

1.1 Introduction

The semiconductor industry has made rapid technological development over past forty years, which has enormous impact on our society and the global economy The success of the semiconductor industry relies on the continuous improvement of performance and the cost reduction of integrated circuits, which is mainly achieved by the shrinking of the device dimensions Throughout the semiconductor industry, the metal-oxide-semiconductor field effect transistor (MOSFET) is the most important device for integrated circuits such as microprocessors and semiconductor memories, because of its high performance, high speed, low static power, low fabrication cost and small size The rapid shrinking of dimension of the transistor makes exponential increase in the number of transistors integrated on a chip and 25~30% cost reduction per year The scaling of transistors follows the famous Moore’s law over forty years, which predicts that the number of components per chip doubles every eighteen months.1 Key elements enabling the scaling of transistors are the use of thermally grown silicon dioxide (SiO2) as gate dielectric and poly-silicon as gate electrode

The thermally grown SiO2, which is so far used as gate dielectric employed to isolate the transistor gate from the Si channel in MOS device, indeed offers remarkable physical

thermally grown on silicon and naturally forms a very stable interface with a low density

of intrinsic interface defects The band gap of SiO2 is quite large (~9 eV), which offers superior electrical isolation properties In addition, SiO2 presents excellent thermodynamically and chemical stability, which is required by the annealing steps at high temperatures (up to 1000ºC) in the fabrication process of transistors In short, the existence of the superb quality of thermally grown SiO2 offers the possibility of device scaling and allowed the fabrication of properly working MOSFET’s with SiO2 gate dielectric layers as thin as 1.5 nm

However, as will be discussed in the following sections, further scaling of the SiO2gate layer thickness below 1.5 nm is problematic.2,3 The first problem arising is that the gate leakage current due to direct tunneling of electrons through the SiO2 will be high (exceeding 1 A/cm2 at 1 V) when the thickness of the SiO2 layer is becoming so thin, which will increase the circuit power dissipation to a unacceptable value.4 Therefore, an

alternative dielectric with high dielectric constant, high-k dielectric material, employed to

achieve the equivalent capacitance density with relatively thicker physical thickness is required for the replacement of SiO2 for the high performance logic application and low operating power logic applications in coming generations.5 Nevertheless, the excellent electrical properties of SO2 present a significant challenge for any alternative gate dielectric candidate without doubt

Along with the replacement of SiO2 with the alternative gate dielectric, the doped poly-silicon which is currently used as gate is desired to be replaced by the metallic gate electrodes The use of stable metallic gate electrodes is expected to solve the issues of poly-silicon depletion effect and boron penetration as the further scaling of

dual-devices In addition, since the instability of poly-silicon is expected on most high-k

dielectric materials, the use of stable metallic gate electrodes is required to solve the

integration problems when the gate dielectric material is replaced by high-k dielectric

materials

In the following sections, a review of the scaling limits for SiO2 and current research works on high dielectric constant dielectric materials and metal gate electrodes are given

1.2 An overview of device scaling

Scaling of MOS device is the heart of growth of the semiconductor industry The industry’s demand for greater circuit functionality and performance at lower cost requires

a higher density of transistors on a wafer, which has mainly achieved by shrinking of the transistor feature size Reducing the length and width of channel can result in the increase

of the density of devices on the chip, while reducing the oxide thickness can improve the device speed by increasing the drive current of the transistor

The improved performance associated with the scaling of logic device dimensions can

be seen by considering a simple model for the drive current of a MOSFET.6 The drive current can be written (gradual channel approximation) as

D

D T G inv

where W is the width of the transistor channel, L is the length of the transistor channel, µ

is the channel carrier mobility, C inv is the capacitance density associated with the gate

dielectric when the underlying channel is in the inversion state, V G and V D are the

voltages applied to the transistor gate and drain, respectively, and the threshold voltage is

given by V T

Assuming constant mobility, a reduction in the channel length and/or an increase in

the gate dielectric capacitance is required to increase I D, which can be translated into higher speed, greater circuit functionality and performance at lower cost

For the gate capacitance, consider a parallel plate capacitance (ignoring quantum mechanical and depletion effects from a Si substrate and gate),

t

A

C=κε0 (1.2)

where κ is the dielectric constant of the gate material (also refer to the relative

permittivity in this literature, for SiO2, κ = 3.9), ε 0 is the permittivity of free space (ε 0 = 8.85×10-3 fF/um), A is the area of the capacitance, and t is the thickness of the dielectric

Obviously, a reduction in the thickness of gate dielectric is required in order to increase the gate dielectric capacitance to improve the drive current

Various scaling rules have been proposed including constant field scaling, constant voltage scaling, quasi-constant voltage scaling and generalized scaling In the commonly used constant field scaling, the transistor’s linear dimensions as well as the operating voltage are all scaled down by a factor of S (S<1), then the gate delay will reduce by a factor of S and the power per transistor will reduce by S3.7

Over past several decades, device dimensions have shrunk drastically and will continue according to the prediction of the International Technology Roadmap for Semiconductors (ITRS) to maintain the growth rate of the semiconductor industry In the state-of-art technologies, the thickness of SiO2 layer is around 1.5 nm which is

1.3 Limitations for gate oxide (SiO2) scaling

Since the birth of the MOS device, the amorphous, thermally grown SiO2 employed

to isolate the transistor gate from the Si channel as a gate dielectric SiO2 provides several key advantages including thermodynamically and electrically stable, high quality Si-SiO2interface as well as superior electrical isolation properties To achieve higher device performance, thinner gate dielectric is required, especially in the deep sub-micron regime The remarkable physical and electronic properties of SiO2 allow the rapid shrinking of gate dielectric’s thickness with the increasing performance of devices While thermal SiO2 of 70 nm in thickness in 1977, today’s MOSFETs in production have gate oxides of

~1.5 nm Since a mono-layer of SiO2 is about 3.5~4.0 Å, an oxide film of 1.5 nm consists

of only a few mono-layers of atoms Muller et al has clearly demonstrated that the

existence of a physical limit for SiO2 around 1.0-1.2 nm It is found that the full band gap

of SiO2 is obtained only after 2 monolayers of SiO2.8 When the interface bond length is included, this indicates that the thickness of 0.7-0.8 nm is required These results set an absolute physical thickness limit of SiO2 at 0.7 nm.9 One can imagine the difficulties of continuing scaling in this ultra-thin regime Besides the physical limitation mentioned, continued scaling of SiO2 layer thickness is limited by several issues, including gate leakage current, boron penetration, interfacial structure and reliability The limitations for gate oxide scaling will be discussed in this section

1.3.1 Direct tunneling leakage current

structure However, when electric filed or temperature is sufficient high, carrier conductance occurs in the real insulators resulting in the tunneling process from gate dielectric to Si channel

While SiO2 provides us with the remarkable properties as the gate dielectric, the gate leakage current increases exponentially as the oxide thickness scaled down Figure 1.1 shows the gate current density as a function of gate voltage for MOS capacitors with different SiO2 gate dielectric thickness The unacceptable high leakage current arises obviously with decreasing SiO2 thickness below 3.5 nm.10,11 The thermal oxide of thickness less than 1.5 nm has a gate leakage current density more than 1 A/cm2 at 1 V The high leakage current will cause problems of excessive power consumption and abnormal device characteristics Depending on the applications, a leakage current density

of 1 A/cm2 is regarded as the maximum tolerable gate leakage current density value from the power consumption viewpoint However, further down scaling increases the leakage current densities (>1 A/cm2) and renders the devices inoperative, setting a fundamental constraint on gate oxide scaling

As a matter of fact, the quantum mechanical direct-tunneling process dominates the flow of charge carriers in the ultrathin SiO2 gate layers thickness typically below 3 nm, which results in a large increase of the leakage current Figure 1.2 presents the quantum mechanical tunneling mechanism, the so-called direct tunneling process In this mechanism, the tunneling charge carriers directly flow through the trapezoidal energy barrier.12 The direct tunneling is a very strong function of the width of the barrier electron tunnels through (oxide thickness in MOS devices) and has smaller dependence on the gate voltage (Vg) It can not be easily suppressed or eliminated and is believed to be the

ultimate limitation on gate oxide scaling for MOS technology.13

Figure 1.1 Gate current density as a function of gate voltage for MOS capacitors with different SiO2 gate dielectric thickness.10,11

Figure 1.2 Schematic energy band diagram of direct tunneling of electron from the Si substrate to the gate in a turned on n-MOSFET (Si/SiO2/poly-Si gate structure)

Direct Tunneling

e

Si/SiO2/poly-Si

1.3.2 Boron penetration

There are other limiting factors regarding to SiO2 gate oxide scaling Most of the advanced CMOS process uses dual gate technology, in which p+ poly-silicon gate electrode is used in the p-channel MOSFET and n+ poly-silicon gate electrode is used in the n-channel MOSFET for its surface channel operation In the p-channel MOSFET, the

p+ poly-silicon gate is fabricated by implanting B or BF2 species followed by the activation of dopants In general, a relatively thick SiO2 can be a barrier for the B penetration However, the boron easily diffuses through oxide during thermal cycles when the oxide thickness is sub-20 Å When the boron penetration occurs, the device suffers shift in threshold voltage, increase in the sub-threshold leakage current, reduction

in the channel mobility as well as oxide reliability degradation with the increasing of charge trapping.14-16 The phenomena of boron penetration becomes more severe while a thinner oxide and a higher density of active dopants are required for the continued scaling

of MOS devices

1.3.3 Uniformity and reliability

In addition to the high leakage current and boron penetration issues with the scaling

of SiO2 thickness, an equally important issue is uniformity and reliability aspects of oxide While the thickness of oxide is down to 2 nm, it is a formidable task for manufacturing such a thin dielectric with good uniformity across the wafer In addition to that, the oxide reliability which is defined by the defect related breakdown becomes a major problem

ultrathin SiO2 regime as a percolation model, which points out that the oxide breakdown comes out from a complete path built up by many defects within the SiO2 layer after a certain amount of stress.17,18 Both charge-to-breakdown (Qbd) and time-to-breakdown (Tbd) data show that the thinner oxide has higher breakdown field strengths inside It is clear that SiO2 is approaching its physical intrinsic limitations

Despite many excellent properties of SiO2, it must be replaced because of the several limitations as discussed above The concerns regarding high leakage currents, boron penetration and reliability of ultrathin SiO2, as early as 10 years ago, have led to incorporate nitrogen in to SiO2 (such as oxynitrides and oxide/nitride stacks) as near-term gate dielectric alternatives Indeed, the addition of N to SiO2 greatly reduces the leakage current and boron penetration with better reliability However, the scaling with oxynitrides and oxide/nitride stacks appears to be limited to teq = ~13 Å by the effects of gate leakage, reliability and mobility degradation.19

It is necessary to replace the traditional SiO2 with a physically thicker layer of oxides

of higher dielectric constant (k) Intensive research is underway to develop oxides into

new high quality electronic materials

1.4 Alternative high-k gate dielectrics candidates and

materials properties considerations

The industry’s demand for greater integrated circuit functionality and performance at

gate dielectric of SiO2 thickness meets the fundamental limitations, which is not easy to

be suppressed by merely improving oxide’s process technology

From an electrical point of view, considering the MOS structure as a parallel plate capacitor (refer to equation 1.2), an alternative way of increasing the capacitance is to use

a dielectric with a higher relative dielectric constant (k) than SiO2 instead of decreasing the thickness of SiO2 For example, a dielectric with a relative permittivity of 16 affords a physical thickness of 40 Å to achieve the equivalent capacitance of teq = 10 Å Continued scaling of CMOS device is demanding a gate dielectric with a higher permittivity (k) than

that of SiO2 to achieve lower electrical thickness (or higher gate capacitance) with a larger physical thickness

To find a suitable high-k material for gate dielectric applications is clearly essential

The choice of materials for this application requires two sets of properties One set encompasses fundamental materials properties that include permittivity, film morphology, barrier height, and stability in direct contact with Si The other set includes interface quality, gate compatibility, process compatibility and reliability Only the candidate reaching both of these criteria can be the future gate dielectric

The first requirement of high-k material is that the oxide should have k over 10 (k for

SiO2 is 3.9 and Silicon Nitride is around 7) In general, the atomic (or ionic) radius increases with the increasing of the atomic number of the metal, leading to a higher dielectric constant.20 And for high-k materials, the dielectric constant value and band gap

generally exhibit an inverse relationship From the empirical relationship between energy band gap (Eg) and the dielectric constant (ε) established by Duffy for simple elemental

materials or binary compounds:21

2

320

⎥⎦

⎤

⎢⎣

⎡+

=ε

g

E (1.3)

This equation indicates that a material having large dielectric constant tends to have a narrower band gap Although Duffy’s equation can not describe the dielectric constant of thin films accurately, it dose show the trend that energy band gap decreases with the increase of the dielectric constant Therefore, in selecting a gate dielectric, the trade off should be made between dielectric constant and band gap Table 1.1 summarized the dielectric constants and energy band gaps of various dielectric materials.22

Table 1.1 The dielectric constants and energy band gaps of various dielectric materials

Electrical properties of the high-k gate dielectrics are also a critical point to consider

for use in CMOS devices Generally, a large band gap (Eg) corresponds to a large conduction-band offset (ΔEc) The high-k dielectric must act as an insulator which

conduction by Schottky emission of electrons or holes from Si into the oxide bands So the required permittivity must be balanced against the band gap for the tunneling process

In practice, the conduction-band offset is usually smaller than the valence-band offset which requires the choice of dielectric to those with band gaps over 5 eV The

calculations by Robertson and Chen including many high-k dielectrics show that ΔEc is

~2.3-2.8 eV for Al2O3 and Y2O3, and ΔEc is ~1.5 eV for ZrO2 and ZrSiO4 as shown in Fig 1.3.18,23

Figure 1.3 Band offset calculations for a number of potential high-k gate dielectric

materials.23

In most cases, the interface with Si plays an important role in determining the overall

electrical properties of MOS devices Intensive studies of high-k materials show that they

the thermodynamics of these systems and thereby attempt to control the interface with Si

As a starting point, high-k dielectric (such as Ta2O5 and TiO2) has been employed mainly in memory capacitor applications Thermodynamic stability on Si is not a requirement for memory capacitors because the dielectric is in contact with the electrodes (typically nitride poly-silicon or metal) instead of Si Reaction at the Ta2O5/Si interface is observed resulting in the formation of a thin SiO2 layer.24,25 Although the underlayer of SiO2 will help maintain a high channel carrier mobility with high quality SiO2-Si interface, the thin film of SiO2 between Ta2O5 will reduce the total capacitance of the stack It is clear that the inherent thermal instability in direct contact with Si is the main limitation to be as a gate dielectric In addition, the conduction band offset of Ta2O5 with

Si is too small (0.3 eV)

The TiO2 system has been heavily studied because it has a high permittivity of k at

80-110, which is depending on the crystal structure and method of deposition It is important to note that all studies on TiO2/Si system have reaction interfacial layer at the channel interface.26,27 The thermodynamically instabilities for the Ta-Si-O and Ti-Si-O systems are in good agreement with the analysis of the Gibbs free energies.28

In contrast to the Ta and Ti system, the metal oxide ZrO2 is predicted to be thermodynamic stable in direct contact with Si up to high temperatures from ternary phase diagram.29,30 Because the chemical similarities between Hf and Zr, the thermodynamical stability is expected to be the same for the Hf-Si-O system.31 In addition, HfSiO4 as well as a large range of (HfO2)1-x(SiO2)x compositions will be stable

in direct contact with Si up to high temperatures, which indicates that the Si interface should allow for control.32-35 However, even though HfO2 is thermodynamic stable

against the decomposition as Hf and SiO2,36 the formation of a thin interfacial layer (oxides, silicates and silicides) has been reported.37-39 From results of ab initio

calculations based on density functional theory, Si substitutional defects are most likely form in HfO2 leading to the formation of a silicate layer at the HfO2/Si interface.40 The formation of interfacial layer is depending on the deposition method and condition.41-44 It

is likely to form a (HfO2)1-x(SiO2)x layer with the silicon atoms from the Si substrate.45-46

The permittivity of the silicate interface is likely to be lower than in the pure HfO2 film (k

~6 for x≈0.4).47 Extensive research efforts have been directed to interface engineering control.48 It is reported that the deposition conditions and post deposition annealing have impacts on the ΔEc of high-k materials with respect to Si, depending on the formation of

interfacial layer.49 To prevent the formation of the silicate layer, deposition of HfO2 in an oxygen-deficient condition is suggested.36,40

The gate dielectric must have a high-quality interface with low-defect-density

interface and low defects with Silicon In general, the high-k dielectrics show larger

interface state density Dit (~1011-1012 states/cm2) than that of SiO2 (Dit ~2×1010states/cm2), resulting in a substantial flat band voltage shift larger than 300 mV In

addition, all of high-k gate dielectrics suffer from intrinsic problem of higher oxygen

vacancy density than SiO2, which lead to higher leakage current, lower carrier mobility, and threshold voltage shift.50 Compared to the properties of SiO2, there are three reasons

for more defects in high-k dielectrics Firstly, oxygen vacancies are easily formed due to

low heat of formation Secondly, their bonding is ionic and they have higher coordination

number which means the high-k dielectrics are poor glass former.51 The third reason is that the oxide is not so able to relax and re-bond to remove defects

Considering the binary oxides which are more thermally stable in direct contact with

Si, including Al2O3, ZrO2, and HfO2, the bonding constraints must be considered.52 The oxygen vacancy is the main defects in ZrO2 and HfO2 according to the calculation results

by Foster et al.53,54 It is found that oxygen vacancy is a main source of charge traps in transistor based on HfO2, because HfO2 is energetically favorable for the vacancy to trap charges due to large electron-lattice interaction.55 The interfacial layer formed by a few mono-layers of SiO2 between high-k and Si is expected to exhibit encouraging device properties which provide a better interface to Si channel than pure high-k dielectric The

interface engineering is important to obtain high quality interface Fortunately, the incorporation of interlayer (such as SiO2, Si3N4, and SiON) has no significant influence

on the barrier height suggesting a negligible variation of the interface dipole.56

Recently, it was found that atomic nitrogen is favorable to form couples with oxygen

vacancies in the high-k gate dielectrics rather than molecule oxygen, which lead to

effective passivation of oxygen vacancies and significant lower leakage current.57-59 In addition, atomic nitrogen can effectively block oxygen diffusion towards and inhibit growth of interfacial SiOx layer However, the nitrogen incorporation may decrease the

band gap and both of valence and conduction-band offsets of high-k dielectrics relative to

Si because of the atomic nitrogen incorporated into interstitial site.60 Post-nitridation annealing was found effectively increase the band gap and band offset of as-nitrided dielectric film by activating interstitial N atoms to form stable N–Hf bonds.56 The effects

of nitrogen incorporation on the electronic structure of high-k dielectrics have been

studied in detail in our group for HfO2, LaAlO3, and SrTiO3 films by photoemissions and the first-principles calculations to understand the microscopic mechanism.61,62

All of the earlier mentioned materials (Ta2O5, TiO2…) clearly have advantages as

high-k gate dielectrics, but they also have undesirable properties for replacing SiO2

Among high-k dielectrics, HfO2 (same as ZrO2, which have similar chemical properties)

is emerging as the leading candidate to substitute SiO2 As mentioned above, the reported

k value for HfO2 is relatively high (k ~25) and HfO2 is expected to be thermodynamicly stable in direct contact with Si As discussed previously, their band offset and barrier heights are suitable

A first major challenge is related to structure The real oxide is amorphous However,

it is reported that HfO2 undergoes polymorphic transformations as a function of temperature The poly-crystallization of HfO2 at relatively low temperature will make increasing leakage current along grain boundaries.63 One optional way is using the pseudo-potential binary oxides as gate dielectric, such as Hf-aluminates ((HfO2)1-

x(Al2O3)x), which remains stable up to 900-1000ºC while keeping amorphous structure.

64-66 Another advantage of Hf-aluminates is that Al2O3 is a good oxygen diffusion barrier which may reduce the rapid oxygen conduction from HfO2 to form interfacial layer

Finally, it should be noted that the interfacial layer between high-k and semiconductor

plays an important role and the interface engineering is the key for HfO2 to be used in CMOS technology There are intensive needs to explore the mechanism and atomic-structure at the interface and find a way to deposit a high quality HfO2 thin film with acceptable physical and electrical properties

1.5 Metal gate candidates and materials properties considerations

Poly-silicon has been used as MOSFET gate electrode for several decades The low charge carrier density of poly-silicon near the gate electrode/dielectric interface (less than

1021 carriers per cm3) gives rise to a depletion layer at the gate/dielectric interface under gate inversion condition As the continuing scaling of MOS devices, the poly-silicon depletion effect will be a major problem and will most likely be unacceptable for the coming sub-65 nm MOSFET because such a depletion layer will contribute to the increase of dielectric thickness and compromise the effort in the reduction of EOT Therefore, it becomes essential to replace the poly-silicon by new metal materials with higher charge carrier densities

In addition, along with the replacement of SiO2 with high-k dielectrics, the

dual-doped poly-silicon is desired to be replaced by metal gate because it is expected that

poly-silicon will not be stable on most high-k dielectrics since it can react to form

silicides Therefore, for long term CMOS scaling, metal gate should replace poly-silicon

as the gate electrode for future MOS devices The most important selection criteria for an alternative metal gate electrode are listed below:

(1) High conductivity and high active electrical concentration

(2) Appropriate work function Фm for NMOS and PMOS to get low threshold voltages

(3) Thermal and chemical stability under high temperatures

(4) Compatibility with CMOS process and integration

Taking into account quantum effect on device drive current, the Фm for NMOS and PMOS gate electrodes must be around 4 eV and 5 eV, respectively.67 The first approach is

to use a single midgap metal with a work function around 4.5 eV for both NMOS and PMOS devices However, the major disadvantage is that the threshold voltage will be

~0.5 V which is much too large for sub-0.1 μm MOS devices The other alternative way

is to involve two metal electrodes for NMOS and PMOS separately There are several metal candidates with work function near 4 eV for NMOS (such as Al, Ta, Mo, Zr, Hf, V, and Ti) and several metals with work function near 5 eV for PMOS (such as Co, Pd, Ni,

Re, Ir, Ru, and Pt for PMOS)

However, most metal gate electrodes with low work function suffer from temperature instability.68 In general, metal gates for NMOS (such as Al, Ta, Mo, Zr, Hf, V, and Ti) react with underlying dielectrics, resulting in poor insulating properties In finding low work function metals with good thermal stability, one option is to introduce

high-N and/or Si in to metals Optimized metal alloys can provide the desired work function with good thermal stability (such as TaN and TaSixNy) For the higher work function metal gate for PMOS, elements are all stable on most dielectrics under consideration The possibility of conductive oxides as alternative gate electrode is attractive and expected to resolve the problem of interfacial oxidation and to reduce the oxygen vacancies at the interface In general, the work function of metal oxide is greater than that of the corresponding metal because adding oxygen into metals modulate the work function while keeping high conductivity Conducting ruthenium oxide, RuO2 with large work function (~5.0 eV), low resistivity and excellent stability have attracted much attention as

a potential alternative electrode candidate for PMOS

It should be noted that the work function of metal gate in contact with high-k

dielectric (effective work function) generally differs from its vacuum work function.69The effective work function is sensitive to the interface structure and chemistry.70 Fermi

Level pinning at the metal/high-k dielectric interface was investigated.71,72 It was supposed that the interface dipole formed at the interface is the intrinsic cause for the effective work function differs from vacuum value However, how the interface chemical bonding determine the Fermi level pinning remains unknown Therefore, the detail

studies on the interface between potential metal gate electrodes and high-k dielectrics are

still demanding

For CMOS technology the dual metal gate will require two metal deposition steps which will result in complex integration process (two additional non-critical photolithography steps) One alternative way is to introduce a certain species to modulate the work function of the metal gate, which has been demonstrated on Mo by implanted with N to get higher work function.73 Another approach is including one layer of heterovalent metal to chemically tune the Schottky barrier for different work functions, which has been presented on Ni/ZrO2 system.74

1.6 Band alignments at metal/high-k/semiconductor

interfaces

In modern electronic devices, the semiconductor interfaces play a crucial role Band

controls the transport properties of electronic devices.75,76 The band discontinuity includes the valence and conduction discontinuities that accommodate the difference in bandgap between the materials, namely the valence-band and conduction-band offsets

(VBO and CBO) in the case of semiconductor heterojunctions and the n-type (for electrons) and p-type (for holes) Schottky barrier heights (SBH) in the case of

metal/semiconductor(or oxides) system As addressed in section 1.4, a key requirement

for an alternative high-k gate oxide is that it acts as a potential barrier to both electrons

and holes, which require that the band offset should be over 1 eV for both conduction and valence-band in order to inhibit Schottky emission of electrons or holes into their bands

In addition, the n-type SBH (for electrons) or effective work function of metal gate on high-k dielectric should be tunable in range of ~1.1 eV (the magnitude of Si band gap)

1.6.1 Band offsets at high-k dielectric/semiconductor interfaces

Concerning the high-k dielectrics application, the barrier at each band or “band

offset” should be over 1 eV for both valence and conduction bands Figure 1.4 shows

valence-band and conduction-band offset between the Si and the oxide For some high-k

dielectric with narrow band gap, such as SrTiO3 (band gap of only 3.2 eV), the band alignment must be symmetrically with respect to both conduction and valence-band edge

of semiconductor substrate to ensure enough band offset (>1 eV) Therefore, it is very

important to accurately determine the band offsets for high-k dielectrics on

semiconductor substrates

Figure 1.4 Schematic band diagrams for metal/oxide/Si stacks Definitions of band

offsets (VBO and CBO) and of SBHs (Φn and Φp) are shown.

The band offsets of the various dielectrics can be determined experimentally Several experimental techniques for determining the barrier heights or band offsets (band

alignments) for thin films including x-ray photoemission spectroscopy,77 infrared absorption or photoluminescence excitation spectroscopy,78 transport methods (capacitance-voltage and current-voltage techniques),79 internal photoemission spectroscopy,76 and first-principles simulations using density functional theory have attracted much attention.70,80-82 Among these, x-ray photoemission spectroscopy has produced reliable band offsets for a variety of metal/high-k/semiconductor systems.83 By photoemission spectroscopy method, the valence-band offset is directly determined by measurement of the valence-band maxima located by extrapolating the spectra of oxide and semiconductor substrate, while the conduction-band requires a value of the band gap

A more accurate method involves a comparison to the core levels based on the model

and of the oxide is assumed to lie at a fixed energy above their respective bulk core-levels, which can be measured on bulk samples (or thick films) The difference of the semiconductor substrate and oxide core-levels can be used to determine the valence-band offset, as shown in equation (1.4):

ΔE v =(E Si2p −E v,s)Si −(E A−E,d)dielectric s −(E Si2p −E A)dielectric s/Si (1.4) where ESi2p and Ev,s are the core-levels and VBM of the semiconductor substrates, EA and

Ev,d are the core-levels and VBM of bulk oxide samples (or thick oxide films) For the thick oxide films used, the thickness should be much larger than the photoelectron mean-free path, and it can represent the properties of bulk oxide materials The last term in the equation is the energy difference between the chosen core-levels ESi2p and EA in a oxide/semiconductor heterojunction

It is noticed that the interfacial structures can be varied under different growth

condition and process for a given high-k dielectric/semiconductor system In this thesis,

the band offset of HfO2/semiconductor (Si, Si0.75Ge0.25 and Ge) system have been

investigated using x-ray photoemission spectroscopy method

1.6.2 Barrier heights at metal gate/high-k dielectric interfaces

Metal gate is proposed to replace poly-silicon as gate electrodes However, the

integration of metal gates with high-k dielectrics has been proven to be a challenge.72 The major requirement is that the Fermi level position of metal gate should be located within

±0.1 eV of the Si valence-band edge and conduction-band edge for p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS), respectively Effective work function (Φm, eff )

the work function (WF) of metal in contact with high-k dielectric (effective WF)

generally differs from its vacuum WF and the effective WF is strongly dependent on the interface structure and chemistry.85-88

Using photoemission method, the effective work function can be directly determined

by barrier heights of metal/high-k dielectrics interface and high-k dielectrics/silicon

interface separately, expressed by Φm,eff = Φn-CBO+EA, where Φn is the n-type SBH at metal/high-k dielectrics interfaces, CBO represents the conduction-band offset between high-k dielectrics and Si, and EA is the electron affinity of Si (4.05 eV), which is the

energy difference between conduction-band minimum (CBM) of Si and vacuum level It

is noticeable that the effective work function is sensitive on the structure at metal

gate/high-k dielectrics interface

In this thesis, the formation mechanisms of SBH at metal gate/high-k dielectrics

interface, namely metal/semiconductor interfaces, have been investigated both experimentally and theoretically

1.7 Motivations and scope for present work

The main purpose of this research is to study the physical, electronic and electrical properties of the HfO2 thin film as a potential replacement for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology

In this study, specific objectives were:

(1) To study the material and electrical properties of the HfO2 thin films deposited on

control) The aim of this work is to study the thermodynamic and thermal stability of the HfO2 thin films, including the effects of the post-treating (rapid thermal annealing) and interface structure on the thin HfO2 films

(2) To study the material and electrical properties of the (HfO2)1-x(Al2O3)x thin films deposited on Si substrate using dual-beam pulse laser deposition technique This work will provide useful information on the effects of Al2O3 alloyed in HfO2

(3) To study the band alignments at the interface of metal/HfO2/Semiconductor stacks

In situ XPS will be performed The substrate-dependent of band alignments is

investigated in this work This work is expected to provide valuable information for

choosing proper high-k gate dielectrics The electronic structure of RuO x as a promising metal oxide gate electrode candidate will also be studied in detail for PMOS application

(4) To understand the formation mechanism of SBHs at metal gate/high-k dielectrics,

the evolution of SBHs at Ni/HfO2 interfaces is studied in this work Meanwhile, principles calculations will be performed to study the physical mechanisms of the

first-evolution of SBHs

The physical and electrical properties studies on HfO2 film is expected to provide valuable information on how to engineer HfO2 to be used as an alternative gate oxide to replace traditionally SiO2 in the ultra-large semiconductor integration In addition, the study on the physics at the dielectric/Si interface and metal/dielectric interface may elucidate the mechanism at the interface from the physical perspective, which may offer guidance on how to tune the interface band offset to meet the different needs in the electronic applications

In this study, the main research focused on the physical, electronic and electrical

properties of HfO2 thin film as a gate dielectric In addition, the barrier heights of selected metal on HfO2 have been studied to investigate the dependence of effective work function on metal/HfO2 stacks

This thesis is organized as follows:

This thesis contains 7 chapters including this introduction In next chapter, a description of the methodology and setting of experiments will be introduced The principles of fabrication methods and the characterization methods will be given in detail Chapter 3 presents HfO2 fabricated by ultra high vacuum sputtering and treated with rapid thermal annealing in different high temperature The capacitance-voltage (C-V) characteristics at high frequency were investigated The dielectric constants were extracted from C-V curves for all samples The annealing effects on electrical properties are described In chapter 4, the experiment results of (HfO2)1-x(Al2O3)x by dual-beam pulse laser deposition are presented Highly thermal stable (HfO2)1-x(Al2O3)x had been successfully fabricated and characterized The fabrication methods and sample characteristions are also included in this chapter Chapter 5 presents substrate dependent barrier heights of HfO2/semiconductor (Si, Si0.75Ge0.25 and Ge) stacks and band alignments at metal/HfO2/Si interfaces The investigation of the evolution of the barrier height at metal/HfO2 interface was described in chapter 6 Finally, the summary of this thesis and recommendations for future work were presented in chapter 7

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