Chapter 11_Memory Devices

Lecture: DIGITAL SYSTEMS Nguyen Thanh Hai, PhD Chapter 11: Memory Devices Faculty of Electrical & Electronic Engineering University of Technical Education Faculty of Electrical & Electro

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Lecture:

DIGITAL SYSTEMS

Nguyen Thanh Hai, PhD

Chapter 11:

Memory Devices

Faculty of Electrical & Electronic Engineering

University of Technical Education

Memory Devices

11.1 Introduction

11.2 ROM Architecture

11.3 Flash Memory

11.4 RAM Architecture

11.5 Cache Memory

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11.1 Introduction

Types of memory devices

Memory Devices

4

0

A

1

A

2

A

3

A

4

A

3

I I2 I1 I0

W R/

ME

4

32 × Memory

outputs Data

3

O O2 O1O0

MSB

inputs

Address

inputs Data

command Read/write

enable Memory

0 1 1 0

1 0 0 1

1 1 1 1

1 0 0 0

0 0 0 1

0 0 0 0

.

1 1 0 1

0 1 1 1

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

.

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

cells Memory Addresses

3

D D2 D1 D0 A4 A3 A2 A1 A0

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.

1 1 1 1 0

Addresses

.

0100

1101

WRITING the data word 0100

into memory location 00011

READING the data word 1101 from memory location 11110

3

I I2 I1 I0 O3 O2 O1 O0

3

A A2 A1 A0

4

A

output

Memory Devices

bus Address

IC

Memory IC bus

Data

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11.2 ROM (Read Only Memory)

ROM block diagram

Address decoder

Controller

Registers R/W

Output buffer

D0

D7

CE1

CE2

CE3

Control

bus

Data bus

A9

A0

Address

bus

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11.2 ROM

0 A 1 A 2 A 3 A

8

16 × ROM

select) (Chip CS

∇

inputs Address

input Control

3 D 4 D 5 D 6 D 7 D

0 D 1 D 2 D

tristate

=

∇

- 1 register = 8 bits = 1 byte

- 4 addresses for 16 register locations

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Address

Memory Devices

11.2 ROM

A 3 A 2 A 1 A 0 =0001

Memory cell R 1

R 1 contains 8

data bits

(D 0 -D 7 )

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Example 11.5

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Example 11.6

Memory Devices

Example 11.7

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11.2.1 EPROM (Erasable Programmable ROM)

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- EPROM can be used to program, erase or reprogram as often as desired.

- To erase an EPROM cell programmed, we can use ultraviolet (UV) light through a window of the EPROM as show in Figure above.

-After erasing, EPROM can be reprogrammed and programming can be done using a circuit.

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11.2.2 EEPROM (Electrically Erasable PROM)

EEPROM

AT28C64B, 64K =

8K x 8 bits

Memory Devices

11.3 Flash Memory

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11.4 RAM Architecture

Memory Devices

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11.4.1 SRAM (Static RAM)

- SRAM using many

transistors to supply for bit

lines (BL)

-This is different from

DRAM

-Types of SRAM: TMS4016

and 6264, …

-M1, M2 and M3, M4: transistor

sets used to switch off or on.

-Word Line (WL) and Bit Line

(BL) used to control M5 and M6

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11.4.2 DRAM (Dynamic RAM)

- A cell

designed

using row

and column

to control

MOSFET

and a

capacity is

to charge

or recharge

for 0 or 1

level.

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Memory Devices -TMS 4116: capacity 16 K

x 1 bit

- 41256: capacity 256 K x

1 bit

- RAS =1 (Raw Address

Strobe): DRAM will

receive Raw address from

A – A

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Expanding Capacity of RAM

A RAM 32Kx4 generated by using 2 RAMs 16Kx4

-CS inverted

using

common line,

AB 4 through

NOT gate to

select RAM

-Two groups

of Data lines

in common

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Nguyen Thanh Hai, PhD Another way to generate a RAM 32Kx4 using 2 RAMs 16Kx4

CS

inverted

using

common

line

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Nguyen Thanh Hai, PhD A way to generate a RAM 32Kx8 from 2 RAMs 16Kx8

-CS inverted

using

common

line, AB 4

through NOT

gate to

select RAM

-Data lines

not to be in

common

Memory Devices

11.5 Cache Memory

CPU

CPU CPU SRAM Cache

Cache Controller

DRAM main memory

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Diagram of a cache in the CPU system

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Diagram of a CPU memory cache

-Thousands or millions of bytes of internal memory (RAM and ROM) -To store programs and data that CPU needs during normal

operation

-For economy, in some systems CPU can need a block of high-speed cache memory for processing something However it is not for all

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Page 11.16 – 11.18

-Cache memory often has architecture as RAM (SRAM) and in some specific cases, it can use DRAM chip

-Cache memory has high speed and is located between a main memory and CPU

-Usually to store instructions and data that CPU can access easily -There are two levels of cache memory, L1 and L2, in which L1: for processing instructions and data, L2: being the external

memory

-L1 and L2 have capacities from 2kB-64KB and 256KB – 3MB

Memory Devices

-Take a look Examples from pages

- Homework

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