Chapter 5_FF_Related Devices

Lecture: DIGITAL SYSTEMS Chapter 5: Flip_Flops and Related Devices Nguyen Thanh Hai, PhD Faculty of Electrical & Electronic Engineering University of Technical Education Faculty of Elect

Lecture:

DIGITAL SYSTEMS

Chapter 5:

Flip_Flops and Related Devices

Nguyen Thanh Hai, PhD

Faculty of Electrical & Electronic Engineering

University of Technical Education

Faculty of Electrical & Electronic Engineering

Flip-Flops and Related Devices

5.3 Clock signals

Flip-Flops and Related Devices

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Nguyen Thanh Hai, PhD

5.1 NAND Gate Latch

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Flip-Flops and Related Devices

Flip-Flops and Related Devices

5.1 NAND Gate Latch

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5.2 NOR Gate Latch

Flip-Flops and Related Devices

S

R

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Flip-Flops and Related Devices

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Nguyen Thanh Hai, PhD

Example 5.2:

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Nguyen Thanh Hai, PhD

University of Technical Education

Faculty of Electrical & Electronic Engineering

Flip-Flops and Related Devices

LOW input clock pulse

Negative transition input clock pulse (edge- triggered)

Flip-Flops and Related Devices

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Nguyen Thanh Hai, PhD

• The circuit for generating a narrow clock pulse Ck with positive transition (edge)

University of Technical Education

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Flip-Flops and Related Devices

• The circuit for generating a narrow clock pulse Ck with negative transition (edge)

Flip-Flops and Related Devices

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Flip-Flops and Related Devices

5.4 Clocked S-R Flip-Flop

Flip-Flops and Related Devices

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Flip-Flops and Related Devices

5.5 Clocked J-K Flip-Flop

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Nguyen Thanh Hai, PhD

5.5 Clocked J-K Flip-Flop

) 0 , 1 , 1 , 1 (

1 1

* 0

=

Q Q K J

) 0 , 0 , 1 , 0 (

0 0

* 0 1 0

=

Q Q K J

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5.5 Clocked J-K Flip-Flop

Flip-Flops and Related Devices

D

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5.6 Clocked D Flip-Flop

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D-FF with its waveforms with negative edge clock

5.6 Clocked D Flip-Flop

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5.7 D Latch

D-Latch with waveforms

Enable=1, D=1, Q=1 Enable=1, D=0, Q=0

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Nguyen Thanh Hai, PhD

5.7 D Latch

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Flip-Flops and Related Devices

Example 5.3:

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Nguyen Thanh Hai, PhD

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Example 5.4:

Flip-Flops and Related Devices

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Nguyen Thanh Hai, PhD

University of Technical Education

Faculty of Electrical & Electronic Engineering

Flip-Flops and Related Devices

5.7 Asynchronous Input

Flip-Flops and Related Devices

CLK PRE

CLR

V

5

+

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Nguyen Thanh Hai, PhD

5.8 Flip-Flop Synchronization

CLOCK

Debounced

switch

A

X

CLOCK

A Q X

1

T 1 4 4 4 4 2 4 4 4 4 3

Pulses Complete

2

T

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5.9 Data Storage and Transfer

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Nguyen Thanh Hai, PhD

Parallel data transfer of contents of register X into register Y

Transfer

1

X

1

X

2

X

2

X

3

X

3

X

1

Y

1

Y

2

Y

2

Y

3

Y

3

Y

4 4 4 4 4 4

4 4 4 4 4 4

6 Register X

4 4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 4 2 1 Y Register

5.9 Data Storage and Transfer

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5.10 Serial Data Transfer: Shift register

3

X

3

X CLK J

K

2

X

2

X CLK J

K

1

X

1

X CLK J

K

0

X

0

X CLK J

K

IN

DATA

Pulse

Shift

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Nguyen Thanh Hai, PhD

pulses Shift

3

X IN DATA

5.10 Serial Data Transfer: Shift register

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5.11 Microcomputer Application

3

X D

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Nguyen Thanh Hai, PhD

5.12 Analyzing Sequential Circuits

X

X CLK

J

K

Y

Y CLK J

K

Z

Z CLK J

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5.12 Analyzing Sequential Circuits

input Clock

Z Y X W

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5.13 Clock Generator Circuits

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Flip-Flops and Related Devices

5.13 Clock Generator Circuits

C R 693

.

0

t 1 = b

)C R (R 693

.

0

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Change of states between Flip-Flop types

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Current

state Next state

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-Take a look Examples from pages

- Homework

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The End