báo cáo nhóm KIẾN TRÚC MÁY TÍNH MULTICYCLE MIPS

Recall: Simple Datapath Instruction memory +4 rt rs rd Registers ALU Data memory imm Data Data Address Controller Opcode, funct Address Instruction... Recall: R-format Dat

04/2012

KIẾN TRÚC MÁY TÍNH

MULTICYCLE MIPS

GV : Nguyễn Đức Minh

SV : Đào Đăng Toàn

Nguyễn Quốc Đạt Nguyễn Đăng Hoàng Vũ

Phạm Hồng Đức Nguyễn Đức Hiếu

Review

• Sự xây dựng Datapath

– Xác định loại lệnh

• R-format

• Rẽ nhánh có điều kiện

• Rẽ nhánh không điều kiện

• Load/store

– Tiến hành xây dựng modul Datapath (RF, ALU,

Memory, SignExt)

– Kết nối các modul

• Datapath đơn xung nhịp

– Tất cả các lệnh thực hiện trong một xung (CPI = 1) – Thời gian một chu kỳ được xác định bằng độ dài đường

dữ liệu dài nhất

– Chu kỳ đồng hồ được đặt theo lệnh chậm nhất (load)



Overview – Multicycle Datapath

• Mỗi lệnh có nhiều stage (tầng)

• Mỗi stage mất nhiều chu kỳ

1 IF

2 ID / RF

3 EXE

4 MEM

5 WB

 Mỗi stage có thể sử dụng lại hardware từ stage

trước

 Sử dụng hiệu quả hơn của phần cứng và thời

gian

Tất cả các lệnh sử dụng cái này

Recall: Simple Datapath

Instruction

memory

+4

rt

rs

rd

Registers ALU

Data memory

imm

Data

Data

Address

Controller

Opcode, funct

Address

Instruction

Recall: R-format Datapath

• Format: opcode r3, r1, r2

Result

Zero

ALU

Read Data 1

Read Data 2

Read Reg 1 Read Reg 2 Write

Register Write Data

Register Write

ALU op

Register File 3

Instruction

Recall: Load/Store Datapath

Recall: Branch Datapath

Multicycle DP

Instr Fetch Instr Decode/Data Fetch Execute

Multicycle DP

Làm thế nào để xây dựng multicycle datapath (DP)

1 Thay 3 ALUs từ single-cycle DP bằng một ALU

2 Thêm 1 multiplexer chọn đầu vào cho ALU

3 Thêm 1 control line cho đầu vào chọn kênh của ALU

• Đầu vào mới: Constant = 4 [PC + 4]

• Sign-ext., shifted offset [BTA calc.]

4 Thêm các thanh ghi trung gian (buffer)

• MDR: Memory Data Register

• IR: Instruction Register

• A,B: ALU operand registers

• ALUout: ALU output register

Multicycle DP

Multicycle DP: 1-bit Ctl Signals

Multicycle DP: 2-bit Ctl Signals

Making Sense of Multicycle DP

Step 1: Decompose the MC/DP execution sequence into cycles Step 2: Examine which cycles apply to which instructions

One-Cycle Steps R-fmt lw sw beq j

1 Instruction Fetch

2 Instruction Decode / Data Fetch

3 ALU ops / R-format Execution

4 R-format Completion

5 Memory Access Completion

Multicycle DP: R-format

Step 1: Fetch instr // Store in IR // Compute PC + 4

Step 2: Decode instruction: opcode, rd, rs, rt, funct fields

Data fetch: Apply rs, rt to Register File

Data Read into A,B buffer registers (ALUin)

Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop)

ALU output goes into ALUout register

Step 4: ALUout register contents written to Register File write input

Register number in rd written (Assert: RegWrite,RegDst) CPI for R-format = 4 cycles

Multicycle DP: Store Word (sw)

Step 1: Fetch instr // Store in IR // Compute PC + 4

Step 2: Decode instruction: opcode, rs, rt, offset fields

Data fetch: Apply rt to Register File => Base address

Data Read into A buffer register (Base) SignExt,Shift offset field into B buffer register

Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset

ALU output goes into ALUout register

Step 4: ALUout register contents applied as Memory Address

Assert: MemWrite [ALUout => RegFile]

CPI for Store = 4 cycles

Multicycle DP: Load Word (lw)

Step 1: Fetch instr // Store in IR // Compute PC + 4

Step 2: Decode instruction: opcode, rd, rt, offset fields

Data fetch: Apply rt to Register File => Base address

Data Read into A buffer register (Base) SignExt,Shift offset field into B buffer register

Step 3: ALU operation (ALUsrcB, ALUop) => Base + Offset

ALU output goes into ALUout register

Step 4: ALUout register contents applied as Memory Address

Assert: MemRead

Step 5: Memory Data Out routed to Register File write input

Register number from rd written to (Assert:

CPI for Load = 5 cycles

Multicycle DP: Cond Branch

Step 1: Fetch instr // Store in IR // Compute PC + 4

Step 2: Decode instruction: opcode, rs, rt, offset fields

Data fetch: Apply rs, rt to Register File

BTA calc: SignExt,Shift offset field into B buffer register

ALU compose PC, offset => BTA

Step 3: ALU operation (ALUsrcA, ALUsrcB, ALUop) = compare

ALU output present at Zero register causes Control

to select BTA or PC+4

CPI for Conditional Branch = 3 cycles

Multicycle DP: Jump

Step 1: Fetch instr // Store in IR // Compute PC + 4

Step 2: Decode instruction: opcode, address fields

JTA calc: SignExt,Shift offset field [Bits 27-0]

Concatenate with PC [Bits 31-28] => JTA

Step 3: PC replaced by the Jump Target Address (JTA)

CPI for Jump = 3 cycles

Conclusions

• MIPS ISA: Three instruction formats (R,I,J)

• One cycle per stage, Different stages per format

• One-Cycle Steps R-fmt lw sw beq j

1 Instruction Fetch

2 Instruction Decode / Data Fetch

3 ALU ops / R-format Execution

4 R-format Completion

5 Memory Access Completion

Challenge: More involved control design