Tiểu luận môn Giải thuật nâng cao chủ đề Virtual Memory

Tiểu luận môn Giải thuật nâng cao chủ đề Virtual Memory Run multiple processes, each with its own address space  main memory can’t contain all. Many processes use only a small part of space Small parts : main memory Other parts : disk Virtual memory : technique of sharing main memory among many processes. Main mem ~ cache for the disk

Virtual Memory

Nhóm 5

11070459 - Thái Tiểu Minh

11070460 - Nguyễn Kim Ngân

13070249 - Lê Minh Nam

13070250 - Trần Đức Nghĩa

A Introduction

Reasons for using virtual memory

1 Reason 1

Run multiple processes, each with its own address

space  main memory can’t contain all.

Many processes use only a small part of space

 Small parts : main memory

 Other parts : disk

Virtual memory : technique of sharing main

memory among many processes.

 Main mem ~ cache for the disk

4

1 Reason 2

A program is too large for main mem 

programmers have to make it fit (*)

Program is devided into pieces  mem/disk

 Only “active” code, data : main mem

Virtual memory :

 Relieves progammer’s job

 Automatically manages memory accesses

between main memory and disk (secondary storage)

1 Reason 3

Virtual memory :

 One process can’t interfere with another

• Because they operate in different address spaces

 User process cannot access privileged

Cache Virtual memory

2 Virtual Memory

8

2 Virtual Memory

Virtual memory = memory on disk

 Virtual memory : logical address (virtual address)

 Main mem : physical address

Contains blocks from main mem and disk

 Controlled by operation system

 Auto overlay

(+) Virtual continuous address space

(+) Size ~ disk size, speed ~ main mem speed

(+) Programmers don’t care about mem size  run

more larger processes.

3 Virtual Memory vs Cache

10

1 Main mem organization

Memory access :

 Cache miss time ~ 5-10 cache hit time

 Main memory miss time ~ 1000 mem hit time

Goals : reducing miss rate  Fully associative

 Higher associativity + larger block size

2.-3 Replacement & write policy

Replacement

 RLU (Least Recently Used) : why?

• Best choice?

Write policy

 Write back : why not write through?

• Benefit for mem access time?

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4 TLB

Memory

miss hit

data

hit miss

Disk Memory

OS Fault Handler

page fault/

protection violation

Page Table

data

virtual addr. physicaladdr.

Page hit

4 Speeding up Translation with a TLB

“Translation Lookaside Buffer” (TLB)

 Small hardware cache

 Maps virtual page numbers to physical page numbers

 Contains complete page table entries for small

number of pages

 Dirty : “1” = dirty data (write back)

 Ref : used to help calculate LRU on replacement

 Valid : Entry is valid

 Access rights : R(read permission), W(write permission)

Virtual Addr Physical Addr Dirty Ref Valid Access Rights

4 The Big Picture

virtual address virtual page number page offset

physical address

valid tag physical page number

valid tag data

1 Paging

Virtual memory = a sequence of fixed-size pages

 Page identified : page number (0N-1)

 N : number of pages in VM

 N*page size : VM size

 Logical address :

• Page offset ≤ Page size

Main mem = frames

 A frame = a page

Page number Page offset

1 A System with Paging Virtual Memory

2 Segmentation

Virtual memory = a set of segments

 Identify : segment number, size

 Logical address :

• Segment offset ≤ Segment size

Main mem = segments (+ holes)

24

Segment number Seg offset

Random FIFO LRU mem

Paging A page

hole First fit

Next fit Best fit Worst fit mem

Segmentation A seg

Paging vs Segmentation

+ Good physical unit of infoSimple mem management Good logical unit of infoSharing, protection

- ??? Hard to find holesNon-trivial replacement

External fragmentaion

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3 Paging segmentation

Virtual memory = a set of segments

 Segment i = ki * fixed-size page (k ϵ Z+ )

 Logical add :

 Segment table  Page table

Main mem = pages

Better than Paging, Segmentation

P number P.offset

S number

4.1 Looking a block - Paging

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Address Translation for Pages

Page table contains, for each page p

• frame number that corresponds to p

• other: perm s, valid bit, reference bit, modified bit

Logical address (p, i) to physical address

translation

• check if operation is permitted

• physical address = p.frame + i

4.1 Looking a block - Paging

Page Fault Valid = 0

Page Hit Valid = 1

p - Page number

f - Page frame number

d – Page Offset

d

4.1 Looking a block - Paging

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Page Fault (~ cache miss)

Find & copy page : disk  main mem (or nonexistent)

Update page table (valid bit, frame #)

CPU

Memory Page Table

After fault

(LRU – mem full)

4.2 Looking a block - Segmentation

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Address Translation for Segments

Segment table contains, for each segment s

• base, bound, permissions, (+ valid bit )

Logical to physical address translation

• check if operation is permitted

• check if i < s.bound

• physical address = s.base + i

4.2 Looking a block - Segmentation

s - Segment number

d – Segment Offset limit – ending address (bound) base – starting address

d

Hit Valid = 1

Fault Valid = 0

Disk

Virtual

Physical

base

4.2 Looking a block - Segmentation

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4.3 Looking a block - Paging Segmentation

4.3 Looking a block - Paged Segmentation

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1 Introduction

Process = a running program + states

 Single process : no need protection, sharing

 Multi : sharing CPU & mem = process switch

 need protection

Protection :

 Everything of a progress must fit in a region

 process-state protected from another process

 Mem protection & Access protection

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Fence Registers

Operating System v.1

User Program

0

n n+1

System v.2

User Program

0

m m+1

Address

m+1

0

Protection in Multiprogram

An address is valid  2 registers “base, bound”

 base ≤ address ≤ bound

 base + address ≤ bound : unsigned address

Operating System

User Program

A

User Program

B

0 n n+1

high

m m+1

n+1 m

B’s registers

base bound

m+1 high starting addr

ending addr

Mem protection example

Each process has its own page/segment table

OS changes tables by changing Base Register

Operating System

User Program

42

Disk

Page Fault Valid bit = 0

Page Hit Valid bit = 1

s - Segment number

d – Segment Offset limit – ending address (bound) base – starting address

d base

Register

Paged Segmentation

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Protection in Multiprogram

Base – bound register can be changed

 By OS process  to switch processes

 Not by user process  to protect users

 user/system mode bit  indicate a process

Mechanism : user ↔ system mode (supervisor)

 System call : save point of sc  system mode

Checking + Translation

 +read only, exe only, user/system bit

2 processes can have a page table entry that is

mapped to the same physical page

Operating System

User Program

A

User Program

Shared

PP 4 Yes Yes

PP 9 Yes No

VP 0:

VP 1:

Page Table

Access Protection

Readable – Writeable - Executable

 RW(!E) : Normal data pages

 R(!W)(!E) : Static shared data pages

 R(!W)E : Code pages

48

hit miss

Disk Memory

OS Fault Handler

page fault/

protection violation

Page Table

data

virtual addr. physicaladdr.

Page hit

Address Translation

Addressing

 14-bit virtual addresses (virtual mem size = 28 )

 Page size = 64 bytes = 26  Offset = 6bit

VO

PO P#

V#

(Virtual Page Number) (Virtual Page Offset)

TLB (Translation Look-aside Buffer)

 TLBIndex = 2bit (do 22 set)

 TLBTag = lg(virtual size/sets) = lg(28 / 2 2 ) = 6bit

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4-way Associative

VO V#

I TLBTag

Set Tag P# Valid Tag P# Valid Tag P# Valid Tag P# Valid

CO CIndex

Example 1 – TLB hit & Page hit

Example 1 – TLB hit & Page hit

Looking in TLB :

 TLB Index  check TLB Tag  check Valid bit

 TLB Index = 3  Tag 03 exists & Valid = 1

 TLB hit ( Page hit)  P# = 0D

56

Set Tag P# Valid Tag P# Valid Tag P# Valid Tag P# Valid

TLBI=3 TLBT=03

Example 1 – TLB hit & Page hit

CT=0D

Example 1 – TLB hit & Page hit

Looking in Cache

 Cache Index  check Cache Tag  check valid bit

 Index = 5  Tag 0D exists & valid = 1  Cache hit

 Offset = 0  take B0 : byte 36

58

CO=0 CI=5

Example 1 – TLB hit & Page hit

CPU  TLB : TLB Hit (Index,Tag), Page Hit  P# = 0D

CO=0 CI=5

Example 1 - TLB hit & Cache hit

OS Fault Handler

page fault/

protection violation

Page Table

data

virtual addr. physicaladdr.

Page hit

Example 2 – TLB miss & Page hit

Memory

miss hit

data

hit

miss

Disk Memory

OS Fault Handler

page fault/

protection violation

Page Table

data

virtual addr. physicaladdr.

Page hit

Example 2 – TLB miss & Page hit

62

V#=0A

TLBI=2 TLBT=02

CO=3 CI=3

Example 3 – TLB miss & Page fault

Memory

miss hit

data

hit

miss

Disk Memory

OS Fault Handler

page fault/

protection violation

Page Table

data

virtual addr. physicaladdr.

Page hit

Example 3 – TLB miss & Page fault

64

V#=01

TLBI=1 TLBT=00

CO CI

LOGO