accurate analog synthesis based on circuit matrix models

Computer Science & EngineeringAccurate Analog Synthesis Based On Circuit Matrix Models... All optimization based sizing methods arebased on the common thread of design space exploration

Computer Science & Engineering

Accurate Analog Synthesis Based On Circuit Matrix Models

Accurate Analog Synthesis With Circuit Matrix Models

A dissertation submitted to theGraduate School

at the University of Cincinnati

in partial fulfillment of therequirements for the degree of

DOCTOR OF PHILOSOPHY

in the Department ofElectrical and Computer Engineering and Computer Science

of the College of Engineering

2009by

Automated synthesis is imperative for the rapid design of analog circuits Knowledge based andoptimization based methods have emerged to provide solutions for analog synthesis, especially fordevice sizing Posing analog sizing as a constrained optimization problem facilitates the application

of many well developed algorithms for this purpose All optimization based sizing methods arebased on the common thread of design space exploration and performance evaluation Design spaceexploration is required for finding design solutions satisfying the given performance constraints.During exploration a performance evaluator is required to determine the quality of the examinedsolutions

The efficiency of the sizing procedure is completely dependant upon the speed of the mance evaluator Some of the recently proposed techniques construct models for performance pa-rameters in the circuits design space and use them for performance prediction Methods based onthis principle can be collectively called Performance Macromodeling methods Avoiding simulationgives the advantage of fast synthesis to these methods at the expense of moderate modeling errors.Performance macromodeling methods can rapidly explore the design space and offer sizing solu-tions in a reasonable time However, they are successful only for synthesizing those specificationswho models have been developed

perfor-In this dissertation we propose performance prediction using Circuit Matrix Models to estimatethe performance of analog circuits Using these models the entire a.c behavior of the circuit iscaptured With the use of matrix models, the limitation that a circuit can by synthesized for themodeled performance specifications is eliminated Any linear performance characteristic can becalculated from the models Analog circuits need to be designed with high accuracy With circuitmatrix models it is seen that performance prediction is precise and synthesized circuits are veryaccurate

We then develop techniques to expedite synthesis by making matrix model evaluation extremelyfast The first technique uses hashing for obtaining the desired speedup This technique takesadvantage of matrix elements being dependent on a subset of design variables Design sub-spacesare visited several times when the entire space is being explored in a synthesis run Hash tables savethe matrix element values computed in the visited subspace and reuse them when that subspace isvisited again This saves a large amount of recomputations and imparts speedup to the synthesisprocedure

The second technique has a nearest neighbor searching algorithm at its core It uses values atdesign points visited to incrementally compute values at neighboring design points A first orderTaylor series approximation is sufficient for such incremental computation and this makes per-formance estimation procedure extremely fast A balanced box decomposition tree data structuremakes detecting exact or approximate neighbors quite efficient The circuit design variables formthe dimensions of the search space The distance metric for neighbor computation is modified byconsidering sensitivity of matrix elements to the search space dimensions Using this method, veryfew computations are required during the synthesis process.

Layout parasitics are detrimental to the performance of analog circuits Considering their effectsearly in the design flow is essential for achieving designs with parasitic closure We have developedcircuit matrix models inclusive of parasitic effects The models use area and perimeter as predictorvariables and can be used to compute parasitic inclusive matrix element values for many geometries.Thus, the most suitable geometry for component modules is selected dynamically by the optimizer

as a part of synthesis Operational amplifiers and filter topologies have been synthesized as a part

I would like to thank Dr Ranga Vemuri for his guidance that helped shape this dissertation Hisadvice helped the research direction, explore several ideas, and refine experiments and publicationsdeveloped during the course of this work My committee members, Dr Wen-ben Jone, Dr HalCarter, Dr Carla Purdy and Dr Jintai Ding, offered helpful suggestions which have further im-proved this work and my sincere thanks to them This work was funded in part by the grant fromNational Science Foundation (CCF-0429717)which made this research work possible

DDEL has been a great place to work and I would like to thank Angan, Shubhankar, Bala,Vijay - my colleagues for the most part here, for allowing me to learn from their experience, theencouragement when the going was rough and the discussions that sometimes helped put things

in perspective Coffee breaks in the lab with Annie, Mike, Surya, Pritesh and others have givenmoments of respite which were valuable, especially on difficult days I would also like to thank Dr.Anuradha Agarwal for responding to my queries even after graduating from the lab

Cincinnati became a home away from home thanks to great support from my friends, the whole

of ’Cinci Friends’ group, Ketaki and many others These times spent enjoying and arguing, brating or just relaxing will be cherished forever I would also like to thank my colleagues fromthe Graduate School office who have been a great bunch and with whom I really enjoyed workingduring both my stints there

cele-I would never have been here but for my parents who always encouraged me to pursue highereducational goals and have been a constant source of encouragement My younger sister Asmita and

my extended family back home have been a great support system for me I would also like to thank

my mother-in-law, Mrs Anjali Salgaonkar for being encouraging about my educational aspirations.Nothing has been more important in the completion of this dissertation than the support of myhusband, Dr Vasant Salgaonkar We were both enrolled in doctoral programs at the same time, butthings did not seem too difficult due to his patience, help and support Vasant has been a constantsource of encouragement through the completion of this research work which had its ups and downsbut none that seemed overwhelming thanks to his support We made it !!

1.1 Overview of the synthesis process 2

1.2 Alternatives for analog circuit synthesis 4

1.3 Desirable Macromodel Characteristics 9

1.4 Research Approach and Overview 11

1.5 Thesis Outline 15

2 Circuit Matrix Models for Accurate Performance Estimation 17 2.1 Introduction to Circuit Matrix Models 17

2.2 Motivation 19

2.3 Modeling Methodology 20

2.3.1 Circuit Matrix Generation 22

2.3.2 Reducing number of models 22

2.3.3 Data Generation 24

2.3.4 Fitting Models for the Matrix Elements 24

2.4 Description of Test Circuits 25

2.5 Accuracy of the developed models 26

2.6 Estimation using Performance Macromodels 31

2.7 Synthesis Using Circuit Matrix Models 33

2.7.1 Synthesis with common performance specifications 33

2.7.2 Synthesis with non-standard specifications 34

2.7.3 Alternate forms of target specifications 36

2.8 Conclusion 36

3 Hash Classes for Efficient Synthesis 38 3.1 Review of Hashing Algorithms 39

3.1.1 R-B trees for implementing hash tables 40

3.2 The Concept of Hash Classes 41

3.3 Partial Solutions in SA based search 43

3.4 Proposed synthesis flow using hash tables 44

3.5 Hash Table Organization 45

3.6 Estimation of Speedup by Hashing 46

3.7 Integrating Hash Classes in the Synthesis Flow 47

3.8 Experiments to determine speedup with hash tables 48

3.8.1 Single Ended Opamp 48

3.8.2 High Gain Differential Amplifier 52

3.9 Synthesis Results 54

3.10 Conclusion 55

4 Sensitivity Based Near Neighbor Search 57 4.1 Limitation of the hashing approach 57

4.2 Calculation of matrix values by incremental updates 58

4.3 Algorithms for Near(est) Neighbor Search 59

4.4 The Optimal Nearest Neighbor Search Algorithm 61

4.4.1 Distance Measures 61

4.5 Multi-dimensional Near Neighbor Search for Analog Synthesis 62

4.6 Method for computing allowable perturbations 63

4.7 Algorithm for synthesis with sensitivity based near neighbor searches 64

4.8 Experiments to determine synthesis speedup 65

4.9 Conclusion 68

5 Layout-aware Synthesis with Module Geometry Selection 69 5.1 Need for Layout-Aware Circuit Models 70

5.2 Parasitic Aware Matrix Models 71

5.2.1 Schematic Matrix Models 72

5.2.2 Device Parasitic Models 73

5.2.3 Models for Non-Device Parasitics 75

5.3 Synthesis with Dynamic Geometry Selection 77

5.4 Proposed Layout-Aware Synthesis Flow 78

5.5 Experiments and Results 79

5.5.1 Operational Amplifier 80

5.5.2 Fourth Order Filter 82

5.5.3 Dynamic Geometry Selection 82

5.6 Conclusion 84

6 Pareto-optimal Circuit Performance Curves 85 6.1 Related work for Pareto-optimal performance curve generation 86

6.2 Layout-aware Pareto-optimal curves using circuit matrix models 88

6.3 Extracting the Pareto-Optimal Performance Curves 91

6.3.1 Problem Formulation 92

6.3.2 Front Generation Methods 93

6.3.3 Improving the Efficiency of Pareto Curve Generation 95

6.3.4 Algorithm 96

6.3.5 Sizing procedure using a generated Pareto Front 97

6.4 Experiments and Results 97

6.5 Conclusion 101

7 Additional applications of the efficient SA algorithm 104 7.1 SA description 105

7.2 Problem characteristics suitable for using the new SA algorithm 105

7.3 Applications 106

7.3.1 Recursive determinant calculation 106

7.3.2 Circuit performance variability calculation 109

7.4 Conclusion 111

8 Conclusions and Future Work 112 8.1 Summary of Research Contributions 112

8.2 Limitations 115

8.3 Future Work 116

8.3.1 Combined circuit matrix models and symbolic performance models for syn-thesis 116

8.3.2 Reduced circuit matrices for fast performance evaluation 117

Bibliography 120 A Simulated Annealing Library for Circuit Synthesis 129 A.1 Generic SA optimizer description 129

A.2 Optimization results achieved through the SA library 130

A.2.1 Holder table Function 130

A.2.2 Cross in tray function 131

A.2.3 Crown cross function 131

A.2.4 Bukin function 132

A.2.5 Bird function 133

A.2.6 Egg holder function 133

A.2.7 Giunta function 134

A.2.8 Styblinski-Tang function 134

A.2.9 Chichinadze function 135

A.2.10 McCormick function 136

A.2.11 Zettle function 136

A.2.12 Levy function 137

A.2.13 Three hump camel back function 138

B Benchmark circuits used for analog synthesis 139 B.1 Operational Transconductance Amplifier 139

B.2 Two stage Operational Amplifier 141

B.3 High Gain Differential Amplifier 142

B.4 Single Ended Operational Amplifier 143

B.5 Fourth Order Sallen Key Low Pass Filter 144

B.6 Second Order Band Pass Filter 145

List of Figures

1.1 General description in an analog top-down design flow 2

1.2 Bottom-up analog flow considering trade-offs 3

1.3 Optimization based analog sizing 6

1.4 Circuit synthesis alternatives 10

1.5 Summary of the proposed approach 13

2.1 (a) Performance Modeling Approach (b) Matrix Modeling Approach 19

2.2 OTA circuit schematic 20

2.3 Phase Margin vs Device Width of OTA 21

2.4 Matrix Element vs Device Width of OTA 21

2.5 TSO schematic 27

2.6 DA schematic [1] 28

2.7 Actual vs Modeled Frequency Response of the OTA 29

2.8 Actual vs Modeled Frequency Response of the TSO 30

2.9 Actual vs Modeled Frequency Response of Differential Amplifier 30

2.10 (i) Amplifier used in bpf (ii) Active band pass filter schematic 35

2.11 Synthesizing filter from Frequency Response 36

3.1 A Simple Two Stage Op-Amp 42

3.2 Proposed Approach: Fast SA based Circuit Synthesis with Hashing 44

3.3 Table for a Hash Class 46

3.4 The Single Ended Operational Amplifier (SEO) 50

3.5 SEO Expt A: Speedup by hashing 51

3.6 SEO Expt B: Speedup by Reinforced Hashing 52

3.7 SEO Expt C: Average and Best Speedup by Reinforced Hashing 53

3.8 DA Expt A: Speedup by hashing 54

3.9 DA Expt B: Speedup by Reinforced Hashing 55

3.10 DA Expt C: Average and Best case speedup by Reinforced Hashing 56

4.1 Neighbor detection using variable sensitivities 62

4.2 Convergence time for synthesized circuits 67

5.1 Effect of geometry on device parasitics (i) ad=48p pd=52.8u as=48p ps=52.8u (ii) ad=24p pd=45.6u as=36p ps=68.4u 74

5.2 Parasitic Estimation Error Ignoring Geometry 74

5.3 Proposed Flow - Synthesis using Parasitic Aware Circuit Matrix Models 79

5.4 Performance Prediction Accuracy using Proposed Models in SEO Synthesis 82

5.5 Performance Prediction Accuracy using Proposed Models in BSKF Synthesis 83

6.1 Overview of the Proposed Approach 88

6.2 An Operational Amplifier Circuit (SEO) 90

6.3 Effect of layout parasitics on Pareto-optimal performances 90

6.4 Pareto-Optimal performance sets 92

6.5 Three MOSA algorithms 93

6.6 Pareto front generated by the three MOSA methods 94

6.7 Reduction in Hash Table Misses for MOSA run on SEO 96

6.8 Accuracy comparison - Model v/s Simulation based Front 98

6.9 SEO: (i) PM (deg) vs UGF (KHz) (ii) BW (KHz) vs UGF (KHz) 99

6.10 Differential Amplifier Schematic 100

6.11 DA: (i) BW (kHz) vs PM (deg) (ii) UGF (KHz) vs BW (KHz) 101

6.12 Bandpass Filter Schematic 101

6.13 BPF:(i) Gain (dB) vs BW (Hz) (ii) Gain (dB) vs Q 102

8.1 Performance estimation from a PRIMA reduced MNA matrix 118

A.1 Holder Table Function 130

A.2 Cross in Tray Function 131

A.3 Crown Function 132

A.4 Bukin 6 Function 132

A.5 Bird Function 133

A.6 Giunta Function 134

A.7 Styblinski Tang Function 135

A.8 Chichinadze Function 135

A.9 McCormick Function 136

A.10 Zettle Function 137

A.11 Levy Function 137

A.12 Three hump camel Function 138

B.1 Operational Transconductance Amplifier (OTA) 140

B.2 Two stage Operational Amplifier (TSO) 141

B.3 High Gain Differential Amplifier (DA) 142

B.4 Single Ended Operational Amplifier (SEO) 143

B.5 Sallen Key Low Pass Filter (LPF) 144

B.6 Second Order Band Pass Filter (BPF) 145

List of Tables

2.1 Entropy and Local Differential Variation of OTA 22

2.2 Reduction of Matrix Elements 23

2.3 Modeling Accuracy for OTA 26

2.4 Design variable ranges for Benchmarks 27

2.5 Worst Case Validation Error 28

2.6 Performance Estimation Accuracy with Proposed Approach 31

2.7 Estimation Accuracy by Direct Performance Modeling 32

2.8 Modeling and Estimation Time 32

2.9 Differential Amplifier Synthesis with Partial Model Evaluation 34

2.10 Synthesis results for the band pass filter 35

3.1 Mapping between Matrix Elements and Design Variables 43

3.2 Hash Class Details for Benchmark Circuits 50

3.3 Analog Circuit Synthesis With Matrix Models 56

4.1 Performance Estimation Accuracy for Allowable Variable Perturbation 64

4.2 Speedup for Benchmark Circuits 65

4.3 Results for Analog Circuit Synthesis using Proposed Method 68

5.1 Effect of Parasitics and Module Geometry on Performance for a Single Ended Op-amp 71 5.2 Accuracy of Device Parasitic Models for Various Layout Geometries 76

5.3 Device Parasitic Modeling Error 77

5.4 Synthesis Result for SEO with Layout Parasitics 81

5.5 Synthesis Result for BSKF with Layout Parasitics 83

5.6 Results for Dynamic Geometry Selection During Synthesis 84

6.1 Validating Model Accuracy 91

6.2 Comparison of three MOSA algorithms 95

6.3 Speedup using proposed method (compared to simulation) 98

6.4 Circuit sizing from Pareto curve (SEO) 102

7.1 Optimizing matrix determinant through a Hashed SA algorithm 109

7.2 Performace variation (UGF) due to perturbations in the nominal design variable value111 B.1 BM1: OTA details 140

B.2 BM2 : TSO details 141

B.3 BM3 : DA details 142

B.4 BM4 : SEO details 143

B.5 BM5 : LPF details 144

B.6 BM6 : BPF details 145

Chapter 1

Introduction

Integrating digital and analog components on a single chip has ushered in a new era towards thedesign of innovative consumer applications We see increasingly complex mixed signal designs in-corporating high performance analog and RF blocks especially in telecom and multimedia Analogcircuitry is unavoidable for interfacing and conditioning signals from the real world with digital andDSP blocks Since the success of competing products is strongly tied to their time-to-market, fastdesign and manufacture is of critical importance Arguably, the design on analog systems is set tobecome even more challenging in the future [2]

Design automation and IP reuse have always formed the cornerstones of the fast growth of the ICindustry The market for digital design tools is fairly mature and creating digital designs comprising

of million gates is not often considered a challenge As opposed to that, analog circuits thoughonly a fraction of the size of their digital counterparts have not lent themselves easily to automation.Analog circuits are many a times handcrafted and designer experience and expertise play a majorrole in achieving a good design Unfortunately, expert analog designers are always in short supply.Moreover, a manual design process partially contributes towards analog and mixed-signal designbeing a bottleneck in the design flow

The need for good automation tools for the design of analog circuits and systems is undeniable.EDA tools are required for various aspects in the design flow Of particular importance are the areas

of analog circuit synthesis, behavioral model development, model order reduction, layout synthesisand system level verification The focus of our work is the development of robust tools for thecircuit synthesis problem

1.1 Overview of the synthesis process

Circuit synthesis is a process where given a set of high level specifications, a detailed designmeeting the stated requirements is generated An analog system may be designed flat or hierar-chically using either a top-down flow or a bottom-up one [3, 4] offer a good review of varioussynthesis methods This section presents an overview of the circuit synthesis flows available foranalog design

In a top-down flow, starting from the system level specifications, an architecture is chosen prising of hierarchical blocks optimized at the system level Propagating constraints from the systemlevel hierarchically downwards to the block level is a vital task and forms an independent area ofstudy Once the constraints are propagated downwards upto the analog cell level, an architecture ischosen for each cell This is known as topology selection

com-Cell Requirements

Technology Parameters

Finished Cell Design

Topology Selection

Circuit Sizing

Layout Generation

Extraction

Simulation and Verfication

System Architecture Design

Overall System Specs

Figure 1.1: General description in an analog top-down design flow

At this stage, each cell or block is designed to meet the derived cell level specifications Thus for

a given circuit topology, we need to size the individual components in order to meet the tions This is known as the circuit sizing problem Sizing examines the circuit at the transistor leveland derives a satisfactory set of component values meeting the objective performance This can be

specifica-an overwhelmingly time consuming process In the event a cell design is infeasible or is unable tomeet the specifications, the hierarchy needs to be climbed up again to select a different architecture.Most analog circuits that are designed in a top-down fashion use steps shown in fig 1.1.

A top-down flow does not easily yield to examining design tradeoffs which is very important inany design process A bottom-up procedure is more beneficial in this respect In a bottom up flow,each cell level block has its tradeoffs described in the form of a pareto optimal front These tradeoffscan be propogated hierarchically upwards to the system level and the designer can consider whatsystem-level tradeoffs are available by interchanging several lower-level blocks Fig 1.2 shows theperformance tradeoff propagation

System

Figure 1.2: Bottom-up analog flow considering trade-offsAfter the entire analog system has been designed by following either an hierarchical or flatdesign methodology, the verification step follows Thus system level design, cell level synthesis,verification form some of the important research problems in the field of analog synthesis In thisdissertation work we are interested in the developing methods at the analog cell level The nextsection presents several alternative methodologies developed by researchers in the field of analogsynthesis and surveys some notable work in this domain

1.2 Alternatives for analog circuit synthesis

Analog cell level synthesizers perform the task of obtaining a valid design solution at the tor level which satisfies the assigned specifications for a given process technology Analog synthesistools are designed in two flavors,

transis-Variable topology and sizing: These tools address two areas, topology selection and circuit

siz-ing, simultaneously The only input provided is the target specifications the circuit should achieve.Both the circuit assembly from device level components (topology) and device dimensions (size)that satisfy the requirements are obtained at the output

Some of the important contributions in topology selection and sizing are now reviewed Maulik

et al [5] proposed the first simultaneous topology selection and sizing algorithm They formulate

synthesis as a Mixed-Integer Non-Linear Programming (MINLP) problem Binary variables areused to select the topology and integer variables for the device dimensions Branch and boundmethod was used to solve the MINLP and synthesize the final circuit The technique found gooddesigns however obtaining the underlying performance equations in terms of topology and sizingvariables is an extremely arduous task SEAS [6] and DARWIN [7] also tackle the topology andsizing problem using evolutionary techniques In the former many intermediate topologies are sizedresulting in a wasted effort while the later overcomes this problem by using a fast transfer functionestimator MOJITO [8] is another evolutionary technique that performs a multi-topology and multi-objective sizing in an effort to build a library of analog components

Sizing for a fixed topology: In this set of synthesis methods, the focus is on the sizing problem.

Topology selection and circuit sizing are considered separately The topology is chosen either based

on heuristics or may be application based The circuit synthesis problem is then defined as, given

a circuit topology find device dimensions such that the target specifications are satisfied Thisproblem, known as the circuit sizing problem, itself is a hard problem for which a lot of researchefforts have been invested since the past decade With sizing itself being a hard task, the variabletopology and sizing problem severely compounds in complexity so far limiting research efforts inthat direction

Several interesting research directions have been under investigation for the circuit sizing lem Most of the circuit sizing techniques fall into two broad categories:

prob-• Knowledge based synthesis

• Optimization based synthesis

Knowledge based synthesis: These methods largely rely on the domain-knowledge of

experi-enced analog designers in the development on synthesis tools The underlying idea is to capture andemulate the designers knowledge in the form of rules and thus automate the sizing process Knowl-edge based methods were notable contributors in the early automated synthesis tools OASYS [9]

is a hierarchical circuit synthesis framework Designer knowledge is used to consider tradeoffs andexplore the space of designable circuits In OPASYN [10], topology selection is heuristic followed

by sizing employing designer derived analytical equations IDAC [11] provides a framework tointegrate analog expertise in a software paradigm that stores knowledge of circuit schematic, of thecircuit class (e.g cascode circuits) and function (e.g amplifier stabilization), while BLADES [12]uses an set of rules to organize the circuit equations

The dependence on designer expertise limit such methods from being easily extensible Forexample, in order to design a new circuit or integrate a new component a large number of analyticequations have to be manually derived This makes such tools cumbersome for practical usage Thedesire to develop tools that are not overly reliant on the designer has produced the second class ofsynthesis methods which are based on optimization

Optimization based synthesis: These methods use robust optimization algorithms to develop

parametric optimization tools for analog synthesis No a-priory knowledge is necessary for this

category of tools making them adaptable and attractive to any class of circuits The synthesis flowfor optimization based methods is described in fig 1.3

The circuit topology, process parameters and design requirements are provided as an input sign variables which include widths and lengths of transistors and bias voltage or current are iden-tified for the circuit The goal of the synthesis tool is to find numerical values for design variables(sizes) such that the design requirements are satisfied

De-The circuit synthesis problem is modeled as a constrained optimization problem De-The goal is

to minimize the circuit area while satisfying some numerical constraints on characteristics such asgain, bandwidth among others Thus, the synthesis requirement is formulated as a cost functiongiven by:

Topology, Design Variables

Specs Met ?

Y N

Here f i (x) describes the objectives to be satisfied Since the objectives may conflict with each

other, the set of weights w iis used to determine their relative importance The synthesized circuit is

also required to meet the constraints represented by g (x) The constrained optimization problem is

often converted to that of unconstrained optimization such as

It is typical to visit several thousand unsatisfactory solutions before a candidate that fulfills thedesign requirements can be found Observing the optimization based synthesis flow of fig 1.3suggests that the design evaluator is a critical component in this method The evaluator verifiesthe quality of each candidate solution and thus is needed at each iteration of the flow Optimiza-

tion based synthesis methods can be classified based on the class of evaluators they use Designevaluators may belong to one of the following classes:

• Numerical simulation based

• Partial simulation techniques

• Numerical model based

Numerical simulation based: Simulation based methods rely on a numerical simulator, usually

the ubiquitous SPICE program, to evaluate design solutions Using spice for evaluation guaranteesthat the design solution obtained is highly accurate Additionally, since numerical analysis is usedfor circuit evaluation manual derivation of performance equations are not required Out of thevarious methods available for synthesis, the simulation methods achieves the best accuracy withlimited set up time

DELIGHT.SPICE [13], one of the earliest optimization based methods, has an interactive timization algorithm (DELIGHT) combined with a numerical simulator (SPICE) Designer inter-action is required making this approach somewhat knowledge based A good initial solution isprovided to the synthesis tool The tool also comprises of a library of good optimization functions.The starting solution is fine tuned to obtain a satisfactory design SPICE is used to numerically

op-analyze the design while it is being locally optimized Medeiro et al [14], relax the requirement of

a good starting solution and synthesize circuits starting from an arbitrary point in the design spacelending greater flexibility to the approach

MAELSTROM [15] improves the numerical simulator based synthesis by adding some new tures targeted to make the environment user friendly and efficient It offers the designer a choice ofvarious simulators by encapsulating them but hiding their implementation details A robust com-bined genetic/annealing algorithm helps better design space exploration A network of parallelworkstations makes the tool more efficient ANACONDA [16] and ASF [17] have some similarfeatures but uses improved optimizing algorithms such as stochastic pattern search and parallel re-combinative simulated annealing respectively

fea-Simulation based methods have the advantage of a SPICE level accuracy of the results However,using a simulator at each iteration of the loop makes the synthesis procedure very time consuming.With optimization based methods, a large part of the design space has to be explored in order to find

a good design solution Using a slow performance evaluator results in requiring hours or even days

to find a good solution limiting the efficacy of simulator based synthesis

Partial simulation based: This set of synthesis methods comprises those that attempt to

over-come the speed limitation of simulation based synthesis Simulators are still used but in a restrictedmanner These include symbolic simulators and simulation-lite procedures Symbolic simulatorssuch as ISSAC [18] are an improvement over knowledge based equation driven procedures Inthose the equations that determine the circuit performance are hand derived This makes it difficult

to adapt them to new topologies and circuits Symbolic simulators on the other hand automaticallyderive performance equations parametric in circuit variables Operating point analysis is still re-quired however all modes of simulation are not required OPTIMAN [19] combines a symbolicsimulator with an optimizer to automate the synthesis process Symbolic analysis has also beenused in [20, 21, 22, 23, 24, 25, 26, 27]

Symbolic simulators are useful for viewing the circuit transfer function as symbolic expressions.The effect of any element on the transfer function can be judged However, most of the times thesymbolic terms are quite complex which makes interpreting them difficult Moreover, the size ofthe symbolic expression grows exponentially with circuit size Thus symbolic expressions have

to be limited to relatively smaller circuits or some sort of approximation techniques have to beincorporated

Another synthesis procedure that uses a partial simulation based approach is ASTRX/OBLX [28].Here a simplified numerical simulator (AWE) is used for analyzing the circuits The asymptoticwaveform estimator, AWE, projects the circuit to a reduced subspace by matching only the first2q-1 moments The circuit response is approximated which enables a speedy but less accuratesimulation

Numerical model based: The need for faster circuit evaluators cannot be undermined in the

design of efficient synthesis methods Faster evaluators accelerate design exploration making theoptimization based procedures tractable Model based methods are developed on the premise of pro-viding a fast circuit analysis environment while compromising accuracy as little as possible Modelsgenerated using circuit simulation data are used to predict the circuit quality during optimization.The need for numerical simulation is moved out of the synthesis loop which lends speedup to modelbased techniques Each differs in both accuracy and complexity depending on the fitting algorithmsused to generate the model Some of the notable published techniques are reviewed here

Wolfe et al [29] as well as Doboli et al [30] use Neural Networks for modeling the performance

parameters of the circuits A Neural networks is constructed for each performance parameter and it

is extensively trained till it shows a good prediction accuracy in the design space

Support Vector Machines (SVMs) have been incorporated as a classification mechanism whenmodeling large design spaces SVMs developed in the domain of machine learning are used to clas-

sify points based on whether or not they satisfy a complex and unknown property Ding et al [31]

used SVMs to predict whether a design point belongs to the feasible design space thus simplifying

the model generation SVMs are also used by Bernardinis et al [32] along with randomized test

procedures to limit the number of false positives (infeasible points falsely classified as feasible) and

by Kiely et al [33].

Han et al [34] used multivariate adaptive regression splines in the construction of the

macro-model Here, the entire design space is not modeled at once Instead a combination of simulationand modeling is used for performance prediction When a new candidate is generated an adaptivesampling scheme is used to selectively update the response surface model This makes the model

generation distributed over the synthesis process and reduces the initial setup time Wolfe et al.

[35] also proposed the use of splines using an adaptive sampling grid Their modeling is completedbefore starting the synthesis Boosted regressors [36], posynomials [37], krigging are some othermodeling methods that researchers have investigated

In [38], McConaghy et al have compared and contrasted a number of synthesis methods that

use numerical model generation It is observed that constructing a good model for performanceparameters is a challenging task due to their non-linear nature With increasing complexity of themodeling methods, the macromodel generation time increases Although some methods may givebetter results than others, typically all macromodeling methods suffer from inaccuracies due to theirlimitations in modeling a complex and non linear performance parameter space

A number of techniques are available for the synthesis of analog circuits Due to limitations ofknowledge based techniques, optimization based procedures have gained preference for automaticsynthesis of analog circuits In the presence of multiple alternatives in implementation, the questionarises as to what makes a good optimization based technique? Some of the desirable properties of

Knowledge Based Optimization based

Full Simulation Simulation-Lite Symbolic Numerical

Macromodels

Figure 1.4: Circuit synthesis alternatives

such a technique would be:

1 accuracy of prediction

2 speed

3 flexibility of specifying requirements

4 short set up time

Simulation based techniques are accurate, can synthesize for any performance that can be culated via a spice analysis and only need the circuit netlist and spice models as input Thus, theyreadily satisfy requirements 1,3 and 4 given above However, due to the excessive time requirement,they do not do well of the requirement of speed

cal-Symbolic methods also display a good performance with respect to accuracy and flexibility.Their use of a numerical simulator to obtain certain parameter values compromises the speed of themethod Moreover, since the symbolic expressions explode for bigger circuits, the set up time may

be large or even fail in some cases due to memory issues

Since numerical model based methods eliminate the simulator from the synthesis loop, they tend

to be fast Accuracy is greatly dependent on the actual modeling technique used Most publishedmodeling techniques give satisfactory results in parts of the design space Like accuracy, set up time

is also a property of the model generation mechanism Adaptive, dynamic modeling techniques tend

to have a higher set up time Unfortunately, most of the available numerical (performance) modelingmethods fare poorly in terms of synthesis specification flexibility In performance macromodelingmethods, the design space is sampled at numerous points and values of certain performance specifi-cations are gathered at these points A curve fitting mechanism is then used to generate a model foreach performance parameter These models called performance macromodels estimate the circuitperformance during synthesis Accuracy of performance prediction depends on the appropriateness

of the fitting method in modeling the underlying data points

However, the inherent drawback of this class of methods is that synthesis specifications arelimited to what performance parameters have been modeled This implies that the entire set of spec-ifications for which this topology can ever be sized have to be known at the time of model generationitself If some parameter was not modeled, it can never be a part of the design specification This is

an important restriction of the performance modeling methods

Circuit synthesis and sizing is one of the most active research areas in the analog CAD domain

A plethora of methods have been under investigation by researchers in the short span of the pastdecade The essence of a majority of these is a speed-accuracy tradeoff Accuracy is an unyieldingrequirement for many high performance analog circuits The aim of this research work is the de-velopment of a synthesis technique for analog circuits that achieves accurate results in a reasonabletimespan

Recent synthesis techniques treat sizing as an optimization problem in a stochastic search space.Their goal is to design an optimally sized circuit that meets the given performance specificationswhile satisfying constraints They do so by constructing models of the circuit performance param-eters Unfortunately, as witnessed by many of these methods, performance parameters make up acomplex and non-linear search space which is generally difficult to model Although many meth-ods are fast enough to synthesize circuits in a matter of hours, not all can claim similar successfor the accuracy of their results [38] There is some evidence to suggest that other circuit charac-teristics such as frequency points, first order expressions of poles and zeros may be modeled moreaccurately [39, 40]

Initially we explored a synthesis technique in which we created models for elements of analogcell circuit matrices Analog cells are composed of few tens of devices which eases the matrixformulation task Symmetry and device matching are important properties that characterize goodanalog designs To make model generation and evaluation faster we utilize circuit matching andreduce the number of unique matrix elements It is observed that numerically matrix elementsare less non-linear than their performance parameter counterparts Thus curve fitting gives betteraccuracy while predicting matrix values in the circuit’s design space On a number of benchmarkstested, the mean prediction error was about 1% or less.

The other advantage of circuit matrix models is that the specifications with which the circuit

is synthesized are not limited to the parameters that were modeled The circuit matrix model iscapable of generating the entire frequency response enabling the calculation of any linear parameter

in the circuits design space Instead of the specifying design requirements in terms of performanceparameters, they can be expressed in alternative forms such as frequency plots, pole-zero valueswithout hindering the synthesis algorithm

The faster the synthesis method, greater is the design space that can be explored in a giventime This prompts us to develop techniques that can speed up synthesis and achieve good design

is reduced time The first method we develop uses hash tables to garner speedup A matrix element

is a function of a subset of design variables Thus the response model for each matrix elementcan be computed using this design subspace During design space exploration by the optimizer,lower dimensional subspaces are revisited multiple times The matrix element values computed atdesign points visited during synthesis are stored in hash tables Grouping elements into hash classesrequires construction of few hash tables, making the technique very efficient The hash table sizedepends on the subspace dimension

Using hash tables to store circuit matrix element values, helps in reducing synthesis time by5x on average With hashing we are able to utilize previously computed element values only forexact previously visited points in the design space We can improve the speedup even further, if wecan compute values of matrix elements from adjacent points where the element value is available.This paves the way for our second technique that uses sensitivity based nearest neighbor searches

to improve synthesis performance

Here the matrix element value is numerically computed from the value at a neighboring pointusing a first order approximation The region of the design space around a given point where such

Generate System Matrix Models

Store Model Regression Parameters

Regression Parameters for Model Evaluation

Optimization Engine (SA)

Propose new Sizes {S}

Formulate H partial solutions {S 1 ,…, S H } from {S}

Locate nearest neighbor for partial solution {S 1 ,…, S H }

No

Evaluate Model & get Value

Compute value increment ally

Neighbor Found within acceptable limits?

Solve Matrix and Obtain Performance

Goals Met ?

Yes

FINAL SIZES

No

Key:

H: Number of Hash Classes

SA: Simulated Annealing

2

10

3

Figure 1.5: Summary of the proposed approach

an approximation holds is determined experimentally An optimal approximate nearest neighbordetection algorithm is used to locate adjacent design points visited earlier during design space ex-ploration within an acceptable radius The chebyshev norm is used for calculating the distance Thedistance is also weighed by sensitivity of the matrix element to subspace dimension This methodallows calculating matrix element value using very few computations while keeping the results veryaccurate Synthesis speedup further improves by about 9x

After laying out the designed circuit in silicon, parasitic effects come into play adversely fecting the performance of the designed circuit The circuit may no longer be able to achieve theperformance that it was designed for Iterations between design and silicon are very expensive andshould be reduced as much as possible Incorporating layout effects in the matrix value predictionmakes the synthesis models layout-aware We use procedural layout generators since they makeconstructing layouts very fast Due to the regular structure of a PLG layout, estimating parasitics ispossible

af-A summary of the entire synthesis flow developed is presented in fig 1.5 Important steps in thesynthesis process are briefly reviewed here:

In addition to synthesizing an instance of the topology for meeting a given set of design tives, it is also important to generate the boundaries of performance that any given topology canachieve This is implemented by a non-dominated performance measuring algorithm using the con-cepts of Pareto optimality The single objective SA algorithm is modified into a multi-objectiveoptimization algorithm and entire limit of performance that a topology can achieve within a prede-fined design variable range is extracted.

objec-1 In this first step we generate matrix models of a given circuit topology A symbolic matrix isdeveloped first and then matrix element values are sampled through the design space Multi-variate regression is used for building matrix models

2 A separate matrix model for the transistor-level (schematic) elements and layout-level asitic) elements helps in preventing abstraction of the layout effects into performance data.Such a separation enables consideration of several module geometries during the synthesisprocess

(par-3 Optimization goals have to be specified for a given circuit The goals may be in the form ofperformance specifications, frequency response, poles and zeros etc Initially we start with arandom seed which does not satisfy goals in most cases

4 We follow an optimization based approach to determine a valid sizing solution Optimizingalgorithms such as Simulated Annealing, Genetic Algorithms, Geometric Programming havebeen used for this purpose We have chosen an SA based optimizer The SA optimizer per-forms two important functions, moves and solution acceptance A move is the SA’s means ofproducing a new solution from an existing one whereas solution acceptance is the mechanism

by which an SA is able to move toward a global optimum

5 Once a new candidate solution is proposed by the optimizer, that solution is dissected to formpartial solutions for individual hash classes Each hash class has its own hash table and abalanced box decomposition tree which are built based on the matrix element values that areavailable from model evaluation

6 A balanced box decomposition (BBD) tree is a data structure that is useful for efficiently cating neighbors in a multi-dimensional search space Each BBD tree has dimension equal

lo-to number of design variables in a hash class A BBD tree is build at the beginning of the

synthesis run and for long running synthesis experiments it can be reconstructed after a determined number of iterations The BBD tree is queried to check if matrix element values

pre-at a neighboring design point The neighbor needs to be within a certain radius of the querypoint for it to be useful

7 If the neighbor detected is within an acceptable tolerance radius from the current partial didate query point, then the matrix element value at the query point can be simply calculated

can-by a first order approximation The approximation holds since it is computed using a veryclose neighboring point

8 If no neighbor was found in the close proximity of the query point, a fast first approximationfor matrix element computation is not possible The matrix element value now needs to becalculated by evaluating the regression model

9 We always store all values of matrix elements that have been computed in order to avoid theirevaluation in a future synthesis step The matrix element values are stored in the hash tablecorresponding to its hash class A BBD tree is build based on the updated hash tables thusthey contribute to neighbor detection as well

10 The numerical system matrix whose elements may have been computed incrementally fromneighboring points or from model evaluation is then solved to compute its performance Per-formance values for the specified goals are obtained in this step If the performance valuesfor the current sizes are seen to meet the specifications then a valid sizing solution has beenobtained The circuit may be laid out with the given transistor sizes and is expected to meetthe required specifications

This dissertation is organized as follows In Chapter 2, we introduce the motivation behind ourproposed approach where models of the circuit matrix are used in predicting the circuit perfor-mance We present experimental results that indicate the accuracy of modeling matrix elements.The fitting algorithm for model generation is described along with modeling and validation results.Performance prediction results compared to a direct macromodeling method supports the accuracy

of our proposed method Synthesis results using the proposed approach to synthesize an amplifier

and filter topology are discussed.

Chapter 3 proposes the idea of using hash tables in conjunction with the matrix models oped in the previous chapter to expedite the synthesis procedure We present the concepts of hashclasses and partial solutions that are integral towards the successful and efficient implementation ofhashing as a technique that provides synthesis speedup Several experiments performed on practicaloperational amplifier circuits evidence the usefulness of this technique

devel-In Chapter 4 we identify some limitations with the use of hash tables which confines the able speedup and seek to address them Using data gathered from neighbors of a design point topredict its value makes the matrix model evaluation very fast The computations required during asynthesis run are drastically reduced by use of this method Design variables sensitivity used forneighbor search detects the most reliable neighbor for a given point Using techniques proposed inChapter 3 and 4 improve synthesis time without any considerable loss in accuracy

achiev-A synthesis methodology should not only have the desired accuracy at transistor level but also

be robust to the effects of layout parasitics This is extremely essential in order to reduce the silicon iterations Chapter 5 discusses the development of matrix models that are parasitic inclusive.Parasitics are extracted and sampled through layouts generated using PLGs Separating transistorlevel and layout level models allows parasitic prediction with varying layout geometries Parasiticinclusive performances are predicted and verified for some test circuits

design-Synthesizing the entire boundary of achievable circuit performance is discussed in Chapter 6.Here we introduce the concept of non-domination and Pareto optimality in analyzing tradeoffs be-tween two or more circuir instances Layout-aware circuit matrix models are used in prediction

of Pareto optimal performances The algorithms generate a tradeoff curve with uniformly spreadperformance points which can also be used to rapidly design a circuit Chapter 7 discusses someapplication of hashing and nearest neighbor detection in problems such as recursive matrix deter-minant computation and performance variation estimation due to variations in the nominal designpoint values Chapter 8 concludes the dissertation and presents some directions for future workrelated to this topic

Any linear (or linearized) circuit can be represented mathematically using the Modified NodalAnalysis (MNA) formulation [41, 42] Using MNA, the components of a circuit and their intercon-nections are expressed in a matrix form Such a matrix is called the system matrix or the circuitmatrix The circuit matrix is represented as follows:

(G + sC)x = B;

y = L T x

here

G: conductance submatrix

transconductance (gm), output conductance (gds), capacitance (cgs , cgd, cgb) etc., whereas for other

circuit elements stamps are in terms of the component values The small signal values of mosfetsare obtained by linearizing the circuit around the operating point

The circuit matrix is solved at various frequency points to obtain the frequency response of thecircuit Performance parameters such as the low frequency gain, Unity gain frequency (UGF), GainMargin (GM), Phase Margin (PM) are calculated from the frequency response In simulation basedsynthesis, the spice engine generates and solves the circuit matrix Macromodeling approachesuse fast evaluating models and eliminate the use of spice As shown in fig 2.1 macromodeling is

possible at two places in the synthesis flow:

1 Modeling the performance parameters

2 Modeling the circuit matrix

Most of the existing macromodeling techniques use the first approach i.e they model the formance parameters directly Such methods greatly concentrate on the performance estimation

per-speed, but suffer a tradeoff with accuracy This paper presents an alternative method of estimating

performance characteristics of linear analog circuits by constructing a model of the circuit matrix.The advantage, as will be seen, is that the matrix can be very accurately modeled even with simplermodeling approaches such as multivariate polynomial regression Since it is possible to accuratelyestimate performance values, true design convergence is obtained by this method

Performance is not directly modeled but it is calculated from the matrix model Although thisrequires some extra computation time, the speed loss is not significant and is offset by the gain inaccuracy and advantage of true convergence The matrix model generation time is dependent on

Sample Performance

Model Performance

Optimization Engine

Goal Met?

Sample Circuit Matrix

Model Circuit Matrix

Calculate Performance No

Yes

Search Space

S P

Key:

S: Proposed Size P: Evaluated Performance

Sizes

Optimization Engine

Goal Met?

Figure 2.1: (a) Performance Modeling Approach (b) Matrix Modeling Approach

the circuit size We have significantly reduced the number of models to be built by utilizing devicematching properties of analog circuits When matrix models are used in optimization based synthe-sis, partial model evaluation is done to speed up the matrix computation in successive iterations

Performance estimation of analog circuits can use either system level models or performancelevel models It is known that the relation between performance parameters such as UGF, PM anddevice sizes is extremely nonlinear [40, 29] Sophisticated modeling approaches such as posyno-mials, neural networks are needed for modeling these severely nonlinear responses However, theseapproaches too give significant errors [38] We have observed that system matrix elements havelesser nonlinearity and can be accurately modeled

Consider the operational Transconductance Amplifier (OTA) in fig B.1 as an example We erated plots of performance parameters against device sizes and matrix elements against device

gen-sizes Figures 2.3, 2.4 are representative plots of performance (PM) and matrix element (gds M4).

We can intuitively state from the figures that the matrix element is less nonlinear The tive observation that matrix elements have less nonlinearity is now backed with two quantitative

Voutn Vinn

Vinp Voutp

Vb Vb1

Vb

Figure 2.2: OTA circuit schematicmeasures:

1 entropy of response curves

2 variance of local differentials

Entropy measures the complexity of a response curve [43], higher the entropy more complex theresponse Entropy of a curve is given by the slope of the cumulative sum of absolute differences

We have used the entropy calculation provided by Denis et al [44] Variance of local first order

differentials measures smoothness of a response, with lesser variance indicating greater smoothness

A response that has low entropy and is smooth is less complex to model

Worst case entropy and local variance values among all matrix elements of the OTA circuit areshown in Table 2.1 The table also shows the entropy and local variance for performance parameters.Phase and Gain Margins have entropy and local variance an order greater than the matrix elements.From these qualitative and quantitative measures we infer that matrix elements are less nonlinearand can be modeled with greater accuracy than their performance counterparts

The matrix elements show a linear or curvilinear variation with respect to design variables Wemodel the response matrix by polynomial regression for polynomial regression it is important that

20 40 60 80 100 120 140 160 180 200 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Mosfet width in um

Figure 2.3: Phase Margin vs Device Width of OTA

20 40 60 80 100 120 140 160 180 200 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Mosfet width in um

Figure 2.4: Matrix Element vs Device Width of OTA

higher order terms do not have high collinearity with lower order terms [45] Therefore the inputvariables of the model are normalized on a [0,1] range using eq.( 2.1)

x trans f ormed= x − x min

It is observed that the capacitance sub-matrix terms are highly collinear with respect to the

Table 2.1: Entropy and Local Differential Variation of OTA

Results are on a dataset of 2000 points

design variables, and lower order polynomials are sufficient for modeling them The conductance

sub-matrix containing terms such as gm, gds etc are more nonlinear and are modeled by higher

order polynomials Once the response model within acceptable error limits is obtained by a LS fit,the regression coefficients are saved The response at any unknown design point within the modelbounds can now be predicted by simply plugging the input variable values in the model given byeq.( 2.2) This makes response prediction extremely fast

2.3.1 Circuit Matrix Generation

The first step in matrix macromodeling is generation of the circuit matrix As explained earlier,

we use MNA formulation to obtain the circuit matrix The matrix generation tool that we havedeveloped takes the circuit netlist at its input The circuit netlist is represented by its spice descrip-tion The tool parses the spice file and determines circuit nodes and elements attached to each node.Active elements are substituted by its small signal equivalent circuit comprising gate capacitancesand controlled sources Once the node information is obtained, the MNA algorithm constructs thesystem matrix symbolically

2.3.2 Reducing number of models

Since we want to model the circuit matrix in terms of its elements, we would like to reduce thenumber of matrix elements to be modeled to as few as possible To enable this reduction, we takeadvantage of:

• matched element identification

• reverse element identification

In the OTA circuit fig B.1, we can see that the transistor pairs M0 − M1, M2 − M3, M4 − M5 and

M6 − M7 are matched Using the half circuit concept [46] we know that the small signal values of

the matched pairs will be equal Thus, if the matrix elements are linear combinations of small signalvalues of matched elements, even these matrix elements will be identical As a simple example,

in the OTA the pairs M0 − M1 and M2 − M3 are matched and gm0 = gm1 and gm2 = gm3 If the

circuit matrix has two elements, one being gm0 + gm2 and the other being gm1 + gm3, we know

that these two elements will always have the same value Thus a single model will be sufficient forboth these matrix elements With the MNA formulation we have seen that such identical elementsoccur at many places in the circuit matrix

It is also observed that in the MNA matrix, some elements appear only with a reversal of polarity

For example, one matrix element is gm4 and the other is −gm4 It is possible to use a single model

for elements that occur with opposite signs Thus, we observed two properties of the circuit matrixelements which will help us reduce the number of elements to be modeled

When the circuit matrix is generated through its MNA formulation, the matrix coefficients arefirst generated in a symbolic form to identify identical and reverse polarity elements For our bench-marks, the number of non-zero coefficients in the original matrix versus the number of coefficientsthat need modeling after reduction is depicted in Table 2.2 The achievable reduction depends onthe topology and the number of matched elements

Table 2.2: Reduction of Matrix Elements

Ma-trix Elements

Elements after Reduction

2.3.3 Data Generation

As with any modeling approach, we first need to generate raw data on which the model will bebuilt The data is obtained by performing a spice operating point analysis at a number of designpoints and storing values of circuit matrix elements We have used random numbers drawn on auniform distribution of the device ranges to sample the entire design space About 2000 randomdata points are sampled for circuits with smaller design space such as the two stage amplifier, OTAand about 4000 points for circuits such as the differential amplifier with a larger design space

We have used high order polynomial response surface models for the circuit matrix as these giveadequate accuracy

2.3.4 Fitting Models for the Matrix Elements

For polynomial models it is important to choose the order appropriately since choosing a lowerorder than necessary will give an erroneous model, whereas choosing a higher order will causeoverfitting In our benchmark circuits we find that polynomials with order 8 and beyond tend tooverfit We predefine the maximum order as 7 for our models The model error is calculated usingeq.( 2.3) We define an error of 0.5% as the allowable model error

ActualValue − PredictedValue

ActualValue

Starting with a linear model, if the model error is less than the allowable error, that order ischosen, else we fit a polynomial with one higher order This is done till the maximum order of 7

is reached In some cases, increasing the order, gives very little return in terms of error reduction

(the adjusted R2 regression criterion), in which we use a lower order model to avoid complexity.Algorithm 1 shows the entire modeling procedure

In order to verify the accuracy of the algorithm, we measure the modeling error for a givencircuit An independent dataset of 1000 uniform random points is generated to validate the matrixmodels Table 2.3 shows the modeling accuracy for each matrix element of the OTA matrix

is reached In some cases, increasing the order, gives very little return in terms of error reduction

(the... little return in terms of error reduction

(the adjusted R2 regression criterion), in which we use a lower order model to avoid complexity.Algorithm shows the entire modeling