Data Sheet High-Performance, Enhanced Flash Microcontrollers phần 1 docx

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICE

Trang 1

Data Sheet

High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

Trang 2

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE Microchip disclaims all liability

arising from this information and its use Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K EE L OQ , microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated

in the U.S.A and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A and other countries.

SQTP is a service mark of Microchip Technology Incorporated

Printed on recycled paper.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EE L OQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products In addition, Microchip’s quality system for the design and

Trang 3

High Performance RISC CPU:

• C compiler optimized architecture/instruction set

- Source code compatible with the PIC16 and

PIC17 instruction sets

• Linear program memory addressing to 32 Kbytes

• Up to 10 MIPs operation:

- DC - 40 MHz osc./clock input

- 4 MHz - 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with

8-bit programmable prescaler

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter with 8-bit

period register (time-base for PWM)

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules

CCP pins that can be configured as:

- Capture input: capture is 16-bit,

max resolution 6.25 ns (TCY/16)

Peripheral Features (Continued):

• Addressable USART module:

- Fast sampling rate

- Conversion available during SLEEP

• Programmable Low Voltage Detection (PLVD)

- Supports interrupt on-Low Voltage Detection

• Programmable Brown-out Reset (BOR)

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced FLASH program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory

• FLASH/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options including:

- 4X Phase Lock Loop (of primary oscillator)

- Secondary Oscillator (32 kHz) clock input

• Single supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

Data EEPROM (bytes) FLASH

(bytes)

# Single Word Instructions

28/40-pin High Performance, Enhanced FLASH

Microcontrollers with 10-Bit A/D

Trang 4

Pin Diagrams

10 11 12 13 14 15 16

1718 19 20 21 22 23 24 25 26

8 7

6 5 4 3 2 1

27 28 29

30 31 32 33 34 35 36 37 38 39

OSC2/CLKO/RA6

NC

RE1/WR/AN6 RE2/CS/AN7

V DD

OSC1/CLKI

RB3/CCP2 *

RB2/INT2 RB1/INT1 RB0/INT0

V DD

V SS

RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT

2 3 4 5 6 1

18 19 20 21 22

12 13 14 15

8 7

44 43 42 41 40 39

16 17

29 30 31 32 33

23 24 25 26 27 28

V SS

V DD

RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI

RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

V SS

V DD

RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 *

Trang 5

Pin Diagrams (Cont.’d)

RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CCP2 *

V DD

V SS

RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2

MCLR/V PP

RA0/AN0 RA1/AN1 RA2/AN2/V REF - RA3/AN3/V REF + RA4/T0CKI RA5/AN4/SS/LVDIN RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7

V DD

V SS

OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 *

RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

2 3 4 5 6 1

8 7

9

12 13

16 17 18 19 20

23 24 25 26 27 28

22 21

MCLR/V PP

RA0/AN0 RA1/AN1 RA2/AN2/V REF - RA3/AN3/V REF + RA4/T0CKI RA5/AN4/SS/LVDIN

V SS

OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 *

RC2/CCP1 RC3/SCK/SCL

RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CCP2 *

V DD

V SS

RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

* RB3 is the alternate pin for the CCP2 pin multiplexing.

Trang 6

Table of Contents

1.0 Device Overview 7

2.0 Oscillator Configurations 17

3.0 Reset 25

4.0 Memory Organization 35

5.0 FLASH Program Memory 55

6.0 Data EEPROM Memory 65

7.0 8 X 8 Hardware Multiplier 71

8.0 Interrupts 73

9.0 I/O Ports 87

10.0 Timer0 Module 103

14.0 Capture/Compare/PWM (CCP) Modules 117

15.0 Master Synchronous Serial Port (MSSP) Module 125

16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) 165

17.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module 181

18.0 Low Voltage Detect 189

19.0 Special Features of the CPU 195

20.0 Instruction Set Summary 211

21.0 Development Support 253

22.0 Electrical Characteristics 259

23.0 DC and AC Characteristics Graphs and Tables 289

24.0 Packaging Information 305

Appendix A: Revision History 313

Appendix B: Device Differences 313

Appendix C: Conversion Considerations 314

Appendix D: Migration from Baseline to Enhanced Devices 314

Appendix E: Migration from Mid-range to Enhanced Devices 315

Appendix F: Migration from High-end to Enhanced Devices 315

Index 317

On-Line Support 327

Reader Response 328

PIC18FXX2 Product Identification System 329

Trang 7

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products To this end, we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150 We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

Trang 8

NOTES:

Trang 9

1.0 DEVICE OVERVIEW

This document contains device specific information for

the following devices:

These devices come in 28-pin and 40/44-pin packages

The 28-pin devices do not have a Parallel Slave Port

(PSP) implemented and the number of

Analog-to-Digital (A/D) converter input channels is reduced to 5

An overview of features is shown in Table 1-1

The following two figures are device block diagramssorted by pin count: 28-pin for Figure 1-1 and 40/44-pinfor Figure 1-2 The 28-pin and 40/44-pin pinouts arelisted in Table 1-2 and Table 1-3, respectively

MSSP, Addressable USART

RESETS (and Delays)

POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST)

POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST)Programmable Low Voltage

Detect

28-pin SOIC

28-pin DIP28-pin SOIC

40-pin DIP44-pin PLCC44-pin TQFP

Trang 10

FIGURE 1-1: PIC18F2X2 BLOCK DIAGRAM

Instruction Decode &

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1)RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.

2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions The multiplexing combinations

are device dependent.

PRODL PRODH

16

8

8 8

8

Register Table Latch

Table Pointer

inc/dec logic

Decode

RB0/INT0

RB4

RB1/INT1 RB2/INT2 RB3/CCP2(1)

RB5/PGM RB6/PCG RB7/PGD

Data EEPROM

Power-up Timer Oscillator Start-up Timer Power-on Reset

Watchdog Timer

Timing Generation

Trang 11

FIGURE 1-2: PIC18F4X2 BLOCK DIAGRAM

Power-up Timer Oscillator Start-up Timer Power-on Reset

Watchdog Timer

Instruction Decode &

RB0/INT0

RB4

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1)RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Brown-out Reset

RA3/AN3/V REF + RA2/AN2/V REF - RA1/AN1 RA0/AN0

Timing Generation

4X PLL

A/D Converter

RB1/INT1

Data Latch Data RAM (up to 4K address reach) Address Latch

Address<12>

12(2)

Bank0, F BSR FSR0 FSR1 FSR2

PCH PCL PCLATH 8

31 Level Stack Program Counter

PRODL PRODH

16

8

8 8

RB2/INT2 RB3/CCP2(1)

Register

8

Table Pointer

inc/dec logic

Decode

RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

Low Voltage Programming

In-Circuit Debugger

RB5/PGM RB6/PCG RB7/PGD

Trang 12

High voltage ICSP programming enable pin.

Oscillator crystal or external clock input

Oscillator crystal input or external clock source input

ST buffer when configured in RC mode, CMOS otherwise.External clock source input Always associated with pin function OSC1 (See related OSC1/CLKI, OSC2/CLKO pins.)

Oscillator crystal or clock output

Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode

In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate

General Purpose I/O pin

PORTA is a bi-directional I/O port

TTLAnalog

TTLAnalogAnalog

ST/ODST

Digital I/O Open drain when configured as output

Timer0 external clock input

TTLAnalogSTAnalog

Digital I/O

Analog input 4

SPI Slave Select input

Low Voltage Detect Input

OD = Open Drain (no P diode to VDD)

Trang 13

PORTB is a bi-directional I/O port PORTB can be software programmed for internal weak pull-ups on all inputs

TTLST

Digital I/O

Capture2 input, Compare2 output, PWM2 output

TTLST

Digital I/O Interrupt-on-change pin

Low Voltage ICSP programming enable pin

TTLST

In-Circuit Debugger and ICSP programming clock pin.RB7/PGD

RB7

PGD

I/OI/O

TTLST

In-Circuit Debugger and ICSP programming data pin

Trang 14

PORTC is a bi-directional I/O port.

ST

—ST

Digital I/O

Timer1 oscillator output

Timer1/Timer3 external clock input

STCMOSST

Digital I/O

Timer1 oscillator input

Capture2 input, Compare2 output, PWM2 output

STST

STSTST

Digital I/O

Synchronous serial clock input/output for SPI mode

STSTST

ST

—ST

Digital I/O

USART Asynchronous Transmit

USART Synchronous Clock (see related RX/DT)

STSTST

Digital I/O

USART Asynchronous Receive

USART Synchronous Data (see related TX/CK)

Trang 15

TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS

High voltage ICSP programming enable pin

Oscillator crystal or external clock input

Oscillator crystal input or external clock source input ST buffer when configured in RC mode, CMOS otherwise

External clock source input Always associated with pin function OSC1 (See related OSC1/CLKI, OSC2/CLKO pins.)

Oscillator crystal or clock output

Oscillator crystal output Connects to crystal

or resonator in Crystal Oscillator mode

In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate

General Purpose I/O pin

PORTA is a bi-directional I/O port

TTLAnalog

TTLAnalogAnalog

ST/ODST

Digital I/O Open drain when configured as output.Timer0 external clock input

Định dạng
Số trang	31
Dung lượng	418,19 KB