Data Sheet High-Performance, Enhanced Flash Microcontrollers phần 9 ppt

Figure 22-4 specifies the load conditions for the timing specifications.. TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS Standard Operating Conditions unless

22.3.2 TIMING CONDITIONS

The temperature and voltages specified in Table 22-3

apply to all timing specifications unless otherwise

noted Figure 22-4 specifies the load conditions for the

timing specifications

TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA≤ +85°C for industrial

-40°C ≤ TA≤ +125°C for extendedOperating voltage VDD range as described in DC spec Section 22.1 and Section 22.2

LC parts operate for industrial temperatures only

CL = 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 22-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO, -40°C to +85°C

Oscillator Frequency(1) DC 25 MHz EC, ECIO, +85°C to +125°C

Oscillator Period(1) 40 — ns EC, ECIO, +85°C to +125°C

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations

except PLL All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in

an unstable oscillator operation and/or higher than expected current consumption All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin When an external clock input

is used, the “max.” cycle time limit is “DC” (no clock) for all devices

TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS (V DD = 4.2 TO 5.5V)

FIGURE 22-6: CLKO AND I/O TIMING

Param

† Data in “Typ” column is at 5V, 25°C unless otherwise stated These parameters are for design guidance only and are not tested

Note: Refer to Figure 22-4 for load conditions.

TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS

TIMER TIMING

Param

15 TioV2ckH Port in valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)

18 TosH2ioI OSC1↑ (Q2 cycle) to Port

input invalid (I/O in hold time)

19 TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns

†† These parameters are asynchronous events not related to any internal clock edges

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC

I/O Pins

34

Note: Refer to Figure 22-4 for load conditions.

FIGURE 22-8: BROWN-OUT RESET TIMING

AND BROWN-OUT RESET REQUIREMENTS

Enable Internal Reference Voltage

Internal Reference Voltage stable 36

Typical

Param

31 TWDT Watchdog Timer Time-out Period

(No Postscaler)

32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period

34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset

D005)

36 TIVRST Time for Internal Reference

Voltage to become stable

37 TLVD Low Voltage Detect Pulse Width 200 — — μs VDD≤ VLVD (see

D420)

FIGURE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Note: Refer to Figure 22-4 for load conditions.

With Prescaler Greater of:

20 nS or TCY + 40 N

value (1, 2, 4, , 256)

Time

Synchronous,with prescaler

value (1, 2, 4, 8)

48 Tcke2tmrI Delay from external T1CKI clock edge to timer

increment

FIGURE 22-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

Note: Refer to Figure 22-4 for load conditions.

CCPx (Capture Mode)

FIGURE 22-11: PARALLEL SLAVE PORT TIMING (PIC18F4X2)

TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2)

Note: Refer to Figure 22-4 for load conditions.

65

Param

62 TdtV2wrH Data in valid before WR↑ or CS↑

(setup time)

2025

—

—

ns

ns Extended Temp Range

63 TwrH2dtI WR↑ or CS↑ to data–in invalid

ns

ns Extended Temp Range

66 TibfINH Inhibit of the IBF flag bit being cleared from

WR↑ or CS↑

— 3 TCY

FIGURE 22-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

72 TscL SCK input low time

Setup time of SDI data input to SCK edge 100 — ns

73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

75, 76

78 79

80

79 78

Note: Refer to Figure 22-4 for load conditions.

FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param

71 TscH SCK input high time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

72 TscL SCK input low time

Setup time of SDI data input to SCK edge 100 — ns

73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL

Note 1: Requires the use of Parameter # 73A.

MSb

79 73

MSb In

bit6 - - - -1

LSb In bit6 - - - -1

LSb

Note: Refer to Figure 22-4 for load conditions.

FIGURE 22-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))

TdiV2scL

73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 — ns (Note 2)

TscL2diL

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

80

79 78

FIGURE 22-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 22-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

(Slave mode)

Continuous 1.25 TCY + 30 — ns

73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 — ns (Note 2)

TscL2diL

FIGURE 22-16: I 2 C BUS START/STOP BITS TIMING

TABLE 22-15: I 2 C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 22-17: I 2 C BUS DATA TIMING

Note: Refer to Figure 22-4 for load conditions.

91

92

93 SCL

SDA

START Condition

STOP Condition 90

Param

90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for Repeated

START condition

91 THD:STA START condition 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

92 TSU:STO STOP condition 100 kHz mode 4700 — ns

93 THD:STO STOP condition 100 kHz mode 4000 — ns

Note: Refer to Figure 22-4 for load conditions.

90

100

101 103

TABLE 22-16: I 2 C BUS DATA REQUIREMENTS (SLAVE MODE)

Param

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock high time 100 kHz mode 4.0 — μs PIC18FXXX must operate at a

before a new transmission can start

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement T SU : DAT ≥ 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

T R max + T SU : DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released

FIGURE 22-18: MASTER SSP I 2 C BUS START/STOP BITS TIMING WAVEFORMS

TABLE 22-17: MASTER SSP I 2 C BUS START/STOP BITS REQUIREMENTS

FIGURE 22-19: MASTER SSP I 2 C BUS DATA TIMING

Note: Refer to Figure 22-4 for load conditions.

SCL

SDA

START Condition

STOP Condition

Param.

90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated START condition

Setup time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock pulse is generatedHold time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Setup time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

93 THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Hold time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C pins

Note: Refer to Figure 22-4 for load conditions.

90

100

101 103

TABLE 22-18: MASTER SSP I 2 C BUS DATA REQUIREMENTS

Param.

100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

91 THD:STA START condition

hold time

100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

clock pulse is generated

110 TBUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be free

before a new transmission can start

Note 1: Maximum pin capacitance = 10 pF for all I2C pins

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥ 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line

is released

FIGURE 22-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 22-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

TABLE 22-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS

120 TckH2dtV SYNC XMIT (MASTER & SLAVE)

125 TdtV2ckl SYNC RCV (MASTER & SLAVE)

126 TckL2dtl Data hold after CK ↓ (DT hold time) PIC18FXXX 15 — ns

TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED)

PIC18LFXX2 (INDUSTRIAL)

FIGURE 22-22: A/D CONVERSION TIMING

Param

VDD < 3.0V

VDD≥ 3.0V

A25 VAIN Analog input voltage AVSS – 0.3V — AVDD + 0.3V V VDD ≥ 2.5V (Note 3)A30 ZAIN Recommended impedance of

analog voltage source

μAμA

During VAIN acquisition During A/D conversion cycle

2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.

131 130 132

(Note 2)

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts

This allows the SLEEP instruction to be executed

2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input.

T CY

TABLE 22-22: A/D CONVERSION REQUIREMENTS

Param

130 TAD A/D clock period PIC18FXXX 1.6 20(4) μs TOSC based

VREF = VDD = 5.0V

VREF = VDD = 2.5V

135 TSWC Switching Time from convert → sample — (Note 3)

Note 1: ADRES register may be read on the following TCY cycle

2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not

changed by more than 1 LSB from the last sampled voltage The source impedance (RS) on the input channels

is 50Ω See Section 17.0 for more information on acquisition time consideration

3: On the next Q4 cycle of the device clock

4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider

23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

“Typical” represents the mean of the distribution at 25°C “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)respectively, where σ is a standard deviation, over the whole temperature range

FIGURE 23-1: TYPICAL I DD vs F OSC OVER V DD (HS MODE)

FIGURE 23-2: MAXIMUM I DD vs F OSC OVER V DD (HS MODE)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only The performance characteristics listed herein arenot tested or guaranteed In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore, outside the warranted range

FIGURE 23-3: TYPICAL I DD vs F OSC OVER V DD (HS/PLL MODE)

FIGURE 23-4: MAXIMUM I DD vs F OSC OVER V DD (HS/PLL MODE)

FIGURE 23-5: TYPICAL I DD vs F OSC OVER V DD (XT MODE)

FIGURE 23-6: MAXIMUM I DD vs F OSC OVER V DD (XT MODE)

Typical: statistical mean @ 25°C

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Minimum: mean – 3 σ (-40°C to 125°C)

FIGURE 23-7: TYPICAL I DD vs F OSC OVER V DD (LP MODE)

FIGURE 23-8: MAXIMUM I DD vs F OSC OVER V DD (LP MODE)

3.0V 2.5V 2.0V

Typical: statistical mean @ 25°C

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3 σ (-40°C to 125°C)

FIGURE 23-9: TYPICAL I DD vs F OSC OVER V DD (EC MODE)

FIGURE 23-10: MAXIMUM I DD vs F OSC OVER V DD (EC MODE)

4.2V

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3 σ (-40°C to 125°C)

FIGURE 23-11: TYPICAL AND MAXIMUM I DD vs V DD

(TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C1 AND C2 = 47 pF)

FIGURE 23-12: AVERAGE F OSC vs V DD FOR VARIOUS VALUES OF R

Typical: statistical mean @ 25°C

FIGURE 23-13: AVERAGE F OSC vs V DD FOR VARIOUS VALUES OF R

FIGURE 23-15: I PD vs V DD , -40 °C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 23-16: ΔI BOR vs V DD OVER TEMPERATURE (BOR ENABLED, V BOR = 2.00 - 2.16V)

Max (-40°C to +125°C)

Typical: statistical mean @ 25°C

Device

in Sleep

Max (+125°C)

Max (+85°C)

Typ (+25°C)

Device Held in RESET

Device in SLEEP

FIGURE 23-17: TYPICAL AND MAXIMUM ΔI TMR1 vs V DD OVER TEMPERATURE (-10 °C TO +70°C,

TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)

FIGURE 23-18: TYPICAL AND MAXIMUM ΔI WDT vs V DD OVER TEMPERATURE (WDT ENABLED)