Chương 4: Fet potx

JFET - characteristic IG=0A dòng cực cổng  ID=IS dòng cực phát = dòng cực nguồn..  ID=IDSS1-VGS/VGSoff2 for JFET, DMOSFET VGSoff=VP  ID=kVGS-VGSth2 for EMOSFET, k=IDon/VGSon-VT... M

 Biasing configuration - chapter 6

 FET small signal analysis – chapter 9

JFET - Construction

JFET - operation

 VGS=0, VDS>0

JFET - operation

 VGS<0, VDS>0

 VGS=0, VDS=VP

JFET - characteristic

 IG=0A (dòng cực cổng)

 ID=IS (dòng cực phát = dòng cực nguồn).

 ID=IDSS(1-VGS/VGS(off))2 for JFET, DMOSFET (VGS(off)=VP)

 ID=k(VGS-VGSth)2 for EMOSFET, k=IDon/(VGSon-VT)

JFET - characteristic

P-channel, IDSS=6mA, VP=6V N-channel, IDSS=8mA, VP=-4V

Storage channel temp

range Tstg -60 to +150

0C

MOSFET - construction

N-channel enhancement N-channel depletion

MOSFET – transfer characteristic

N-channel enhancement N-channel depletion

MOSFET – transfer characteristic

P-channel enhancement P-channel depletion

Igate reverse(Vgs=+-15, Vds=0) IGSS +-10 nAdc

 CMOS=Complementary MOSFET

 pMOS and nMOS on the same substrate

 Can reduce size and power consumption of MOSFETs

 Use mostly for IC

 pMOS and nMOS ON/OFF operation

 Example: inverter

Configuration

 Common source configuration

 Common gate configuration

 Common drain configuration

 Fixed-bias configuration

 Self-bias configuration

 Voltage-divider biasing

Fixed-bias configuration

 ID = IDSS(1-VGS/VGS(off))2

 VDS = VDD - RDID

 Note: n-type, VGS<0, for JFET and D-MOSFET

 Rarely use for E-MOSFET

Self-bias configuration

 ID = IDSS(1-VGS/VGS(off))2= IDSS(1+RSID/VGS(off))2

 Note: n-type, VGS<0, for JFET and D-MOSFET

 Rarely use for E-MOSFET

Voltage-divider configuration

 VGS=VG-IDRS;VDS=VDD-RDID-RSIS=VDD–(RD+RS)ID

 ID = IDSS(1-VGS/VGS(off))2 , VGS<0, for JFET and D-MOSFET

 ID=k(VGS-VGSth)2 , VGS>0, k=IDon/(VGSon-VT) for E-MOSFET

Voltage-divider configuration

Note:

 VGS<0, for JFET and D- MOSFET

 VGS>0, for MOSFET

E-Feedback biasing configuration

 VDS = VDD-RDID

 ID=k(VGS-VGSth)2 for EMOSFET k=IDon/(VGSon-VT)

 Note: VGS>0, for E-MOSFET

FET small signal analysis

 FET model: (a)

 r∏ large, about n100-n1000 MΩ=>can ignore=> (b)

• Can ignore if RD small => (c)

Common source - CS

Common drain - CD

Common gate

Example

Example