Thiết kế và thực hiện hệ thống VLSI - 02 pot

In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the junction is zero... N MOS AND P MOS TRANSISTORSnMOS transistor p

Design and Implementation of

VLSI Systems Lecture 02

Thuan Nguyen Faculty of Electronics and Telecommunications,

University of Science, VNU HCMUS

Spring 2011

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L ECTURE 2: CMOS C IRCUIT

L ECTURE 2: CMOS C IRCUIT

silicon 4.995  10 22 atoms in cm 3

W HAT HAPPENS IF WE SANDWICH P & N TYPES ?

In equilibrium, the drift and diffusion components of current

are balanced; therefore the net current flowing across the

junction is zero

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W HAT HAPPENS IF WE SANDWICH P & N TYPES ?

6

PN- JUNCTION REGIONS OF OPERATION

In reverse bias, the width

of the depletion region

increases The diode acts

as voltage-controlled

capacitor

A forward bias decreases the potential drop across the

junction As a result, the magnitude of the electric field decreases and the width of the depletion region narrows

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N MOS AND P MOS TRANSISTORS

nMOS transistor pMOS transistor

Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk)

Body is typically grounded Body is typically at supply voltage 8

N MOS TRANSISTOR

n+

p

Gate Source Drain

bulk Si

SiO2 Polysilicon

n+

g=0: When the gate is at a low voltage (VGS < VTN):

 p-type body is at low voltage

 source and drain-junctions diodes are OFF

 transistor is OFF, no current flows

g=1: When the gate is at a high voltage (VGS ≥ VTN):

 negative charge attracted to body

 inverts a channel under gate to n-type

 transistor ON, current flows, transistor

N MOS PASS ‘0’ MORE STRONGLY THAN ‘1’

n+

p

Gate Source Drain

bulk Si

SiO2 Polysilicon

n+

• Why does ‘1’ pass degraded?

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P MOS TRANSISTOR

SiO2

n

Gate Source Drain

bulk Si

Polysilicon

g=0: When the gate is at a low voltage (VGS < VTP):

 positive charge attracted to body

 inverts a channel under gate to p-type

 transistor ON, current flows

g=1: When the gate is at a high voltage (VGS ≥ VTP):

 negative charge attracted to body

 source and drain junctions are OFF

 transistor OFF, no current flows

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P MOS PASS ‘1’ MORE STRONGLY THAN ‘0’

SiO2

n

Gate Source Drain

L ECTURE 2: CMOS C IRCUIT

pMOS + nMOS = CMOS

M ORE CMOS GATES

What is this gate function?

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A B

Y

3- INPUT NAND S

What are the advantages of CMOS circuit style?

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pMOS pull-up network

output inputs

nMOS pull-down network

S ERIES -P ARALLEL C OMBINATIONS

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 nMOS: 1 = ON

 pMOS: 0 = ON

 Series: both must be ON

 Parallel: either can be ON

OFF ON ON ON

(d) ON ON ON OFF

a

b 0

a

b 1

a

b 1

a

b

1

1 0 1 a

b g1 g2

W HAT ARE THE TRANSISTOR SCHEMATICS OF

2:00 1:11 1:10 0:11 0:10 End 18

A B

Y

p

Gate Source Drain

bulk Si

SiO2 Polysilicon

pMOS strong ‘1’, weak ‘0’  VDD

nMOS strong ‘0’, weak ‘1’  VSS

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pMOS + parallel + pull up

nMOS + serial + pull down

pMOS + serial + pull up

nMOS + parallel + pull down

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W HAT ARE THE TRANSISTOR SCHEMATICS OF

THE NOR GATE ?

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A ND -O R -I NVERTER (AOI) GATE

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A

B

C D

A

B

C D

B D

Y A

C

A C

A B

C D

B D

T RI - STATE INVERTER

A

Y EN

2:1 M ULTIPLEXER (2:1 MUX)

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0 1

S D0

2:1 I NVERTING MUX

 Inverting multiplexer

 Or pair of tristate inverters

 Essentially the same thing

 Noninverting multiplexer adds an inverter

S

Y

S D0

D1

Y

0 1 S

Y

D0

D1 S

4:1 M ULTIPLEXER (4:1 MUX)

4:1 mux chooses one of 4 inputs using two selects

 Two levels of 2:1 muxes

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D L ATCH

 a.k.a transparent latch or level-sensitive latch

D L ATCH D ESIGN

 Multiplexer chooses D or old Q

1 0 D

CLK

CLK CLK

D F LIP - FLOP

 At all other times, Q holds its value

 a.k.a positive edge-triggered flip-flop,

Q

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D F LIP - FLOP D ESIGN

 Built from master and slave D latches

QM CLK

CLK CLK

D F LIP - FLOP O PERATION

Q

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H OMEWORKS

 Homework Assignment #1 View

 Submit your answer in the next week

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Q & A

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