21st Century Manufacturing Episode 2 Part 1 ppsx

This shows a a mask at the top, b the mask positioned above the photoresist on the wafer, and c the preferentially damaged photoresist on top of the silicon dioxide layer.. Reprinted by

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Siwafer 1f. O.Ol-1.0I-lmSi02

<hi Ftpre5.17 Simplified views of the oxidation equipment and process (from

Semiconductor Device Fundamentals by Pierret, © 1996 Reprinted by permission

of Prentice-Hall, Inc., Upper Saddle River, NJ)

However, dry oxygen is again preferred for growing the gate oxide's Si02

because it gives better Si to Si02 interface properties Rapid thermal oxidation (RTO) allowsshort timeoxidation at suitably hightemperatures (Campbell, 1996) 5.10.3 Creating Photomasks

The CAD files containing the desired circuit patterns are transferred to a set of

pho-tographic plates or photomasks To do this, the CAD files are first fed into a pattern generator-acomputer controlled exposure machine The generator uses flash expo-sure to transfer the IC pattern onto a light-sensitive plate known as the mask This step is similar to photographic developing The generator flashes onto the plate a large series of rectangles that correspond to the circuit diagram The plate is covered

in an emulsion/photoresist material, which deliberately breaks down under the exposure Then, once the exposed resist is sloughed off, the plate is transparent just

in those areas that correspond to the circuit

5.10.4 Photolithography: Projecting the Mask Pattern onto

theWBfer

Many steps follow to transfer the pattern in each photomask to the wafer The wafer surface is coated with light-sensitive photoresist material Typically, photoresist liquid is poured onto the center of the round wafer, which is spunat 1,000 to 5,000 rpm in order to produce a uniform, thin adhesion Thethickness of the film can be controlled by altering liquid viscosity and spinning speed The photoresist is dried in

a warm nitrogen or plain air oven

Photolithography is shown in Figures 5.18 through 5.20 In the early days of IC manufacture, contactandproximityprinting were used (Wolf and Tauber, 1986) In

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M:lstep.-scan Flame 5.19 Schematics of the different stepper configurations in the lithography process

Figure 5.18 is more in keeping with theproximity-type photomask This shows (a) a mask at the top, (b) the mask positioned above the photoresist on the wafer, and (c) the preferentially damaged photoresist on top of the silicon dioxide layer During photolithography, ultraviolet (UV) light exposes the photoresist in a prescribed way, depending on whether anegative orpositive resist material is being used Positive resists are now the norm in industry because they give better control for small transistor features Positive resists contain a sensitizer that normally pre-vents them from being dissolved away in an alkaline developer solution bath But if they are exposed to the UV light that has come through the patterns in the mask, the

erentially removed, leaving a city block-like structure

In early Ie production, it was also possible to expose many dice at once One simultaneous exposure was done with a mask that contained many repeats of the same pattern However, asIefeatures became smaller, it was found difficult to achieve the registration from one photomask to the next Also, wafers can get ther-mally distorted during the intermediate CVD or doping/diffusion steps

Of course, precise alignment of the wafer and the mask is absolutely essential for each subsequent layer to match up with the previous one For that reason, today,

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fItue 5.2G Schematic of the reduction step lind repeat technique for projection printing

Reduction lens system

die on the wafer, is exposed This is the method called projection printing using a lens

system that is mounted well away from the wafer surface The photomask is inserted

in a step-and-repeat camera, or the optical wafer stepper.1bis transfers the pattern by

beaming a light through the lens system to the photoresist The images are dernagnl-tied through the lens down onto the wafers (Figures 5.19 and 5.20)

5.10.5Etching: Creating the Transistor Channels

Once the pattern is transferred, the light-exposed areas of the photoresist are removed by developing, and the remaining photoresist is baked to harden and

con-chemical solutions or a dry plasma gas can be used to selectively etch away those

areas of unexposed photoresist protect the underlying areas of the pattern that are

to be temporarily kept in place

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Figure 5.21 Wet etching (left) creates undercutting as opposed to dry reactive ion etching (right) (fromIntroduction 10 Microelectric Fabrication by Jaeger,© 1988 Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, NJ)

Wet etching with a solution containing hydrofluoric acid (HF) creates the val-leys or windows innitride/oxide layers Temperature, time, and solution strength are monitored carefully so that the nitride/oxide on the substrate is etched quickly, and yet the photoresist on the other surfaces is not damaged

Wet etching causes undercutting into the walls underneath the photoresist,asshown

on the left of Figure 5.21.Thus, although wet etching might still be done in small

proto-does not create the undercutting It can be done with a variety of plasma beams For example, reactive ion etching (RIE) simultaneously attacks the surface with chemical and physical effects.The plasma is excited in a radio-frequency electric field, and a stream of reactive ions hits the surface to achieve the following for a silicon surface:

• Gases containing fluorine or chlorine interact chemically with a silicon com-pound and weaken the inherent structure

• The ions in the plasma have enough energy to knock out the exposed, weak-ened atoms, thereby eroding the surface

Note that dry etching may also be used in the later stages to etch patterns into the aluminum interconnect layers

An examination of Figure 5.22 shows the result of some of the processing steps:

• The photoresist is protecting a layer of silicide on top of a layer of polysilicon

on top of the silicon wafer (dark gray)

• The protected areas are 0.5 micron wide

• The unprotected areas are 1.5 microns wide

• The dry etching prevents undercutting, but there is still some undesirable tapering of the vertical walls

• The silicide (TISz) is 0.18 micron thick, and the polysilicon is 0.26 micron thick 5.10.6Doping: Selectively Isolating the Active Transistor

and Select AreBs

Doping can be accomplished by bombarding the silicon with dopant atoms from

a particle accelerator (ion implantation) followed by further controlled drive-in diffusion

Ion implantation uses a high-voltage accelerator to induce dopant atoms into

Resist

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Figure 5.22 Result of using photoresist to protect the polysilicon covered channels 0.5 micron wide (fromDevice Electron.ics for Integrated Circuits,

Richard S Muller and Theodore I Kamins, Copyright © 1986 Reprinted by permission of John Wiley&Sons, Inc.)

more precisely controlled, and allows a wider range of barrier layer materials Fig-ure 5.23 shows that the desired dopant atoms are ionized (bottom right) and then accelerated by an electric field (center of figure) to energies that typically range from

25 to 200 keV When this beam hits the exposed surfaces, the dopant atoms penetrate the first 1 to 2 microns of the surface layer This high-energy bombardment in fact also damages the crystallographic lattice of the silicon The structure is therefore annealed, and this also has the effect of locating the dopants at the substitutional rather than interstitial sites to create n" or»:regions

a-type dopant impurity

FIaure.5.24 The basic diffusion process (from Semiconductor Device

Fundamentals by Pierret, © 1996 Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, NJ)

The ion implantation method allows good control of the dopant concentration: dopant concentrations are measured in the number of atoms per square centimeter

of surface.High purity of dopants is possible because a mass spectrometer (labeled analyzer magnet in the figure) near the dopant source acts as a sorting agent, allowing only the desired dopant species to reach the wafer target

Also it should be mentioned that ion implantation can penetrate through an existing layer such as the thin oxide shown in Figures 5.6 and 5.11 Thus additional doping can be done after the high-temperature cycles that form the Si02•Muller and

SiwaIers T",900aC-1200"C

Original p-dopaut Diffused

~n·dopant

Drive-in diffusion follows ion implantation to create a deeper penetration.

Figure 5.24 schematically shows the diffusion at around 1,OOO"C of an a-type dopant

into an existing p-type doped substrate The concentration of dopant is governed by

Fick's law of diffusion (see, for example, Muller and Kamins, 1986)

5.10.7 Chemical Vapor Deposition (CVDI: Creating Layers

for Barriers and Circuits

Thin layers and other materials can be sequentially deposited on the wafer with chemical vapor deposition (CVD) Out of interest, also note that CVD is used

exten-involves thermal reactions or breakdowns of gas compounds to coat the substrate This is a popular method for depositing barrier layers Polysilicon, silicon dioxide, and silicon nitride are routinely deposited using CVD In Figures 5.25 and 5.26

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load

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ft&me 5.25 Low-pressure CVD (fromDevice Electronics for Inregrated Circuits,

Richard S Muller and Theodore I Kamins, Copyright © 1986 Reprinted by

Wafers

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Standup wafers-

Gas control system

'Source gases Pomp Trap

Fipre 5.26 Plasma enhanced CVD.

routinely used to deposit Si02and Si3N4and polysilicon The diagram shows the gases flowing around the vertical wafers where surface reaction and diffusion take place The plasma enhanced (PECVD) process is chosen becauseitoccurs at lower temperatures and is well suited to certain operations For example, the final deposi-tion of the passivadeposi-tion layer on top of the aluminum interconnecdeposi-tions must occur below 500°Cso that the aluminum does not melt

Ametallurgical cross section through the films createdbythe CVD methods reveals amorphous or polycrystalline transitional layers that build from the pure

substrate By contrast, epitaxy differs from these previous CVD methods because it

commonly used to grow a thin layer of single crystal silicon onto the silicon wafer Vapor phase silicon tetrachloride (SiC4) or silane (SiH4)is used to form additional silicon on top of a preexisting structure It is especially useful when needing to grow

a lightly doped layer of silicon on the top of a heavily doped substrate, particularly

in bipolar transistors It is also useful in CMOS techniques to grow lightly doped

described in detail in Campbell (1996, see Chapter 14)

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5.10.8 Interconnections and Contacts

To produce a functioning integrated circuit, the millions of transistors and devices fabricated through the repeated photolithography-etching-doping-deposition cycles must finally be interconnected Interconnections are made with metals that adhere well to substrate materials Aluminum or aluminum-silicon-copper alloys are gener-ally used Copper will increasingly be used to achieve smaller submicron circuit geometries (Singer, 1997; Braun, 1999) Between two and six layers (shown in Figure 5.27) of metal are deposited over the entire surface of the wafer, with each layer insu-lated by a dielectric layer Metal penetrates to the active transistor regions to form the interconnections to, say, the n+region shown on the left of Figure 5.27 The second and other layers create circuits between different transistors and devices

Dif-vias,also indicated in the right side of the figure

Sputtering deposits thin films onto the wafer surface in vacuum conditions A

source of the desired deposition material is bombarded with ions, typically ions of argon, AI+.1his knocks out atoms from the source, which then sputter onto the wafer and create the thin film The general setup for a conductive material such as aluminum

are mounted on the system's anode in the lower part of the figure

Evaporation processes can alternatively be used to deposit a thin surface film

on the wafer for the aluminum interconnections As shown in Figure 5.29, an alu-minum source is heated and vaporized inside a vacuum chamber The wafers are

aluminum vapor travels through the chamber to be deposited on the wafer Careful control of temperature, atmosphere, and placement is obviously needed to create layers

• Infilament evaporation, short samples of aluminum wire are heated in a tung-sten boat or are hung from the loops of a resistance-heated tungtung-sten filament Resistance heating vaporizes the aluminum source

• Inflash evaporation a spool of the aluminum wire is constantly fed into the vacuum chamber A heated ceramic bar vaporizes the incoming wire

• Inelectron-beam evaporation, a fixed source is heated and vaporized with a 15ke V

"e-beam.vThe filament and fiash heating methods are subject to the purity of the source

F'lgureS.27 Basic two-level metallization (fromManufacturing Processes for Engineering Malerilll.Jby Kalpakjian, ©1m.Reprinted by

permission of Prentice-Hall, Inc., Upper Saddle River, NJ)

Si Si02

Contact

First-level

metal

Second_level metBl

Si02

Vacuum chilwber

Cathode shield

Anode

Argon inlet

Cathode (sourcemateriaI)

To vacuum pump

figure 5.28 Sputtering for the interconnect layers (from Introduction to

Microelecrric Fab,kotwnby Jaeger, ©1988 Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, NJ)

/Wafer

Fipe 5.29 Hotfilament evaporation

(from Semiconductor Device Fundamentals by Pierret,©1996 Reprinted by permission of Prentice-Hall, Iac., Upper Saddle River, NJ)

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To vacuum pump

The e-beam method can cause wafer damaging x-rays In general practice all these evaporation techniques are less favored in today's commercial tabs Sput-tering is used for its superior topological coverage and moderate pressure requirements

After the last layer of metal is patterned, a final passivation layer is deposited

in order to protect the [C from contamination and damage Small openings are then

will be attached to the package

Wafers

Heater

Evaporating

"material

5.11 BACK·END PROCESSING METHODS

5.11.1 Summary

Wafers are electronically tested for functionality and separated into individual dice Each die is set into a chosen package, wire-bonded to the outer perimeter of the package, and finally tested ready for assembly onto a printed circuit board (PCB)

This segment of semiconductor production is called back-end processing Figure 5.30

provides an overview of these back-end steps for one of the most common package types, the dual-in-line package The single IC is shown on the front right side It is set onto the base with epoxy or a metal alloy The wire bonds (shown darker) run from bonding pads on theIeto the lead frame of the package The lead frame connections

go through to the Jcleads or gull-wings that subsequently are attached to the PCB The outer cover (labeled molding compound) completes the package 5.11.2Testing and Separation

IC designers include special test dice on the wafer that are subjected to all the same oxidation, etching, layering, and doping processes as the desired Ie These special test dice are monitored as much as possible after each of the processing steps described earlier At the very end of wafer production these test dice are put through an addi-tional series of computer-controlled tests in which fine, needlelike probes contact the aluminum bonding pads of the test dice If this first check shows that the processing parameters were within proper limits, then each die is tested for functionality Dice that need to be rejected are marked with an ink spot

After preliminary testing is completed, each die is separated from the wafer, usually by a diamond saw In this process the wafer is held down on a sticky sheet of Mylar and the diamond saw is used either to saw between the dice completely

Molding compound FigureS.30 Thedual-in-linepackage

(DIP) (from Manufacturing Engineering and Technology 3/ebyKalpakjian,

© 1995 Reprinted by permission

of Prentice-Hall, Inc., Upper Saddle River,NJ)

Bond wires

-tDie

Lead frame Spot plateDie-support paddl.