Handbook of algorithms for physical design automation part 71 potx

Crosstalk noise induced on a net greatly depends on how many aggressor nets switch and how their transitions are aligned among themselves, and in the case of delay noise, also with respe

C1

1 1

1 1

VThevenin

RThevenin

FIGURE 34.8 Aggressor driver model.

1 A small signal analysis of the gate can be performed, wherein a small noise voltage is applied at the output (over a 0 or Vdd bias as appropriate for the output state) and the output current is measured The ratio of the output current to the applied noise voltage then characterizes the holding resistance Note that, a conservative (larger) holding resistance value is obtained when the output is biased to the maximum expected noise level

2 The holding resistance of the driver gate can be computed from the channel resistances of individual transistors, by traversing all the conducting paths in the gate from output node to Vdd/ground [12] As the transistors in the conducting paths will be in the linear operating region, the transistor channel resistance in the linear region may be precharacterized as

a function of transistor width For a conservative analysis, the inputs of the gate must be asserted so as to obtain the maximum holding resistance

34.3.1.3 Switching Victim Driver Model (for Delay Noise)

A switching event on the victim affects the load seen by the aggressors and vice versa The change

in aggressor's effective loading owing to victim's switching has only secondary effects on the noise induced on the victim (effected through the change in aggressor's output slew), and so can be ignored For this reason, the aggressor driver model (discussed before) is created with no special consideration

of the victim's switching However, a driver model created thus cannot be used for a switching victim without incurring significant error, because the nonlinearity error is severe in the victim driver case The change in effective loading of victim owing to aggressors' switching and its impact on victim's delay is significant One way to compensate this error is to adjust the Thevenin resistance of the

driver model to a larger resistance, called the transient holding resistance, Rtr, which is calculated as below and illustrated in Figure 34.9 [7]

1 Obtain the noise waveform on the victim by performing a linear simulation using an initial (uncompensated) Thevenin model with the victim source grounded Aggressors are simu-lated individually and aligned appropriately to get the maximum peak noise From the noise

voltage waveform, Vn(t), compute the associated noise current waveform, In(t), using the

simplified model in Figure 34.9a: In = Vn/Rth+ CLOAD(∂Vn/∂t).

2 Perform nonlinear simulations of the victim driver gate with CLOAD, with and without the

added current source In(t) at the output, to obtain the noiseless transition V1 and noisy

transition V2, as shown in Figure 34.9b, and calculate the noise voltage response of the

nonlinear model, Vn, by subtracting the two nonlinear simulation results: Vn = V1− V2

(Figure 34.9c)

Vn V1

V1

In

Rth (Rtr )

(V ⬙n )

(V ⬘n )

(In )

(c)

V(t)

t

FIGURE 34.9 Characterization of transient Thevenin resistance: (a) Computation of noise current waveform

using a linear driver model, (b) Computation of noisy and nonnoisy output waveforms with a nonlinear driver model, and (c) Computation of noise voltage waveform for computing transient holding resistance

3 Finally, construct the equivalent linear model with the transient holding resistance Rtrby

replacing Rthin Figure 34.9a with Rtr Determine the value of Rtrsuch that the area under

the resulting noise voltage waveform Vnmatches the area under Vn It can be shown that

Rtr=
Vndt /
Indt.

34.3.1.4 Receiver Characterization

The loading of a receiver gate on a victim or an aggressor net is modeled as a fixed capacitance, averaged over the period of transition of its input A receiver gate is also characterized for its noise threshold values that define a local failure, or for noise propagation The noise threshold can

be as detailed as a noise rejection table, such as the one shown in Figure 34.7, or as simple as the static noise margin The noise propagation table, which gives the amount of output noise as a function of properties of input noise pulse (width and height), provides a very efficient mechanism for propagating noise to memory elements, without a need to perform an expensive simulation of a cascade of multiple stages of nets together Where a noise propagation table is available, the noise threshold can be computed on the fly when a local noise check is to be performed

The above discussed linear models do introduce some error, but their accuracy is acceptable

in most situations Situations requiring high accuracy may be simulated using accurate nonlinear models with SPICE level accuracy, using the worst-case conditions (e.g., alignment of aggressors) predicted through the linear model

34.3.2 CONSERVATIVEFILTERING OFNONRISKYNETS

Simulation with detailed models is unnecessary for a majority of nets as coupling noise is significant only in a small fraction of the nets We can use extremely simplified, but conservative, models to quickly identify potentially risky nets (a very small number usually) for detailed noise analysis It is

a common practice to use initially very simple driver and interconnection models and then gradually increase the details of the models and resimulate only those net clusters that fall with the simpler model A hierarchy of filters used by Ref [12] is shown in Figure 34.10 and described below as an example of this approach:

1 Conservative default driver models are used for victims and aggressors Lumped resistance-capacitance (RC) models are used for nets The lumped grounded capacitor of the victim net is placed at the driving end of the victim net and the lumped coupling capacitance at the receiver end of the net The resulting model is shown in Figure 34.10a In this case, the actual driver models and the distributed RC need not be loaded, and the noise can be computed analytically

Cg-path

Rpath

Cc

Cc

Cg

Rthev =Rdefault /N

Rthev =Rdefault /N

Rhold

Rhold

Rside

Rnet

v

v

Rside

Cg-path Cg-path = sum of grounded caps for source–sink path

Cg-agr

Cg-agr = grounded capacitance of aggressors

Cg-side = side branch capacitance

Cg-side

Rpath

Rpath,Rside = resistances of source–sink path and side branch

Cc

Cc , Cg = sum of coupling and grounded capacitance

Rthev = ||RThevenin

Rhold

Rhold = victim driver holding resistance

tThevenin v

(c)

N= number of aggressors

Rdefault , tdefault = default aggressor Thevinin model

FIGURE 34.10 Hierarchy of conservative noise filters.

2 The default victim driver is now replaced by the linear model of the actual driver and the victim net model is expanded to handle the main path to receiver and the side paths differently, as shown in Figure 34.10b

3 The default aggressor driver is now replaced by the actual aggressor linear drivers and the aggressor nets are expanded to include topology details, as shown in Figure 34.10c

34.4 REDUCING PESSIMISM IN CROSSTALK NOISE ANALYSIS

As described in the previous sections, practical noise analysis is performed in a static way that locally creates a worst-case scenario This results in an inherent pessimism in both functional and delay noise analyses Crosstalk noise induced on a net greatly depends on how many aggressor nets switch and how their transitions are aligned among themselves, and in the case of delay noise, also with respect to the victim transition An infinite number of switching scenarios is possible, depending

on input signal arrival times, process variation, environment parameters, and the logical operation

of the circuit Predicting the exact worst-case noise occurrence is very difficult Therefore, noise analysis tools compute a conservative estimate of possible induced noise Typically, it is assumed that all aggressor nets switch in the same direction at the worst alignment time However, many switching scenarios are prohibited in reality because of timing and logic correlations between the victim and aggressor signals In most cases, worst-case switching scenario does not occur due to such correlations, rendering the estimated noise from a naive analysis approach very pessimistic This pessimism, also called false noise, results in false functional and timing violations False noise results in wastage of precious design and silicon resources, which are spent for fixing nonexisting problems

In this section, we present an overview of approaches that utilize the timing and logical correla-tions to reduce false noise Note that this section presents techniques that make use of available design data to reduce pessimism Choosing a meaningful failure criterion during analysis, as explained in Section 34.2.2, is an orthogonal way to reduce false failures

34.4.1 LOGICCORRELATION

A pair of aggressor nets, which can each switch individually at a particular time point, may not be able to switch together at that time because of logic relationships in the circuit A simple example of such a situation is shown in Figure 34.11 Aggressor 1 and Aggressor 2 can never both be at logic 0, therefore they cannot have a falling transition at the same time

Any circuit has many logic correlations between its signals For noise analysis, these correlations can be considered as logic constraints prohibiting circuit nets to have some combinations of signals For false noise analysis, it is especially important to find that a group of aggressor nets are prohibited from having simultaneous rising or falling transition if the victim net is at the given voltage level Aggressor nets(a1, a2, , a n ) cannot switch simultaneously in the same direction if one of the two

signal combinations(a1= 1, a2= 1, , a n = 1) or (a1= 0, a2 = 0, , a n = 0) is prohibited when

the victim net is at the given state

In Refs [18–21], logic constraints between the pins of a gate are represented in disjunctive form, which coincides with the gate's characteristic equation For example, logic constraints for a two-input

AND gate with logic function x = a · b can be written as x · a · b + x · a + x · b = 0, which is exactly its characteristic function Here term x · a · b prohibits the combination (x = 0, a = 1, b = 1) In

Figure 34.12, a simple circuit and some of its logic constraints are shown

Such logic constraints are generated at gate or transistor level and propagated through the circuit with the purpose of generating nontrivial logic relations Logic correlations can be in the form of simple pairwise relations, such as simple logic implications (SLIs) [18] and new implications can be generated by forward and backward propagation of existing ones They can also be among multiple signals and resolution method can be used for propagation and generation of new relations [21]

In case of functional noise, after logic constraints generation, noise analysis is performed for every cluster for its respective noise type If the generated logic constraints are made of two variable relations only, a constraint graph is formed based on generated SLIs, and then maximum weighted independent set (MWIS) problem is solved [18] If the constraints involve many variables [21], then the constraint graph turns into a hypergraph Therefore, instead of the constraint graph, a reduced order binary decision diagram (ROBDD) of the noise cluster constraints is constructed Using the characteristic ROBDD of the noise cluster, the maximum noise of a given type is calculated by finding the maximum weighted set of the aggressors for which simultaneous switching of the same type is not prohibited In Figure 34.13, examples for a constraint graph and a constraint hypergraph are given

Aggressor 1

Aggressor 2

FIGURE 34.11 Example illustrating logic correlations.

a2

a4

a5

a3

a1 ·a4 ,a2 ·a4 , a2 ·a5 , a3 · a5

a1 ·a2 ·a4 , a2 ·a3 ·a5

v

v·a4 , v · a5 ,v·a4 · a5

FIGURE 34.12 Example circuit and its logic constraints.

(b) Constraint hypergraph

(a) Constraint graph 0.1

0.1 0.2

0.2

0.25

0.25

0.1

0.1

0.3

0.3

MWIS: {a1 , a2 , a5 } with weight

w = 0.65

MWIS: {a1 , a3 , a5 } with weight

w = 0.45

Hyperedges: {a1 , a2, a3 }, {a4 , a5 }, {a2 , a3 , a5 }

Edges: {a1 , a2 }, {a2 , a3 }, {a2 , a4 }, {a2 , a5 }, {a4 , a5 }

SLI constraints = {a1a2 , a2a3 ,

a2a4 , a2a5 , a4a5 }

Constraints: {a1a2a3 , a4a5 , a2a3a5 }

a2

a2

a1

a1

a4

a4

a5

a5

a3

a3

·

·

·

·

·

·

FIGURE 34.13 Constraint graph and constraint hypergraph for a noise cluster.

On the other hand, in case of delay noise analysis, a maximal set of aggressors needs to be selected such that the effect of noise is maximized globally and conservatively over several signal stages of a timing path As a result, logical constraints must be considered among a much larger set of signals (set of victims in the timing path and all their aggressors) than is necessary for functional analysis Because an aggressor can interact with multiple victim nets on a timing path and each interaction can contribute different amount of delay change relative to other aggressors, the problem of finding such

an aggressor set becomes difficult Despite the exponential complexity, enumerative traversal of the ROBDD of constraints is a reasonable approach for functional noise analysis, as each noise cluster is analyzed separately and a typical noise cluster consists of only about ten aggressor nets However, to achieve maximum possible pessimism reduction in delay noise analysis, it is necessary to consider all victim nets of an analyzed path and all their aggressor nets together As a result, one needs to compute MWIS from about 100 or more nets depending on the length of the timing path Thus, more

sophisticated techniques than direct enumeration are necessary In Ref [19], a branch-and-bound method as well as several heuristic techniques to address this need are provided

34.4.2 SWITCHING(TIMING) WINDOWS

In addition to logic correlations, the victim and the aggressor nets may have restrictions in the temporal domain because of signal delays in the circuit An activity window is defined as the interval from the earliest time to the latest time the net can switch Typically, activity windows are obtained from static timing analysis by propagating the early and the late arrival times of the circuit inputs (or sequential element outputs) along all paths to the outputs (or sequential element inputs) In functional noise, sensitivity windows are also useful and can be generated by performing backward propagation

of required times at circuit outputs or latch inputs A sensitivity window of a victim net is defined as the interval from the earliest required time to the latest required time, in other words the period of time when the net should stay stable for a correct logic value acquisition at a sequential element Timing windows can be used simply to decide whether an aggressor can induce noise on a victim by checking for the existence of overlap between the aggressor net timing window and the proper timing window of the victim net (activity window in delay noise and sensitivity window in functional noise) We will use Figure 34.14 to explain some concepts in timing window usage In case

of functional noise, suppose that A1, A2, and A3 are aggressor timing windows for rising transition

and V is victim sensitivity window A1, A3, and V overlap in region r1 A1, A2, and V overlap in region r2 In other words, A1 and A2 can induce noise together as well as A1 and A3, but not all three of them at the same time Scan line algorithms are usually used to determine the worst-feasible

aggressor set In case of delay noise, suppose that V is victim timing window for falling transition.

Same arguments apply as in functional noise analysis in determining the worst aggressor set that will impact the victim net delay the most Note that timing windows of nets can only be compared if they are in the same synchronous clock domain, otherwise nets in asynchronous clock domains can switch at any time relative to each other

Besides the above simple idea of using temporal relations in the circuit to reduce pessimism in crosstalk noise analysis, several ideas have been proposed to refine the usage of timing windows In Ref [15], instead of obtaining sensitivity windows by backward propagation of required times, noise windows (period of time when noise pulse can occur) are propagated and checked against required time window at the timing check points Because propagated noise pulses have windows associated with them, this method allows one to see whether the propagated and injected noise can occur at the same time In Ref [22], a more refined definition of a timing window is used where instead of the traditional continuous timing window, a set of discontinuous timing windows are used to more accurately represent possible switching events

In the case of delay noise, further refinement in timing window usage has been proposed by finding how much of an induced delay by an overlapping active aggressor should actually be taken

A1

A2

A3

r1

V

FIGURE 34.14 Timing windows for noise evaluation.

into account in the noise-aware static timing analysis traversal For example, in Figure 34.14, although

A1and A3may impact the delay of the victim net, this may not be important from a setup analysis point of view as long as the delay increase does not go beyond the latest arrival time of the victim net

(t l ) In this scenario, aggressor A2considered to be switching around time t lis the most likely one to impact the latest arrival time of the victim net Because the latest arrival time is the one that is finally checked against timing constraints at a path endpoint, this is sufficient for a noise-aware timing analysis in terms of delay increase [23] Timing windows depend on signal propagation delays and therefore depend on the injected noise On the other hand, the injected noise depends on the timing windows So we have a chicken and egg problem This problem is usually resolved by iterating timing window calculations and noise analysis until convergence

Note that the logic correlation techniques presented in the previous section are based on zero-delay implications These logic relations are valid only when the circuit has reached a stable state, i.e., at the beginning and end of a clock cycle However, when the circuit is in transition, it is possible that two aggressor nets can switch simultaneously even though their zero-delay logic relations would indicate that such switching is impossible This occurs when there are glitches in the circuit Methods

to handle this have been proposed where timing and logic information are propagated together in the form of timed logic representation [2]

34.5 NOISE AVOIDANCE, NOISE-AWARE DESIGN, AND NOISE REPAIR

In previous sections, we talked about crosstalk noise phenomenon, accurate and efficient analysis techniques, as well as pessimism reduction techniques to prevent false failures In this section, we turn

to design implications of crosstalk noise and present techniques and methodology to be incorporated

in the design flow with the purpose of early detection and avoidance of noise problems, as well as postroute repair approaches

As mentioned in Section 34.2, several approaches are available to avoid and reduce crosstalk noise In literature, fast crosstalk noise estimation methods [24,25] have been developed, which can

be used as metrics to evaluate what-if scenarios as well as study the effectiveness of noise reduction approaches [26] Also, extensive work has been carried out in noise prevention, noise-aware design, and noise repair [27–35] In what follows, we present some widely used practical approaches

34.5.1 NOISEPREVENTION ANDNOISE-AWAREDESIGN

Modern design flows have adopted crosstalk noise prevention and noise-aware design techniques such that this issue is addressed early in the design cycle In this section, we look at some of these methods

34.5.1.1 Slew Control

Signal slope on a net is a good indicator of how strongly the net is driven compared to its RC loading characteristics Strongly driven nets not only become more noise immune but also become stronger aggressors Slew control targets to balance this throughout the design, preventing very weak victims and very strong aggressors This is a noise avoidance technique employed early in the design cycle, during synthesis and placement Although applying slew optimization globally results in stronger aggressor drivers, its benefit on overall noise because of the prevention of unacceptably weak victim drivers is greater [30]

In practice, a faster slew constraint produces a better design for noise, both in number of functional and delay noise violations, as well as the severity of worst-path delay slack Balancing the slew rates throughout the design reduces the possibility of strong aggressors injecting high amounts of noise into weak victims, thus reducing functional noise failures On the other hand, delay variation owing

to crosstalk noise, in a first-order approximation, is proportional to t · (V /Vdd), where t is the

transition time and Vn is the injected noise height Therefore, improving slew rate also helps to reduce crosstalk-induced delay variation Achieving faster slew may increase the layout area and the power consumption of the design, as buffers are inserted to meet the target slew rate It has been reported that the increase in power consumption because of the inserted buffers is minimal as a result

of improved slew rates, which help reduce the short circuit power [30] These effects should be taken into consideration as constraints during design decision process

34.5.1.2 Congestion Minimization

Coupling capacitance is the factor that crosstalk noise is most sensitive to [26] and therefore reducing coupling is a very effective noise prevention/repair method As crosstalk capacitance and spacing between nets are closely correlated, reducing routing congestion in a design helps reduce noise This

is an avoidance method applied during placement and routing stages of the design cycle

34.5.1.3 Noise-Aware Routing (Spacing, Shielding, Layer Assignment)

A router can use simple crosstalk noise estimation methods as mentioned earlier to be noise-aware Capacitances and resistances in the noise estimation model can be calculated using per unit length parasitic information and wirelength, wire width, spacing to neighbor nets, and coupling length (distance where two wires run parallel to each other) Routers can try to optimize parameters under their control (wirelengths and coupling lengths) using techniques available to them such as spacing, shielding, layer/track assignment, etc [31–37]

34.5.2 POSTROUTENOISEREPAIR

Noise prevention methods presented in Section 34.5.1 help with the overall crosstalk noise quality

of the design In later stages of the design cycle, i.e., after detailed routing, flexibility to make modifications is reduced and targeted actions are required to handle remaining functional and timing failures owing to crosstalk noise

34.5.2.1 Gate Sizing, Buffer Insertion

Even after employing the prevention and noise-aware design techniques given in Section 34.5.1, some failures remain in postroute stage It has been shown that the crosstalk noise induced functional and timing failures in a design usually have common causes and attacking functional noise problems first results in a more straightforward noise repair approach [30]

The most commonly used techniques in postroute noise repair are gate sizing, buffer insertion, net spacing, and shielding There are benefits and drawbacks with all these approaches To reduce crosstalk noise on a victim net, its driving gate's strength can be increased (i.e., same functionality with bigger equivalent transistor widths) However, this also causes the victim net to be a stronger aggressor on its neighbors, causing new problems to show up while fixing existing ones Even worse, a sequence of gate sizing actions can become cyclic involving few nets and thus prevent the convergence of the repair actions Algorithms have been developed to identify and address such cyclic effects such that the sizing is very effective and the convergence is fast [29] Buffer insertion helps both by dividing a net into two separate nets thus reducing coupling, and by providing additional drive strength if necessary However, buffer insertion is more intrusive in the design than gate sizing

It is a common practice to place dummy buffers in the design at early stages, which can then be used for such repair purposes Net spacing on the other hand reduces coupling capacitance between particularly targeted nets However, in already congested routing situations, this technique may result

in dense routing regions to shift from one area of the design to another resulting in new failures Net shielding is another effective method to address crosstalk noise issues This method places a power (Vdd or ground) net next to a crosstalk noise problematic net, virtually eliminating its coupling

capacitance As with spacing, this technique may not be feasible depending on the availability of power grid and signal routing resources

Hierarchical properties of the design being worked on also play a role in deciding which noise repair techniques will be most effective Routing changes are to be preferred over sizing and buffering for fixing noise at the system-on-chip (SoC) integration stage This assumes that all SoC blocks are timing clean, and long global nets are already buffered in the previous timing optimization phase Although both sizing and buffering can be used for block level noise fixing, driver sizing is not to

be preferred at the chip level because the drivers reside in the SoC blocks that are being integrated However, gates in the sea of gates can be resized at the chip level, because they are legalized and routed at the chip level

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