9.8 CONCLUSION In this chapter, we have introduced two slicing floorplan representations, that is, slicing tree and Polish expression, on which many existing slicing floorplan design/opt
Trang 1182 Handbook of Algorithms for Physical Design Automation
w d
h
(x,y,z) (c)
1 2
3 4
5
X X Y
Z
(d)
X
2
4
4
1
1
5
5
3
Parent links
Indices
FIGURE 9.15 (a) 3D slicing floorplan with five modules (b) Corresponding slicing tree (c) Dimensions of
a 3D block (d) Static array
where n is the number of modules Each of the first n− 1 elements in the array represents an internal
node, and the first element always represents the root of the tree The last n elements represent the leaves Each element of the array is associated with a ten-tuple (t, p, l, r, x, y, z, w, d, h) The t
is the tag information and its value is X, Y , or Z for each internal node and a module name for a leaf p, I, and r denote the element indices in the array for the parent, the left child, and the right child of a node, respectively The x, y, z, w, d, h are the dimensional information of a module or a
subfloorplan, and(x, y, z) is called the base point (see Figure 9.15c) Figure 9.15d is the static array
for the slicing tree shown in Figure 9.15b, where only the parent link of each element is drawn for simplicity Given the static array of a slicing tree, the position of each module and the dimensions
of the corresponding floorplan can be calculated by a recursive procedure starting from the root Two kinds of moves, exchange and rotation, are used during the annealing process for generating neighboring solutions An exchange move randomly chooses two subtrees and swaps them; as a result, the two corresponding elements in the static array will be updated accordingly On the other hand, a
rotation move randomly selects a subtree and rotates the corresponding subfloorplan along x-, y-, or z-axis; as a result, the elements of the static array corresponding to the internal nodes contained in the
subtree will be updated accordingly It can be proved that the two neighborhood moves are complete
in the sense that each slicing tree can be reached from another one via at most 10n− 6 moves This 3D floorplanner can be specialized to solve the 2D problem as well, and according to Ref [28], it is able to produce 2D slicing floorplans with the smallest areas for the two largest MCNC benchmarks, ami33 and ami49, among all 2D slicing and nonslicing floorplanning algorithms ever reported in the literature Besides, this 3D floorplanner can be extended to handle various types of placement constraints and thermal distribution
9.8 CONCLUSION
In this chapter, we have introduced two slicing floorplan representations, that is, slicing tree and Polish expression, on which many existing slicing floorplan design/optimization algorithms are based We have presented efficient/effective area and power optimization algorithms for slicing floorplans These optimization algorithms are typically embedded into a slicing floorplanner We have discussed the problem of slicing floorplan design with or without placement constraints, and highlighted existing solutions Finally we have described some more recent results in slicing floorplans for FPGAs
Trang 2Slicing Floorplans 183
and 3D ICs, in addition to the mathematical analysis on area upper bound and the completeness of slicing tree representation
Before concluding this chapter, we would like to point out that since 1970s, slicing floorplans have been an active research topic, and therefore it is very difficult to discuss all existing solutions
of this area in a single chapter Instead, we have chosen to present the results, including the most recent ones in the past ten years, which we think will interest readers the most
REFERENCES
1 R H J M Otten Automatic floorplan design Proceedings of Design Automation Conference, pp 261–267,
1982
2 D F Wong and C L Liu A new algorithm for floorplan design Proceedings of Design Automation Conference, Las Vegas, Nevada, pp 101–107, 1986.
3 L J Stockmeyer Optimal orientation of cells in slicing floorplan designs Information and Control,
57(2):91–101, 1983
4 W Shi An Optimal algorithm for area minimization of slicing floorplans Proceedings of International Conference on Computer-Aided Design, San Jose, California, pp 480–484, 1995.
5 R H J M Otten Efficient floorplan optimization Proceedings of International Conference on Computer Design, Las Vegas, Nevada, pp 499–502, 1983.
6 G Zimmermann A new area and shape function estimation technique for VLSI layouts Proceedings of Design Automation Conference, Atlantic City, New Jersey, pp 60–65, 1988.
7 K.-Y Chao and D F Wong Floorplanning for low power designs Proceedings of International Symposium
on Circuits and Systems, Seattle, Washington, pp 45–48, 1995.
8 R E Tarjan Data Structures and Network Algorithms SIAM Press, Philadelphia, Pennsylvania, 1983.
9 T Corman, C E Leiserson, and R Rivest Introduction to Algorithms MIT Press, Cambridge,
Massachu-setts, 1990
10 U Lauther A min-cut placement algorithm for general cell assemblies based on a graph representation
Proceedings of Design Automation Conference, San Diego, California, pp 1–10, 1979.
11 D P La Potin and S W Director Mason: A global floorplanning approach for VLSI design IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, CAD-5(4):477–489, 1986.
12 G J Wipfler, M Wiesel, and D A Mlynski A combined force and cut algorithm for hierarchical VLSI
layout Proceedings of Design Automation Conference, pp 671–677, 1982.
13 B W Kernighan and S Lin An efficient heuristic procedure for partitioning graphs Bell System Technical Journal, 49(2):291–307, 1970.
14 D G Schweikert and B W Kernighan A proper model for the partitioning of electrical circuits Proceedings
of Design Automation Workshop, pp 56–62, 1972.
15 C M Fiduccia and R M Mattheyses A linear-time heuristic for improving network partitions Proceedings
of Design Automation Conference, pp 175–181, 1982.
16 B Quinn A force directed component placement procedure for printed circuit boards IEEE Transactions
on Circuits and Systems, CAS-26(6):377–388, 1979.
17 S Kirkpatrick, C D Gelatt, and M P Vecchi Optimization by simulated annealing Science, 220, 671–680,
1983
18 F Y Young and D F Wong Slicing floorplans with boundary constraints Proceedings of Asia and South Pacific Design Automation Conference, Hong Kong, pp 17–20, 1999.
19 E.-C Liu, T.-H Lin, and T.-C Wang On accelerating slicing floorplan design with boundary constraints
Proceedings of International Symposium on Circuits and Systems, Geneva, Switzerland, pp III-339–III-402,
2000
20 E.-C Liu, M.-S Lin, J Lai, and T.-C Wang Slicing floorplan design with boundary-constrained modules
Proceedings of International Symposium on Physical Design, Sonoma County, California, pp 124–129,
2001
21 F Y Young and D F Wong Slicing floorplans with range constraints Proceedings of International Symposium on Physical Design, Monterey, California, pp 97–102, 1999.
22 F Y Young, H H Yang, and D F Wong On extending slicing foorplans to handle L/T-shaped modules and
abutment constraints IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems,
20(6):800–807, 2001
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23 W S Yuen and F Y Young Slicing floorplan with clustering constraints Proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp 503–508, 2001.
24 F Y Young and D F Wong Slicing floorplans with pre-placed modules Proceedings of International Conference on Computer-Aided Design, San Jose, California, pp 252–258, 1998.
25 F Y Young and D F Wong How good are slicing floorplans? Proceedings of International Symposium on Physical Design, Napa Valley, California, pp 144–149, 1997.
26 M Lai and D F Wong Slicing tree is a complete floorplan representation Proceedings of Design, Automation, and Test in Europe, Munich, Germany, pp 228–232, 2001.
27 L Cheng and D F Wong Floorplan design for multi-million gate FPGAs Proceedings of International Conference on Computer-Aided Design, San Jose, California, pp 292–299, 2004.
28 L Cheng, L Deng, and D F Wong Floorplanning for 3-D VLSI design Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, China, pp 405–411, 2005.
29 P Guo, C.-K Cheng, and T Yoshimura An O-Tree representation of non-slicing floorplan and its
applications Proceedings of Design Automation Conference, New Orleans, Louisiana, pp 268–273, 1999.
30 J M Emmert and D Bhatia A methodology for fast FPGA floorplanning Proceedings of International Symposium on Field Programmable Gate Arrays, Monterey, California, pp 47–56, 1999.
31 Xilinx Inc http://www.xilinx.com
32 K Banerjee, S J Souri, P Kapur, and K C Saraswat 3-D ICs: A novel chip design for improving
deep submicrometer interconnect performance and systems-on-chip integration Proceedings of the IEEE,
89(5):602–633, 2001
Trang 410 Floorplan Representations
Evangeline F.Y Young
CONTENTS
10.1 Introduction 185
10.2 Corner Block List 187
10.2.1 Corner Block 187
10.2.2 Definition of Corner Block List 188
10.2.3 Transformation between Corner Block List and Floorplan 189
10.2.4 Floorplanning Algorithm 189
10.2.5 Extended Corner Block List Structure 189
10.3 Q-Sequence 191
10.3.1 Extended Q-Sequence 192
10.3.1.1 New Move Based on Parenthesis Constraint Tree 192
10.4 Twin Binary Trees 194
10.5 Twin Binary Sequences 196
10.6 Placement Constraints in Floorplan Design 199
10.7 Concluding Remarks 201
References 201
10.1 INTRODUCTION
A floorplan representation is a data structure that captures the relative positions of the rooms in
a dissection of a rectangular region It differs from a packing representation, which captures the relative positions of the blocks to be packed into a rectangular region In this chapter, we will study different rectangular dissection representations (with the exception of the slicing representation which was discussed in the last chapter) There are several graph-based representations for rectangular dissections in the early floorplanning literature, e.g., polar graph, neighborhood graphs, etc In this chapter, we will only focus on recent representations for floorplans, which are mainly string-based Unlike the slicing representation, these representations can characterize any dissection of a rectangle into rooms We begin by formally defining a floorplan (which is also often referred to as a mosaic floorplan in the literature) A rectangular dissection is a floorplan if and only if it observes the following three properties:
1 Each room is assigned exactly one block
2 The internal line segments (segs) of the dissection are only permitted to form T-junctions (Figure 10.1) “+”-shaped junctions, where two distinct T-junctions meet at the same point, are considered to be degenerate The representational power of floorplans is not impacted
by this because the two T-junctions can be separated by sliding the noncrossing segment of one of the two T-junctions by a very small distance (Figure 10.2)
185
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B A
C
E
F
A
C
G D
Mosaic floorplan with nonslicing structure
Mosaic floorplan with slicing structure
D B
FIGURE 10.1 Examples of floorplans, showing (a) a mosaic floorplan with slicing structure and (b) a mosaic
floorplan with nonslicing structure
3 The topology is defined in terms of room–seg adjacency relationships rather than room– room adjacency relationships The distinction between the two is described below
A floorplan can be defined in terms of relationships between adjacent rooms (i.e., rooms whose boundaries share a line segment) or in terms of adjacency relationships between a room and a seg (one of the boundaries of a room is the seg) In either case, it is necessary to specify the nature of
the adjacency relationship (e.g., room A is to the left of room B or room B is above segment s in
Figure 10.3) Two floorplans are equivalent with respect to the room–seg relation if and only if it is possible to label the rooms and the segments in such a way that the two sets of room–seg relations are identical Similarly, two floorplans are equivalent with respect to the room–room relationship if and only if there is a labeling of the rooms such that the two sets of room–room relations are identical Figure 10.3 shows two floorplans that are identical with respect to the room–seg relationship, but
Sliding slightly one T-junction horizontally
Sliding slightly one T-junction vertically
Two T-junctions meet
at the same point
Or
FIGURE 10.2 Degenerated case modeled by slightly moved T-junctions.
A
B
C
E
D
v
w s
t
D B
E C
A
v
t
FIGURE 10.3 Room–seg relation and room–room relation.
Trang 6Floorplan Representations 187
not with respect to the room–room relationship In this chapter, floorplans are defined with respect
to the room–seg relation
10.2 CORNER BLOCK LIST
The corner block list (CBL) [1] was one of the first representations proposed for the class of mosaic floorplans CBL is a topological representation and the topological relationship between two rooms
as described by a CBL is independent of the modules contained in those rooms We will see later
in this section that the time complexity to transform a CBL to a placement is O (n) where n is the number of rooms It just takes n (3 + lg n) bits to describe a packing in CBL and the size of the solution space is O (n!2 3n−3).
In a mosaic floorplan F, the room*in the top-right corner is called the corner block The orientation
for a corner block B is defined according to the T-junction at the bottom-left corner of the room containing B There are only two kinds of T-junctions, a T rotated by 90◦anticlockwise or a T rotated
by 180◦ In the first case, B is said to be vertically oriented and is denoted by a “0” bit For the other case, B is said to be horizontally oriented and is denoted by a “1” bit The two possible orientations
of a corner block are illustrated in Figure 10.4 To obtain the CBL of a floorplan, or to construct the floorplan from a CBL, the concepts of deleting and inserting a corner block are needed
If the corner block B of a given mosaic floorplan F is vertically oriented, B is deleted by sliding the bottom segment of B up along its left segment until it reaches the upper boundary of F Similarly, if B
is horizontally oriented, it is deleted by sliding its left segment along its bottom segment until reaching
the right boundary of F An example to illustrate this deletion process is shown in Figure 10.5 It is
FIGURE 10.4 Different orientations of a corner block.
C
F
G
H
D
H F E C G
F E C G
Delete a vertically oriented corner block
Delete a horizontally oriented corner block E
FIGURE 10.5 Deletion of the corner block in a mosaic floorplan.
* The term “block” is a physical entity with a width and a height, whereas a “room” is a topological entity without specified dimensions We use the two terms interchangeably in this section to be consistent with the original CBL paper.
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D
B
C
A
E C
B A
D
A
B C E D
F
Insert a horizontally oriented corner block (covering one T-junction)
Insert a vertically oriented corner block (covering two T-junctions)
FIGURE 10.6 Insertion of a corner block to a mosaic floorplan.
not difficult to see that a mosaic floorplan will remain mosaic after deleting the corner block The
corner block insertion process is the reverse of the deletion process To insert a new corner block B
to a mosaic floorplan F horizontally, a vertical segment (covering a certain number of 270◦rotated
T-junctions) at the right boundary of F is pushed to the left to create a room at the top-right corner
of F for B Similarly, to insert a new corner block Bto a mosaic floorplan F vertically, a horizontal
segment (covering a certain number of 0◦rotated T-junctions) at the upper boundary of F is pushed downward to create a room at the top-right corner of F for B An example to illustrate this insertion process is shown in Figure 10.6
10.2.2 DEFINITION OFCORNERBLOCKLIST
The CBL of a mosaic floorplan F containing n blocks is a three-tuple (S, L, T) where S = s1· · · s nis a
sequence of the block names, L = l1· · · l n−1is a bit string denoting the corner block orientations, and
T = t1t2· · · t n−1is a bit string denoting some T-junction information The CBL of F is constructed
by recursively deleting corner blocks from F until only one block is left We define a sequence of mosaic floorplans F i , i = 0, , n − 1, where F0 = F and F i+1is obtained from F i by deleting the
corner block in F i Then, s i is the corner block of F n −i ; l i is a bit denoting the orientation of s i+1
(“0” [“1”] for a vertically [horizontally] oriented block); and t i is a sequence of k i“1”s followed by
a “0,” where k i is the number of T-junctions covered by the bottom (left) segment of the vertically
(horizontally) oriented corner block of s i+1 Notice that F n−1has only one block and the orientation
of or the number of T-junctions covered by it is undefined, so the indices i of l i and t ionly run from
1 to n− 1 An example of the CBL of a mosaic floorplan is shown in Figure 10.7
It takes no more than n (3 + lg n) bits to represent a floorplan by a CBL where n × lg n bits are used to record the block names in the list S, n− 1 bits are used to record the orientations in the
list L and no more than 2n − 1 bits are used to record the T-junction information in the list T.
D C
B
L= (10110)
T= (01001010)
FIGURE 10.7 Corner block list of a mosaic floorplan.
Trang 8Floorplan Representations 189
Transformation from floorplan to CBL
1 While there is a corner block B, repeat
2 Delete B.
3 If B is not the last block, record (B, orientation, T-subsequence).
4 Add the last block to the block name list and concatenate all records in a reversed order to obtain the lists(S, L, T).
FIGURE 10.8 Transformation from floorplan to CBL.
Transformation from CBL to floorplan
1 Initialize the floorplan with block S[1].
2 For i = 2 to n do
3 Add block S [i] to the floorplan with orientation L[i − 1], covering a number of
T-junctions according to list T
4 Ifthe number of T-junctions required to be covered is more than the number of
T-junctions available, report error and exit
FIGURE 10.9 Transformation from CBL to floorplan.
10.2.3 TRANSFORMATION BETWEENCORNERBLOCKLIST ANDFLOORPLAN
The linear-time transformations between CBL and floorplan are described in Figures 10.8 and 10.9
A drawback of CBL is that an arbitrary three-tuple(S, L, T), where S is a permutation of n block names, L is an n − 1-bit string, and T is a bit string starting and ending with “0”s and having n − 1
“0”s in total, may not correspond to a floorplan, because of the constraints on the composition of the
list T
This CBL representation can be used in search-based optimization technique like simulated annealing Neighboring solutions can be generated by the following moves:
1 Randomly exchange two blocks in S
2 Randomly toggle a bit in L
3 Randomly toggle a bit in T
4 Randomly pick a block and rotate it by 90◦, 180◦, or 270◦
5 Randomly pick a soft block and change its shape
Notice that the second and the third move may result in an infeasible CBL, i.e., one that does not correspond to any floorplan Therefore, checking and appropriate correction steps are needed
10.2.5 EXTENDEDCORNERBLOCKLISTSTRUCTURE
The extended CBL, ECBLλ, was proposed by Zhou et al [2] to represent general floorplans that may include empty rooms Like the CBL, ECBLλrepresents a rectangular dissection and assigns blocks
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Transformation from floorplan to ECBL
1 Insert a false block to each empty room
2 While there is a corner block B, repeat
3 Delete B.
4 If B is not a false block, record (B, orientation, T-subsequence),
elserecord (false block, orientation, T-subsequence)
5 Add the last block to the block name list and concatenate all records in a reversed
order to obtain the lists(S, L, T).
FIGURE 10.10 Transformation from floorplan to ECBL.
Transformation from ECBL to floorplan
1 Initialize the floorplan with block S[1].
2 For i = 2 to λn do
3 Ifall real blocks are added already, output the floorplan and exit,
4 else
5 Add block S [i] to the floorplan with orientation L[i − 1] covering a number of
T-junctions according to list T
6 Ifthe number of T-junctions required to be covered is more than the number of
T-junctions available, report error and exit
FIGURE 10.11 Transformation from ECBL to floorplan.
to rooms, but it contains more rooms than there are blocks, leaving some of the rooms empty In block assignment, a false block of zero width and height is assigned to an empty room An extended CBL, ECBLλ, is defined as follows:
Definition 1 Given n blocks, an extended corner block list with an extending factor λ, denoted by
ECBLλ , is a corner block list (S, L, T) of a floorplan with λn rooms, of which λn − n rooms are empty and occupied by false blocks and the remaining n rooms hold the n given blocks.
The transformation algorithms between floorplan and ECBL are updated to account for the intro-duction of false blocks (Figures 10.10 and 10.11) Similar to the analysis of CBL, the complexities of
these algorithms are both O (λn), and the number of combinations of ECBL λ is O (C n
λn n!23λn−4 ) There is an additional factor of C n
λn in the total number of combinations because there are C n
λn
ways to select n rooms from λn rooms to accommodate the n real blocks.
The solution space of ECBLλis guaranteed to contain the optimal solution whenλ = n It can
be shown that the bounded sliceline grid (a packing representation discussed in the next chapter) BSGn×ncan be represented by an ECBLn, i.e.,λ is set to n From the optimum solution theorem of
bounded sliceline grids, there exists a BSGn×n-based packing corresponding to the optimal solution,
so the solution space of ECBLn must also contain the optimal solution However, settingλ to n
will significantly increase the size of the solution space and the complexities of the transformation algorithms from linear to quadratic Fortunately, it has been shown experimentally that fairly good results can be obtained by settingλ to a real number constant in the range [1.5,3], which agrees with
a fact proven later that(n − 2√n ) empty rooms are enough to generate any packing.
Trang 10Floorplan Representations 191 10.3 Q-SEQUENCE
A new data structure called the Quarter-state sequence (abbreviated as Q-sequence) was proposed
by Sakanushi et al [3,4] to represent a floorplan A Q-sequence is a string of room labels and two
positional symbols with a total length of 3n where n is the number of rooms Both encoding and
decoding of the Q-sequence representation can be done in linear time
To construct the Q-sequence of a floorplan, the following terms are defined A room is called
the tail room if it lies at the bottom-right corner of the floorplan A room r that is not a tail room
has a bottom-right corner, which is either a 180◦ or a 270◦ rotated T-junction In either case, the
noncrossing segment of the T-junction is called the prime seg of r If the prime seg l of a room r is vertical (horizontal), the rooms that touch l from the right (below) are called the associated rooms
of r, and the topmost (leftmost) associated room is called the next room of r The Q-state of room r
is a string starting with the room label r followed by n r “R”s (“B”s) if the prime seg of r is vertical (horizontal), where n r is the number of associated rooms of r The subQ-sequence Y is constructed
by concatenating the Q-states of all the rooms in the order of r1, r2, , r n , where r1is the room at
the top-left corner of the packing, and r i+1 is the next room of r i , for i = 1, , n − 1 We define string X as consisting of p “R”s with q “B”s, where p and q are the numbers of rooms touching the
left-wall and the top-wall of the whole floorplan The final Q-sequence is obtained by concatenating
X with the subQ-sequence Y An example is shown in Figure 10.12 Henceforth, we assume that the rooms are always labeled from 1 to n in the Q-sequence (i.e., r i = i).
Given a Q-sequence Q, we can obtain an RQ-sequence by deleting all the “B”s and replacing
every “R” by an open parenthesis and every room label by a close parenthesis We can construct
a BQ-sequence similarly by interchanging the roles of “B” and “R” There are two necessary and sufficient properties:
1 Single: The subsequence of Q between any two rooms contains a string with at least one
“R” or at least one “B.”
2 Parenthesis: The RQ-sequence and BQ-sequence of Q are well formed.
It can be shown that the number F (n) of distinct Q-sequences for n blocks is upper bounded by
from the sequence and floorplan realization can be done in linear time A decoding algorithm will
be given in the next section Besides, boundary constraint can also be handled efficiently by using the Q-sequence representation
6
2 1
3
5 4
RRBB1RR2BB3BB4R5R6
FIGURE 10.12 Example of the Q-sequence representation.