Handbook of algorithms for physical design automation part 30 potx

In ISPD’04, Proceedings of the International Symposium on Physical Design 2004, pp.. In ICCAD ’04, Proceedings of the International Conference on Computer-Aided Design 2004, pp... Becaus

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Part IV

Placement

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Problem Formulation

Gi-Joon Nam and Paul G Villarrubia

CONTENTS

14.1 Introduction 277

14.2 Problem Formulation 278

14.3 Modern Issues in Placement 281

14.4 General Approaches to Placement 285

References 286

14.1 INTRODUCTION

Placement is a physical synthesis task that transforms a block/gate/transistor-level netlist into an actual layout for timing convergence It is a crucial step that assembles the basic building blocks of logic netlist and establishes the overall timing characteristic of a design by determining exact locations

of circuit elements within a given region In modern VLSI designs, the size of chip becomes larger and the required clock frequency keeps increasing due to higher performance and more complex functional requirements on a single chip Moreover, with aggressive technology scaling into the deep submicron (DSM) era, interconnect delays become the dominant factor for overall chip performance Because the locations of circuit elements and corresponding interconnect delays are determined during the placement stage, it has significant impact on the final performance of the design Moreover,

if a design is placed poorly, it is virtually impossible to close timing, no matter how much other physical synthesis and routing optimizations are applied to it Hence, placement is regarded as one

of the most important and effective optimization techniques in the physical synthesis flow Today, placement is no longer a point tool in modern timing closure flow [1] Significant portions of logic and physical optimization algorithms have to interact with placement to improve timing of a design and to guarantee a legal placement solution after optimizations Consequently, most industrial and academic physical synthesis tools are developed around a placement infrastructure

The typical objective function of placement is to minimize total wirelength of a design This

is because wirelength can be easily modeled and serve as a good first-order approximation of real objective functions such as timing, power, and routability of a design There also exist various forms of wirelength For example, quadratic wirelength, linear wirelength, or some approximation

of linear wirelength are popular models that are employed in many placement tools Recently, Steiner wirelength, which is considered as the most accurate estimator of the routed wirelength, was also used as the placement objective function in some academic placement tools Whatever wirelength form is used, producing a good placement wirelength is critical for timing closure of modern designs because the wirelength directly affects the interconnect delays of electrical signals The wirelength also affects the routability of a design, which is another important aspect of physical synthesis The routing is performed right after the placement and there is no point in producing an unroutable placement solution

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14.2 PROBLEM FORMULATION

Because the primary task of placement is to determine the locations of circuit elements in a design, the

placement region P needs to be defined first Usually, a placement region is a rectangle area defined

by coordinates (xlow, ylow, xhigh, yhigh) This is not a necessity for modern placement and actually

a wider variety of placement regions such as L-shapes or T-shapes have been observed recently in special problem instances such as region constraint∗(movebound) placement However, for global placement, a rectangular placement region is still the norm The circuit netlist is represented as a

graph G = (V, E), where V is a set of circuit elements in a design and E is a set of connections (nets) among them The vertex set V consists of two disjoint subsets, MV and FV where MV/FV represents

a set of movable/fixed circuit elements respectively For each v ∈ FV, the location (x, y) of v is already determined and the placement should not change them The location of each v∈ MV needs

to be determined by placement and their locations must fall within the given placement region P Each net e i ∈ E is a hyper-edge and conveniently represented as a subset of circuit elements, which are electrically connected each other, i.e., e i = {v i1 , v i2, ., v im }, ∀v ij ∈ V Hence, |e|, the cardinality of net e, denotes the number of pins on the net Figure 14.1 shows a simple example of

a placement problem The big rectangle in Figure 14.1a represents a placement region P and each circle represents a movable circuit element to be placed within P Small rectangles on the boundary

of the placement region are I/O pins that are considered as fixed circuit elements These movable and fixed circuit elements are connected to each other by nets The goal of placement is to find a legal location for each movable circuit element while minimizing the given objective function In this example, only one movable circuit element (circle) is assumed to be placed within a placement grid (slot) that is defined by dotted lines

Some class of global placement algorithms, such as a partitioning-based algorithms or simulated annealing, is effective in directly handling hyper-edge nets Others, particularly analytical placement algorithms, require a hyper-edge to be transformed into a set of clique edges For example, quadratic optimization-based analytic placement needs a clique-edge model to solve a symmetric positive definite linear system equation A net usually has a source-pin (driver) and multiple sink pins, which make it a directed hyper-edge.†The current state-of-the-art global placement algorithms still ignore

the directions of the hyper-edges and treat a netlist graph G as a undirected graph However, the

directions of hyper-edges can be utilized to better handle certain types of nets A high fan-out clock

(b) (a)

FIGURE 14.1 Simple placement instance (a) Before placement and (b) after placement.

∗ More discussion of region constraints and movebounds are provided in Section 14.3.

† There exists a bidirectional net such as a bus signal In this case, one pin can be considered as a source pin while the others are regarded as sink pins.

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FIGURE 14.2 Net model: hyper-edge model, clique-edge model, and star (a) Original net with a driver and

four sinks, (b) hyper-edge, (c) clique edge, and (d) star

net, for example, can be better placed by representing it as a star model with a source pin in the center Figure 14.2 shows a hyper-edge net and corresponding clique/star models A more detailed circuit netlist representation discussion can be found in Chapter 7

The typical objective function of a placement is the sum of net wirelengths, i.e.,WL(e), ∀e ∈ E.

For a given net, different types of wirelength WL(e) can be measured A net half-perimeter (NHP)

wirelength model (Figure 14.3b) measures the smallest bounding box, which surrounds all sinks of the net A minimum spanning tree (MST) model (Figure 14.3c) calculates a minimum tree length, which connects all pins of the net However, only a direct connection of a pair of pins on the net is considered to build a tree A Steiner tree (ST) model (Figure 14.3d) is also a tree connecting all pins

of the net, but any arbitrary point (not pin) in a tree segment is also considered to branch off other tree segments to reduce the tree length Therefore Steiner tree length is always equal to or better than that of MST Because the routes of nets are implemented with horizontal and vertical metal layers,∗

a rectilinear minimum spanning tree or rectilinear Steiner tree is a more accurate estimation of real net wirelengths and these rectilinear versions of MST and ST are popularly used in physical design research (see Chapter 24 for more detailed discussion on MST and ST) Simple NHP bounding box

is the most popular model used in placement today simply because it is efficient to compute and also it is a good approximation of routed wirelength for the majority of nets For some difficult nets, Steiner tree wirelength might be necessary to optimize for better routability, but the number of these nets is marginal in most cases

A net e can have a weight w (e) associated with it In a timing-driven placement (Chapter 21), a

net is assigned a weight based on its timing criticality The more critical a net is for timing closure, the higher the weight assigned to the net so that a placement algorithm can try harder to reduce its wirelength leading to less signal delay When a net weight is present, the common objective function

of a placement is the weighted sum of wirelengths, i.e.,w(e)∗WL(e), ∀e ∈ E.

∗ X-route with 45◦angle metal layer is available in advanced technology However, horizontal and vertical metal layers are still more common as of today.

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FIGURE 14.3 Net wirelength model: NHP, MST, and ST Net model is drawn in dotted line (a) Routed net

with a driver and four sinks, (b) NHP model, (c) rectilinear MST model, and (d) rectilinear ST model

Suppose that there are n movable circuit elements [v1, v2, , v n ] and m nets [e1, e2, , e m] in

a given netlist graph G = (V, E), i.e., |V| = n and |E| = m Let each movable circuit element

v i’s location be(x i , y i ) Then, the placement problem can be formulated as follows [2–4]: Given a

placement region P with width W and height H, a netlist graph G = (V, E), and objective function

f (V, E), find the location (x i , y i ) of each v i ∈ MV such that (1) each v i ∈ MV is placed completely

within P, (2) no overlap exists between any pair of (v i , v j ), ∀v i , v j ∈ V, and (3) the objective function

f (V, E) is minimized In the case of the standard cell placement problem, an additional circuit row

constraint must be honored and each standard cell must be placed within a circuit row boundary The intuition of the wirelength based placement objective function is to reduce signal delays of the design and enhance routability simply by minimizing the total (weighted) wirelength With the aggressive advance of technology, placement starts to model other important aspects of the design directly, such as power, signal integrity, thermal distribution, clocking, placement congestion, or even optical proximity correction effects for better design manufacturability However, the fundamental formulation of the placement problem tends to stay the same, even in these new variants of placement algorithms New issues can be addressed by factoring in the corresponding modeling component into the wirelength based objective function For example, those additional factors are modeled into net weights and the weighted wirelength objective function can be minimized during placement Chapter

22 elaborates on how these modern issues are addressed in placement algorithms

Placement is an NP-complete problem [5] Consequently, the placement problem is usually divided into subproblems—global placement, legalization, and detailed placement—and each sub-problem is attacked separately Global placement determines the approximate distributions of circuit elements while optimizing a given objective function, typically wirelength Usually global placement allows some degree of overlapping among circuit elements leading to an illegal placement solution The legalization step then transforms an illegal global placement solution into a legal one (i.e.,

no overlap is allowed) while minimizing the perturbation to the original global placement solution Figure 14.4 shows a placement example before and after the legalization process Detailed placement finally improves the objective function further by performing local refinements It is also important to

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FIGURE 14.4 Before and after legalization of placement (a) Before legalization, i.e., illegal solution and

(b) after legalization, i.e., legal solution

keep a legal, nonoverlapping placement state during detailed placement Sometimes, the legalization process is viewed as part of the detailed placement process A variety of global placement algo-rithms are further described in Chapters 15 through 19, and Chapter 20 presents detailed placement algorithms

14.3 MODERN ISSUES IN PLACEMENT

In this section, we review several important issues in modern placement problem

1 Fixed layout region placement: Placement has been actively researched for a long time

as a fundamental problem in design automation The classical placement problem typi-cally focused on minimizing the overall placement area by packing circuit elements more compactly This packing-driven area optimization is still a dominant theme in the floor-planning domain In a modern chip synthesis flow for timing closure, however, placement optimization is executed almost always after the die size and package have been chosen Thus, placement should be formulated as an (wirelength) optimization problem with a fixed layout region, rather than a packing-driven area minimization problem [6] In fixed region placement, the layout area is already determined and the circuit elements and its netlist are also determined Thus, the amount of white space is a constant This implies that the man-agement of white space during placement becomes more important than before, to minimize placement objective functions such as wirelength and routing congestion

2 White space management for congestion control: One thing noticeably different in modern

IC designs is the increasing amount of white space available in a design [7] As design complexity continues to increase while time-to-market decreases, IP reuse and semihier-archical or full-hiersemihier-archical designs are becoming increasingly pervasive leading to more chunky design footprints with memory arrays, IP blocks, etc., as opposed to pure standard cell designs Consequently, today’s placement instances resemble the problem of arranging

“dust” logic (standard cells) around these large blocks Because the large blocks tend to dictate the design footprint, one can no longer assume that the placeable area in some way matches the total cell area of the design; one must recognize the trend of the increasing percentage of free space available on the chip One might think increased free space, or design sparsity, might make placement easier However, even though the dust logic is a small percentage of the chip area, there can still be millions of cells in the dust logic that have profound effects on timing and routability In other words, packing all the cells in a design can yield the minimum wirelength solution, but create enough congestion to make

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