Handbook of algorithms for physical design automation part 19 pptx

9.4 OPTIMIZATIONS ON SLICING FLOORPLANS One approach to floorplan design is to first determine a floorplan topology the slicing structure for a slicing floorplan, that is, the relative p

4 2 1 3

V

4

V

V

H

4

FIGURE 9.1 Slicing floorplan and its two slicing trees (a) A slicing floorplan for four modules, (b) and (c)

two slicing trees for the floorplan in (a)

accommodates a different module Figure 9.1a shows a slicing floorplan for four modules There are advantages of using slicing floorplans For example, focusing on slicing floorplans significantly reduces the search space and, thus, the runtime Moreover, the shape flexibilities of modules can be fully utilized to pack modules tightly [3–5] Consequently, existing slicing floorplan algorithms in general run very efficiently and yet can pack modules tightly

In Section 9.2, we give some necessary preliminaries with respect to the floorplan design problem

In Section 9.3, we present two schemes for representing slicing floorplans In Section 9.4, we study several important optimization problems, including the well-known area optimization problem, and their solutions for slicing floorplans These optimization algorithms are typically embedded into a slicing floorplanner We then turn our attention to classical slicing floorplan design, and introduce different solutions in Section 9.5 In Section 9.6, we focus on modern slicing floorplan design that takes placement constraints into account Several placement constraints are addressed, and their solutions are described Finally, we highlight more recent advances in slicing floorplan design for field programmable gate arrays (FPGAs) and three-dimensional integrated circuits (3D ICs), in addition to several interesting theoretical results, in Section 9.7, and draw a conclusion in Section 9.8

9.2 PRELIMINARIES

In the floorplan design problem, we are given a set of n modules, named 1, 2, , n, and a list of n

triplets of numbers,(a1 , p1, q1), (a2, p2, q2), , (an , p n , q n ) with p i ≤ q i, 1≤ i ≤ n For each module

i, (a i , p i , q i ) specifies its area and shape constraint That is, if module i has width w i and height h i, the following conditions must hold:

1 w i × h i = a i

2 p i ≤ (h i /w i ) ≤ q i , if i ∈ M1

3 p i ≤ (h i /w i ) ≤ q ior(1/q i ) ≤ (h i /w i ) ≤ (1/p i ), if i ∈ M2

We define(h i /w i ) to be the aspect ratio of module i Module i is said to be a hard module if p i = q i,

otherwise it is said to be a soft module The two disjoint module sets M1 and M2 are given with

M1 ∪ M2 = {1, 2, , n}, where M1 specifies the set of modules with fixed orientation, and M2

specifies the set of modules with free orientation (i.e., they can be rotated) Given a floorplan, if x i

and y iare the width and the height, respectively, of the basic rectangle that accommodates module

shape constraints for a module where each shaded region (including the shape curve) is called the bounded area A point in the bounded area gives the dimensions of the basic rectangle that can

accommodate the module (The x and y coordinates of the point give the width and the height of the

room.) Figure 9.2a and b correspond to the case where the module is rigid; in addition, the module in Figure 9.2a has fixed orientation while the one in Figure 9.2b can be rotated Figure 9.2c and d both correspond to the case where the module is flexible (soft); similarly the module in Figure 9.2c has

fixed orientation while the one in Figure 9.2d has free orientation Let H, L , L , L , and L be the

(a) (b) (c) (d)

d c

b b

a a

a a

d

x x

x x

FIGURE 9.2 Different shape curves (a) The shape curve for a hard module with fixed orientation, (b) the

shape curve for a hard module with free orientation, (c) the shape curve for a soft module with fixed orientation, and (d) the shape curve for a soft module with free orientation

hyperbola xy = a i , the line y = q i x, the line y = p i x, the line y = (1/p i )x, and the line y = (1/q i )x,

respectively In these figures, the intersections between H and L1, L2, L3, L4 are points a, b, c, d,

respectively

To describe the wiring information between each pair of modules, an n × n matrix C can be provided, where element c ij, 1 ≤ i, j ≤ n, denotes the number of wires between modules i and

j Given a floorplan, its quality is typically measured by the area of the enveloping rectangle, the

center-to-center total wirelength, or a weighted sum of the area and the wirelength If d ij denotes

the center-to-center Manhattan distance between basic rectangles (or modules) i and j, 1 ≤ i, j ≤ n,

the total wirelength can be defined to be

to find a floorplan that minimizes a given cost measure subject to the area and shape constraints imposed on each module Moreover, a designer can also specify the range of the aspect ratio of the chip to constrain the final floorplan to have a certain shape

9.3 SLICING FLOORPLAN REPRESENTATIONS

In this section, we describe two well-known and frequently used representations, slicing tree [1,3] and Polish expression [2], for slicing floorplans Their details are given in Sections 9.3.1 and 9.3.2

9.3.1 SLICING TREE

The hierarchical structure of a slicing floorplan can be described by an oriented rooted binary tree, called slicing tree*[1,3] Figure 9.1b shows a slicing tree for the slicing floorplan given in Figure 9.1a

Each internal node of a slicing tree is labeled with either V or H, denoting either a vertical or a horizontal cut Each leaf denotes a room (or module) and is labeled by a number between 1 and n.

A slicing tree is said to be skewed if no node and its right child have the same label [2] Figure 9.1c is a skewed slicing tree while Figure 9.1b is not, although both slicing trees represent the same floorplan From Figure 9.1, it is clear that a slicing floorplan may be represented by more than one slicing tree These slicing trees correspond to different orders in which consecutive horizontal and vertical cuts are made In fact, a skewed slicing tree is obtained by making consecutive horizontal cuts from top

to bottom, and consecutive vertical cuts from right to left It can be proved that the skewed slicing tree is unique for a given slicing floorplan

It should be noted that a slicing tree is only a top-down description of the cut types (horizontal

or vertical) for a given slicing floorplan, and no dimensional information is associated with each cut Therefore, a slicing tree may represent more than one slicing floorplan These floorplans differ

in the dimensions for the rooms An equivalence relation can be defined on the set of all slicing

floorplans with n modules Given two different floorplans, they are said to be equivalent iff they

* There are slicing floorplans that can be also represented by trees such that internal nodes in these trees have more than two children These trees can always be transformed into binary trees Therefore, using a binary tree to represent a slicing floorplan causes no loss of generality.

are represented by the same skewed slicing tree As a result, the set of slicing floorplans can be partitioned into equivalence classes, where each equivalence class of slicing floorplans corresponds

to a different slicing structure Therefore, we can use the set of skewed slicing trees with n leaves to represent the set of slicing structures with n modules without causing any redundancies As we shall

see in Section 9.4, there are efficient algorithms for selecting a “best” floorplan (e.g., measured by the floorplan area) among the floorplans with the same slicing structure

9.3.2 POLISH EXPRESSION

Given a slicing tree, we can obtain the corresponding Polish expression by performing the postorder traversal of the tree [2] For example, the Polish expressions for the two slicing trees shown in

Figure 9.1b and c are 412H3VV and 412HV 3V , respectively Clearly, there may be more than one

Polish expression that represents the same slicing floorplan This makes the Polish expression rep-resentation (or equivalently the slicing tree reprep-resentation) an undesirable choice for representing solutions at least for the following reasons First, the solution space is unnecessarily increased Sec-ond, the set of slicing structures is not evenly distributed over the set of Polish expressions, causing undesirable biases toward some slicing structures Because there is always only one skewed slic-ing tree for representslic-ing a slicslic-ing structure, the correspondslic-ing normalized Polish expression is thus defined and obtained by performing the postorder traversal of the skewed slicing tree [2] Because

no internal node and its right child have the same cut type in a skewed slicing tree, there are no

consecutive V ’s or H’s in the corresponding normalized Polish expression Besides, it can be also

proved that there is a one-to-one correspondence between the set of normalized Polish expressions

of length 2n − 1 and the set of slicing structures with n modules.

9.4 OPTIMIZATIONS ON SLICING FLOORPLANS

One approach to floorplan design is to first determine a floorplan topology (the slicing structure for a slicing floorplan), that is, the relative positions of the modules by using the wiring information among the modules On the basis of the floorplan topology, various optimization problems are then solved

to minimize a given cost measure Among them, the area optimization determines a shape for each module such that the area of the resultant floorplan is minimized [3–6] Besides, if each module is also given a power consumption value associated with each allowable shape, the area/power optimization problem can be defined to select a shape as well as its associated power consumption value for each module such that the power (obtained by summing up the power consumption values of all modules) and the area of the resultant floorplan are optimized simultaneously [7] In this section we address several variants of the area optimization problem and the area/power optimization problem for slicing floorplans, and introduce their efficient solutions

9.4.1 AREA OPTIMIZATION

In this subsection, our focus is on slicing floorplan area optimization We assume that the given slicing structure is specified by a slicing tree Two variants of slicing floorplan area optimization are addressed The first one assumes that the given slicing tree is oriented in the sense that the cut type of each internal node is explicitly specified Such an oriented tree complies exactly with the definition of a slicing tree as given in Section 9.3 On the other hand, to increase the chance of further minimizing flooplan area, the second variant assumes that the given tree is unoriented, which means that the cut type of each internal node is not specified and thus needs to be determined as well

9.4.1.1 Oriented Slicing Tree

For the case where an oriented slicing tree is given, we describe three algorithms by Stockmeyer [3], Shi [4], and Otten [5]

9.4.1.1.1 Stockmeyer’s Algorithm

In Ref [3], Stockmeyer considers the module orientation problem where each module is rigid but may

be rotated Therefore, each module has at most two possible shapes The shape curve for each such module looks like the one shown in Figure 9.2a or b Given an oriented slicing tree and the possible shapes of each module, Stockmeyer gives an efficient algorithm to select a shape for each module such that the resulting floorplan has the smallest area among all equivalent floorplans represented

by the given slicing tree

Let T be the given slicing tree, u be a node of T , and L (u) be the set of leaves in the subtree

rooted at u Stockmeyer’s algorithm constructs a list of pairs, {(w1, h1), (w2, h2), , (wk , h k )}, with

k ≤ |L(u)| + 1, w1 > w2 > · · · > w k and h1 < h2 < · · · < h k for u The first and second numbers

in each pair denote the width and the height of a module (if u is a leaf) or a subfloorplan (if u is an

internal node), respectively Besides, two pointers are kept for each pair in the list to facilitate the determination of the shape for each module that achieves the minimum-area floorplan

The construction is done in bottom-up manner For a leaf of T , the algorithm constructs a list to store the shapes of the corresponding module If a module has dimensions w and h with w > h, the

list is{(w, h), (h, w)} On the other hand, if w = h or the module has a fixed orientation, only one

with children u1and u2, let{(w1, h1), (w2, h2), , (w m , h m )} and {(w

1, h1), (w 

2, h2), , (w

k , hk )}

be the two lists of pairs which have been constructed for u1 and u2, respectively Besides, we have

m ≤ |L(u1)| + 1 and k ≤ |L(u2)| + 1 Suppose u corresponds to a horizontal cut Then a pair

(w i , h i ) from u1and a pair(w

j , hj ) from u2can be combined to get a pair(max(w i , wj ), h i + h

j ) in

the list for u It is clear that that not all mk such new pairs need consideration if some of them are redundant For example, with w i > w

j, there is no need to combine(w i , h i ) and (w

z , hz ) for any

z > j because max(w i , wj ) = max(w i , wz ) = w i , and h i + h

j < h i + h

z (Note that in this case (max(w i , wz ), h i + h

sorted lists, is used for combining the two lists to obtain the list for u.

1 i ← 1, j ← 1.

2 If i > m or j > k then terminate.

3 Add(max(w i , wj ), h i + h

j ) to the list for u with pointers to (w i , h i ) and (w

j , hj ).

4 If w i > w

j , then i ← i + 1 and goto (2).

5 If w i < w

j , then j ← j + 1 and goto (2).

6 If w i = w

j then i ← i + 1, j ← j + 1, and goto (2).

Clearly, the time complexity of the procedure is linear, that is, O (m + k), and the length of the list

produced for u is at most m + k − 1 ≤ |L(u1)| + 1 + |L(u2)| + 1 − 1 = |L(u)| + 1 The procedure

can be easily modified if u corresponds to a vertical cut.

After the list for the root of T is constructed, a pair producing the minimum area (and satisfying

the given chip aspect ratio constraint) is chosen and the corresponding pointers are used to determine

the shape of each module in a top-down manner The time complexity of the whole algorithm is O (n2)

in the worst case, where n is the number of modules It should be pointed out that the algorithm can

be naturally applied to handle the general case where modules may have more than two possible shapes

9.4.1.1.2 Shi’s Algorithm

In Ref [4], Shi considers the same area optimization problem as in Ref [3] and presents a faster

algorithm that runs in O (m log m) time, where m is the total number of possible shapes of all modules.

This complexity does not depend on the number of modules, the depth of the slicing tree, or the

distribution of the m shapes among the modules He also proves that O (m log m) is the lower bound

on the time complexity for any area minimization algorithm, which implies that his algorithm has

an optimal runtime

Instead of using a list to store the set of possible shapes for each node u of a slicing tree, Shi’s

algorithm uses a balanced binary tree (e.g., AVL tree [8] or red–black tree [9]), denoted by BBT(u).

We call BBT(u) the shape tree for u For every irredundant shape s of u, there is a node v(s) in

w [v(s)]: to be used for computing the width of s

h [v(s)]: to be used for computing the height of s

w+[v(s)]: to be added to the widths of all descendents of v(s)

h+[v(s)]: to be added to the heights of all descendents of v(s)

on either key However, the width w (s) and the height h(s) of s are not explicitly stored in the

corresponding node v (s) Instead, they are stored in the path from the root of BBT(u) to v(s) Let

are computed as follows:

v ∈P(s)

w+[V]

v ∈P(s)

h+[V]

For example, a balanced binary tree storing five shapes (5,5), (4,6), (3,7), (2,8), and (1,9) are shown

in Figure 9.3 The reason for introducing the two fields h+and w+ is as follows Suppose u is an internal node of the slicing tree T , has two children u1 and u2, and corresponds to a horizontal cut

Suppose that we want to combine k shapes s1, s2, , s k of u1with a shape t of u2to get k shapes of u.

Let BBT(u1) denote the tree storing the list of shapes, s1 , s2, , s k of u1 Also assume that the widths

of s1, s2, , s k are all greater than the width of t To combine s i ’s and t, Stockmeyer’s algorithm will add the height of t to the heights of s1, s2, , s k and take O (k) time However, it takes only O(1)

time for Shi’s algorithm to add the height of t to the h+field of the root of BBT(u1 ) Now BBT(u1)

becomes a shape tree for u The h+value will be propagated down and added to the height of a node

in BBT(u1) as soon as the corresponding shape is accessed in the future As a result, repeated and

unnecessary updates can be avoided by postponing the propagation until future access happens

We next explain how to construct the irredundant shapes for an internal node u of T with children

u1 and u2and store them in a shape tree BBT(u) Assume the irredundant shapes of u1 and u2have

(w,h) = (2,6) (w+ ,h+ ) = (0,2)

(w,h) = (1,7) (w+ ,h+ ) = (0,0)

(w,h) = (3,4) (w+ ,h+ ) = (1,0)

(w,h) = (2,5) (w+ ,h+ ) = (0,0)

(w,h) = (4,2) (w+ ,h+ ) = (0,1)

FIGURE 9.3 Balanced binary tree storing five shapes.

been obtained and stored in the shape trees BBT(u1 ) and BBT(u2 ), respectively Let the number

of shapes in BBT(u1) and BBT(u2) be m1 and m2 Without loss of generality, we assume m1 ≥ m2 The shape tree BBT(u) is constructed in the following three steps The first step is to find irredundant

shapes of u such that their widths are decided by u2, or by u1and u2, and to store them in a list L for later use The second step is to find irredundant shapes of u such that their heights are decided by u1

The last step is to insert the list L generated in the first step into the shape tree obtained in the second

step The three steps are implemented by performing search, insertion, and deletion operations on

9.4.1.1.3 Otten’s Algorithm

Recall from Section 9.2 that each point on the shape curve of a module denotes a possible shape

of the module The shape curve of a module can be naturally generalized to a subfloorplan that

corresponds to an internal node of a slicing tree Let u be an internal node of a given slicing tree with children u1 and u2 Let C (u), C(u1 ), and C(u2 ) denote the shape curves of u, u1 , and u2,

respectively Let C (u1) + C(u2 ) be the shape curve obtained by adding C(u1) and C(u2) along the y-direction; that is, C (u1 ) + C(u2) = {(x, y + y)|(x, y) ∈ C(u1) and (x, y) ∈ C(u2)} (Figure 9.4a).

Let C (u1 )∗C (u2 ) be the shape curve obtained by adding C(u1) and C(u2 ) along the x-direction; that

is, C (u1)∗C (u2) = {(x + x, y )|(x, y) ∈ C(u1) and (x, y ) ∈ C(u2)} Otten in Ref [5] observes that

if u corresponds to a horizontal cut, C (u) can be obtained from C(u1 ) + C(u2) On the other hand,

if u is a vertical cut, C (u) can be obtained from C(u1 )∗C (u2 ) It is easy to see that C(u) produced

in either way is also a shape curve Moreover, C (u) is piecewise linear if both C(u1 ) and C(u2) are

piecewise linear The shape curves shown in Figure 9.2a and b (both are also called staircase shape curves) and Figure 9.4b are all piecewise linear Any piecewise linear shape curve can be completely characterized by an ordered list of all its corners (For example,{a}, {a, d} and {a, b, c, d, e} are the

ordered lists of corners of the curves shown in Figures 9.2a,b and 9.4b, respectively.) For piecewise

linear shape curves, Otten gives an efficient algorithm that computes C (u) by adding C(u1) and C(u2)

at the corners along a corresponding direction

It should be pointed out although Stockmeyer’s algorithm originally only targets the set of staircase shape curves (which is a subset of all piecewise linear curves), it is also directly applicable to piecewise linear curves because it adopts the same idea as Otten’s algorithm (though both algorithms were developed independently)

(b) (a)

X

Y

a b c d e

C(u1 )

C(u2 )

X

Y

C(u)

FIGURE 9.4 (a) Adding two shape curves along the y-direction (b) Piecewise linear shape curve.

9.4.1.2 Unoriented Slicing Tree

In Ref [6], Zimmermann studies a variant of the area optimization problem in which no assumption

is made about the cut type of each internal node in a slicing tree He presents an algorithm that first computes the two shape curves for each internal node, one for a vertical cut and the other for

a horizontal cut See Figure 9.5 for an illustration, where the shape curves in Figure 9.5c and d are

obtained by adding the two shape curves in Figure 9.5a and b along the y-direction (corresponding

to a horizontal cut) and the x-direction (corresponding to a vertical cut), respectively Then the lower bound of the two shape curves is chosen at each x coordinate to produce the final shape curve of this

internal node (see Figure 9.5e where the final shape curve is shown in boldface) In addition, each segment of the final shape curve can be marked to represent the chosen cut type This algorithm has exponential-time complexity in the worst case even if the shape curve of each module is piecewise linear, but has pseudopolynomial complexity when each module has integer dimensions

9.4.2 AREA/POWER OPTIMIZATION

In Ref [7], Chao and Wong study an optimization problem that considers both area and power For each possible shape of a module in the problem, a power consumption value is also given and associated with the shape Each possible shape together with its associated power consumption value are called an implementation Given a slicing tree, the problem asks to select an implementation for each module based on the power and geometrical information such that both the area and the power consumption of the resultant floorplan are optimized The power consumption of a floorplan is obtained by adding up the power consumption value of the selected implementation of each module

y

0

2

4

6

8

10

y

0 2 4 6 8 10

0

2

4

6

8

y

0 2 4 6 8

y

y

0 2 4 6 8 10

FIGURE 9.5 Illustration of Zimmerman’s algorithm (a) and (b) are two shape curves, (c) the shape curve

obtained by adding the two shape curves in (a) and (b) along the y-direction, (d) the shape curve obtained by adding the two shape curves in (a) and (b) along the x-direction, and (e) the shape curve (in boldface) obtained

by choosing the lower bound of the two shape curves in (c) and (d) at each x coordinate

Two versions of the optimization problem are considered The first one is to minimize the floorplan power consumption subject to a given upper bound on the floorplan area Another one is to minimize the floorplan area subject to a given upper bound on the floorplan power consumption Both versions can be solved by almost the same algorithm The only difference is the criterion for selecting a best implementation for the floorplan after the set of implementations is constructed for the floorplan Suppose each implementation of a module is denoted by a triple(w, h, e) where w, h, e

repre-sent the width, the height, and the power consumption value, respectively Also assume that each implementation is irredundant (An implementation(w, h, e) is redundant if there is another

imple-mentation(w, h, e) of the same module such that x ≥ x, y ≥ y, and e ≥ e.) Let Q be the set of

possible implementations of a module, and{e1, e2, , e k} be the set of distinct power consumption

values in Q Q is first partitioned into k disjoint sets, Q1, Q2, , Q ksuch that each implementation

in Q i has the same power consumption value p i, 1≤ i ≤ k The geometric information of the imple-mentations in Q iis denoted by the set{(w, h)|(w, h, e) ∈ Q i}, which is assumed to be specified by

a piecewise linear shape curve C i The pair(p i , C i ) is called a power-indexed shape curve Let C

and Cdenote two piecewise linear shape curves Given two power-indexed shape curves(C, e) and (C, e), (C, e) + (C, e) ((C, e)∗(C, e), respectively) is defined to be the power-indexed shape curve (C+C, e +e) ((C∗C, e +e), respectively) (Recall that both C+Cand C∗Ccan be efficiently

com-puted [3–5].) Let S = {(C1, e1), (C2, e2), , (Cl , e l )} and S = {(C

1, e1), (C 

2, e2), , (C 

k , ek )}

be two sets of power-indexed shape curves We define S + S (S + S, respectively) to be

{(C i + C

j , e i + e

j )|1 ≤ i ≤ l, 1 ≤ j ≤ k} ({(C i∗Cj , e i + e

j )|1 ≤ i ≤ l, 1 ≤ j ≤ k}, respectively).

The algorithm constructs a set of power-indexed shape curves for every internal node in a

bottom-up fashion Let u be an internal node with children u1 and u2 Let S (u), S(u1), and S(u2) denote

the sets of power-indexed shape curves of u, u1, and u2, respectively S (u) can be constructed by

S (u1) + S(u2) (if u is a horizontal cut) or S(u1)∗S (u2) (if u is a vertical cut) Besides, if there exist two

power-indexed shape curves in S (u) having the same power consumption value, they can be combined

into one by merging their shape curves Once the set of power-indexed shape curves for the root,

say S = {(C1, e1), (C2, e2), , (Cl , e l )}, is computed, the area of every irredundant implementation

of the root can be calculated from a corner on each C i Among those implementations whose power consumption (area, respectively) satisfies the given power (area, respectively) bound, the one with minimum area (minimum power, respectively) is selected

The algorithm has exponential-time complexity in the worst case, but if each implementa-tion of any module has integer power consumpimplementa-tion value and dimensions, the algorithm runs in pseudopolynomial time

9.5 CLASSICAL SLICING FLOORPLAN DESIGN

The slicing floorplan design problem in general can be solved by the following two typical approaches The first approach is to derive the final solution in two stages It first determines a slicing structure (or an initial floorplan) using wiring information among modules (and possibly area information of modules), and then uses the geometric shape information of the modules to solve some optimization problems, for example, those introduced in the previous section, on the slicing structure and to produce the final solution The mincut-based methods [10,11] and the point-configuration based methods [1,12] fall into this type of approach Another approach to solve the floorplan design problem is by simultaneously considering the interconnection information as well as the area and shape information This approach starts with an initial floorplan and iteratively improves solutions

by taking both interconnect and shape information into account until the convergence is reached or the runtime exceeds The simulated annealing based algorithm [2], which uses the set of normalized Polish expressions as the solution space, belongs to this type of approach

It will require more than a single chapter to review all existing methods for slicing floorplan design Therefore, our focus in this section is on introducing some classical methods, including the mincut-based methods [10,11], the point-configuration based methods [1,12], and the simulated annealing based method [2], which fall into the above-mentioned two types of approaches

9.5.1 MINCUT-BASED SLICING FLOORPLAN DESIGN

A typical mincut-based method is to first apply a mincut partitioning algorithm (e.g., [13–15]) to generate a slicing structure (or an initial floorplan) and then use various optimization techniques

to generate the final solution During the mincut partitioning process, the shape of each module is ignored, and only its area is taken into account This process is equivalent to a sequence of partitioning steps each of which divides a set of modules into two subsets such that the number of nets connecting modules from both subsets and the area difference between the two subsets are small The partitioning process terminates when each subset contains only one module The algorithms in Refs [10,11] are classified as this type of approach, and are described below

The mincut-based algorithm given in Ref [10] assumes that the modules to be placed are all hard modules, but can be rotated and reflected Throughout the mincut partitioning process, the chip

layout is represented by a pair of dual graphs G x = (V x , E x ) and G Y = (V x , E y ) Each of G x and G y

is a planar, directed acyclic graph (DAG) containing one source and one sink, and may have parallel

edges There is a one-to-one correspondence between the edges of G x and G y, and each corresponding pair of edges(e x , e y ) represents a rectangle with width l(e x ) and height l(e y ), where l(e) denotes the

length associated with edge e Besides, each pair of edges (e x , e y ) also corresponds to a subset of

modules; the area l (e x ) × l(e y ) equals the total area of the modules in the subset At the beginning,

both G x and G y contain one edge each, e x and e y, and this pair of edges corresponds to the set of all

modules The chip layout covered by the modules is assumed to be square, and therefore both l (e x )

and l (e y ) are set to be√A, where A is the total area of the modules The set of all modules is then

partitioned into two subsets using a modified Kernighan–Lin algorithm [13,14] such that the number

of nets incident to modules in different subsets is as small as possible and the area difference in the two subsets does not exceed a predefined value This step also corresponds to a splitting of the edge

pair into two new edge pairs each of which represents one subset The length of each edge in G xis adjusted according to the total module area of the corresponding subset The partitioning procedure

is applied to both of the subsets, but the cut direction is changed and therefore the edge lengths in

G y need adjusting afterward The partitioning algorithm is applied recursively to the new subsets

until each subset contains one module Now each edge pair of G x and G ycorresponds to a module, but the shape of the module is not correctly represented To fix it, the lengths of each edge pair are first replaced by the dimensions of the corresponding module, and then in both graphs a longest path from the source to each node is calculated to get the position of the corresponding module

It is clear that the mincut partitioning process induces a slicing floorplan due to the nature

of recursive mincut partitioning To further reduce the area or wirelength of the floorplan, three methods, rotation, squeezing, and reflecting, are applied To rotate a module, the width and height

of the module are exchanged The squeezing technique splits a node into two nodes and inserts

a zero-length edge pair The reflection technique flips a module with respect to the x- or y-axis.

Reflection of a module only influences the wirelength Note that squeezing causes local changes in

a graph, and therefore may destroy the slicing structure

In contrast to the above-mentioned algorithm, another mincut partitioning based method, called Mason [11] allows each module to have a number of possible shapes (i.e., soft module), and uses

a slicing tree (instead of a pair of dual graphs) to represent the partitioning hierarchy At each partitioning step, an in-place partitioning scheme is applied together with a combined exhaustive and heuristic partitioning method The idea behind in-place partitioning is to perform partitioning

by taking external connections into account, resulting in a better global positioning of modules The exhaustive partitioning procedure enumerates all possible solutions to find the optimal solution

On the other hand, the heuristic partitioning method adopts the Fiduccia–Mattheyses method [15] Whether the exhaustive or heuristic method is used for a partitioning step is based on the number of modules to be partitioned Once the slicing tree is constructed, the dimensions and position of each module are determined by an area optimization method similar to those in Refs [3–5]

9.5.2 POINT-CONFIGURATION BASED SLICING FLOORPLAN DESIGN

The point-configuration based approach treats each module as a point by ignoring the area of the module It is based on using the interconnection information as the only measure of the mutual proximity between modules, and uses a mathematical method involving matrix manipulation to position the modules as points in the plane From this point configuration, a slicing structure is constructed by taking module areas and shapes into consideration Finally, various optimization procedures are applied to produce the positions and orientations (or dimensions) of the modules realizing the final floorplan under a cost measure The algorithms in Refs [1,12] are classified as this type of approach, and are introduced below

The algorithm in Ref [12] combines the advantages of force-directed placement and mincut algorithm A force-directed placement algorithm solves a system of differential equations that con-siders interconnection information It is fast in calculating a point configuration, but modules may overlap in the solution because it ignores the size and shape information of the modules On the other hand, a mincut algorithm can effectively consider module areas during the partitioning process, but due to its sequential nature, the partitioning result depends on the starting solution and the amount

of nets cut is minimized only locally Therefore, the algorithm in Ref [12] uses a modified Newton– Raphson method [16] to calculate a point configuration, and a cut algorithm to calculate a slicing floorplan based on the point configuration as well as the shapes of the modules In fact, the cut algorithm does not need a partitioning algorithm like the ones in Refs [13–15]; instead it uses the point configuration produced by the force-directed algorithm Each cutline (which carries the posi-tion informaposi-tion on the fixed-area chip and thus geometrically separates modules into two parts) is determined with respect to the constraints such as the sizes and shapes of the modules, the number

of modules per subset, and the minimization of critical signal nets The cut algorithm terminates when each subset (corresponding to a basic rectangle on the chip plane) contains only one module

A slicing structure is implied by the cut algorithm, but due to the shape mismatches between basic rectangles and modules, modules may overlap To eliminate module overlaps, modules are moved and rotated by taking module shapes into consideration

Another point-configuration based algorithm is given in Ref [1] To get a point configuration,

the algorithm in Ref [1] first defines a dutch metric D which is an n ×n matrix with each off-diagonal element d ijbeing 1− c ij , and each diagonal element being 0, where c ij=
{wk|pik=1 and pjk=1}
{wk|pik=1 or pjk=1} Note that

w k is the weight given for net k (the higher the weight of a net, the closer the modules connected by the net should be), and p ik = 1 if module i is connected to net k, otherwise p ik= 0 With the matrix

largest eigenvalues are obtained, where Z, I, J are n × n matrices, Z = J − (1/n)I, I has all elements being 1, and J has each diagonal element being 1 and the other elements being 0 The corresponding

two-dimensional point configuration of the modules is now specified by the two eigenvectors Next, using the information on module areas and assuming that all modules are flexible, but their shapes are close to square, a slicing structure is constructed based on deformation calculation The consequence

of this construction is that modules with points relatively far from each other are separated after

a few cutlines while modules with points at a relatively short distance are together in many nested cutlines Moreover, the relative positions of the modules in the slicing structure will closely resemble those of the corresponding points in the Schoenberg construction Finally, the wiring space in the structure can be estimated and translated into a set of constraints for an optimization procedure to produce the position and orientation of each module that realizes the best final floorplan subject to these constraints

9.5.3 SIMULATED ANNEALING BASED SLICING FLOORPLAN DESIGN

Wong and Liu in Ref [2] present a slicing floorplan design algorithm that simultaneously minimizes the chip area and the total wirelength Their algorithm is referred to as the Wong–Liu algorithm