Hardware and Computer Organization- P11 ppsx

LEA Load Effective Address Calculates the effective address offset of a data element and loads the value into a register LDS Load DS with Segment and Register with Offset Reads a ful

We see this in the next two bytes of the instruction, AA 00 The r/m field value 001 then gives us

the final form of the address calculation, [BX + DI + DISP] The final byte of the instruction, 55h,

is the 8-bit immediate value, imm8, as shown in the format of the opcode

If we modify the instruction as follows:

CS:MOV [BX+DI+0AAh],5555h

The instruction code becomes 2E C7 81 AA 00 55 55 The opcode changes from C6 to C7, cating a word operation and the immediate field is now two bytes long The entire instruction is now 7 bytes long, so we can see why the 8086 architecture must allow for nonaligned accesses from memory since the next instruction would be starting on an odd boundary if this instruction began on a word boundary

indi-8086 Instruction Set Summary

While it is beyond the scope of this text to cover the 8086 family instructions in detail we can look

at representative instructions in each class and use these instructions as to gain an understanding

of all of the instructions Also, some of the instructions will also extend our insight into the overall x86 family architecture

We can classify the original x86 instruction set into the following instruction families:

• Data transfer instructions

• Arithmetic instructions

• Logic instructions

• String manipulation instructions

• Control transfer instructions

Most of these instruction classes should look familiar to you Others are new The 68K family instruction set did not have dedicated instructions for loop control or string manipulation Whether

or not this represents a shortcoming of the architecture is difficult to assess Clearly you are able

to manipulate strings and form software loops in the 68K architecture as well Let’s now look at some representative instructions in each of these classes

Data Transfer Instructions

Just as with the MOVE instruction of the 68K family, the MOV instruction is probably the most used instruction in the instruction set We’ve looked at the MOV instruction in some detail in this chapter, using it as a prototype instruction for understanding how the x86 instruction set architec-ture functions We may summarize the instructions in the data transfer class in the following table6 Note that not all of the instruction mnemonics are listed and some f the instructions have additional variations with unique mnemonics This table is meant to summarize the most general classification

oft-Mnemonic

MOV MOVE Copies data from a source operand to a destination operand PUSH PUSH Creates storage space for an operand on the stack and then cop- ies the operand onto the stack POP POP Copies component from the top of the stack to memory or register

Mnemonic

IN INPUT Read data from address in I/O space

OUT OUTPUT Write data to address in I/O space

XLAT TRANSLATE Translates the offset address of byte in memory to the value of the byte. LEA Load Effective Address Calculates the effective address offset of a data element and loads the value into a register LDS Load DS with Segment and

Register with Offset

Reads a full address pointer stored in memory as a 32-bit double word and stores the segment portion in DS and the offset portion

in a register LES Segment and Load ES with

Register with Offset

Same as LDS instruction with the exception that the ES register is loaded with the segment portion of the memory pointer rather than DS

LAHF Load AH with Flags Copies the Flag portion of the Processor Status Register to the AH register SAHF Store AH in Flags Copies the contents of the AH register to the Flag portion of the Processor Status Register PUSHF Push Flags onto stack Creates storage space on the stack and copies the flag portion of the Processor Status Register onto the stack. POPF Pop Flags from stack Copies the data from the top of the stack to the Flag portion of the Processor Status Register and removes the storage space from

ADC Add with carry Add two integers or unsigned numbers and the contents of the Carry Flag INC Increment Increment the contents of a register or memory value by 1

AAA ASCII adjust AL after addition Converts an unsigned binary number that is the sum of two unpacked binary coded decimal numbers to the unpack decimal

Mnemonic

CMP Compare Subtracts two integers or unsigned numbers and sets the flags accordingly but does not save the result of the subtraction

Nei-ther the source nor the destination operand is changed AAS ASCII adjust after subtraction Converts an unsigned binary number that is the difference of two unpacked binary coded decimal numbers to the unpacked decimal

equivalent.

DAS after subtraction Decimal adjust

Converts an 8-bit unsigned value that is the result of subtraction

to the correct binary coded decimal equivalent

MUL Multiply Multiplies two unsigned numbers

IMUL Integer Multiply Multiplies two signed numbers

AAM ASCII adjust for Multiply Converts an unsigned binary number that is the product of two unpacked binary coded decimal numbers to the unpacked decimal

equivalent.

IDIV Integer divide Divides two signed numbers

AAD ASCII adjust after division Converts an unsigned binary number that is the division of two unpacked binary coded decimal numbers to the unpacked decimal

equivalent.

CWD Convert word to double Converts a 16-bit integer to a sign extended 32-bit integer

CBW Convert byte to word Converts an 8-bit integer to sign extended 16-bit integer

All of the above instructions have analogs in the 68K architecture with the exception of the 4 ASCII adjust instructions which are used to convert BCD numbers to a form that may be readily converted to ASCII equivalents

Logic Instructions

The following table summarizes the 8086 logic instructions,

Mnemonic

NOT Invert One’s complement negation of register or memory operand SHL Logical shift left SHL and SAL shift the operand bits to the left, filling the shifted

bit positions with 0’s The high order bits are shifted into the CF bit position

SAL Arithmetic shift left

SHR Logical shift right Shifts bits of an operand to the right, filling the vacant bit posi- tions with 0’s the low order bit is shifted into the CF position SAR Arithmetic shift right Shifts bits of an operand to the right, filling the vacant bit posi- tions with the original value of the highest bit The low order bit is

shifted into the CF position ROL Rotate left Rotates the bits of the operand to the left and placing the high order bit that is shifted out into the CF position and low order bit

position.

Mnemonic

ROR Rotate right Rotates the bits of the operand to the right and placing the low order bit that is shifted out into the CF position and the high order

TEST Logical compare Determines whether particular bits of an operand are set to 1 Results are not saved and only flags are affected.

OR Bitwise OR Computes the bitwise logical OR of the two operands.

XOR Exclusive OR Computes the bitwise logical exclusive OR of the two operands.

As you can see, the family of logical instructions is pretty close to those of the 68K family

String Manipulation

This family of instructions has no direct analog in the 68K architecture and provides a powerful group of compact string manipulation operations The following table summarizes the 8086 string manipulation instructions:

Mnemonic

REP Repeat Repeatedly executes a single string instruction

MOVS Move a string component Copy a byte element of a string (MOVSB) or word element of a string (MOVESW) from one location to another. CMPS Compare a string component Compares the byte (CMPSB) or word (CMPSW) element of one string to the byte or word element of a second string SCAS Scan a string for component Compares the byte (SCASB) or word (SCASW) element of a string to a value in a register LODS component Load string Copies the byte (LODSB) or word (LODSW) element of a string to the AL (byte) or AX (word) register. STOS Store the string component Copies the byte (STOSB) or word (STOSW) in the AL (byte) or AX (word) register to the element of a string

The REPEAT instruction has several variant forms that are not listed in the above table Like the 68K DBcc instruction the repeating of the instruction is contingent upon a value of one of the flag register bits It is clear how this set of instructions can easily be used to implement the string ma-nipulation instructions of the C and C++ libraries

The REPEAT instruction is unique in that it is not used as a separate opcode, but rather it is placed

in front of the other string instruction that you wish to repeat Thus,

REPMOVSB

would cause the MOVSB instruction to be repeated the number of times stored in the CX register

Also, the MOVS instruction automatically advances or decrements the DI and SI registers’ tents, so, in order to do a string copy operation, you would do the following steps:

con-1 Initialize the Direction Flag, DF,

2 Initial the counting register, CX,

3 Initialize the source index register, SI,

4 Initialize the destination index register, DI,

5 Execute the REPMOVSB instruction.

Compare this with the equivalent operation for the 68K instruction set There is no direction flag to set, but steps 2 through 4 would need to be executed in an analogous manner The auto increment-ing or auto decrementing address mode would be used with the MOVE instruction, so you would mimic the MOVSB instruction with:

MOVE.B (A0)+,(A1)+

The difference is that you would need to have an additional instruction, such as DBcc, to be your loop controller Does this mean that the 8086 would outperform the 68K in such a string copy op-eration? That’s hard to say without some in-depth analysis Because the REPMOVSB instruction

is a rather complex instruction, it is reasonable to assume that it might take more clock cycles to execute then a simpler instruction The 186EM4 processor from AMD takes 8 + 8*n clock cycles

to execute the instruction Here ‘n’ is the number of times the instruction is repeated Thus, the instruction could take a minimum 808 clock cycles to copy 100 bytes between two memory loca-tions However, in order to execute the 68K MOVE and DBcc instruction pair, we would also have

to fetch each instruction from memory over an over again, so the overhead of the memory fetch operation would be a significant part of the comparison

Control Transfer

Mnemonic

CALL Call procedure Suspends execution of the current instruction sequence, saves the segment (if necessary) and offset of the next instruction and

trans-fers execution to the instruction pointed to by the operand.

JMP Unconditional jump Stops execution of the current sequence of instructions and trans- fer control to the instruction pointed to by the operand. RET Return from procedure Used in conjunction with the CALL instruction the RET instruction restores the contents of the IP register and may also restore the

contents of the CS register.

JE Jump if equal If the Zero Flag (ZF) is set control will be transferred to the address

of the instruction pointed to by the operand If ZF is cleared, the instruction is ignored.

JL Jump on less than If the Sign Flag (SF) and Overflow Flag (OF) are not the same,

then control will be transferred to the address of the instruction pointed to by the operand If they are the same the instruction is ignored

JNGE greater of equal Jump on not

Mnemonic

JB Jump on below If the Carry Flag (CF) is set control will be transferred to the

ad-dress of the instruction pointed to by the operand If CF is cleared, the instruction is ignored.

JNAE Jump on not above or equal

JBE Jump on below or equal If the Carry Flag (CF) or the Zero Flag (ZF) is set control will be transferred to the address of the instruction pointed to by the

operand If CF and the CF are both cleared, the instruction is ignored.

JNA Jump on not above

JP Jump on parity If the Parity Flag (PF) is set control will be transferred to the

ad-dress of the instruction pointed to by the operand If PF is cleared, the instruction is ignored.

JPE Jump on parity even

JO Jump on overflow If the Overflow Flag (OF) is set control will be transferred to the address of the instruction pointed to by the operand If OF is

cleared, the instruction is ignored.

JS Jump on sign If the Sign Flag (SF) is set control will be transferred to the address of the instruction pointed to by the operand If SF is cleared, the

instruction is ignored.

JNE Jump on not equal If the Zero Flag (ZF) is cleared control will be transferred to the

ad-dress of the instruction pointed to by the operand If ZF is set, the instruction is ignored.

JNZ Jump on not zero

JNL Jump on not less If the Sign Flag (SF) and Overflow Flag (OF) are the same, then

control will be transferred to the address of the instruction pointed to by the operand If they are not the same, the instruc- tion is ignored

JGE Jump on greater or equal

JNLE Jump on not less than or equal If the logical expression ZF * (SF XOR OF) evaluates to TRUE then control will be transferred to the address of the instruction

pointed to by the operand If the expression evaluates to FALSE, the instruction is ignored

JG Jump on greater than

JNB Jump on not below If the Carry Flag (CF) is cleared control will be transferred to the

address of the instruction pointed to by the operand If CF is set, the instruction is ignored

JAE Jump on above or equal

JNC

JNBE Jump on not below or equal If the Carry Flag (CF) or the Zero Flag (ZF) are both cleared control will be transferred to the address of the instruction pointed to by

the operand If either flag is set, the instruction is ignored.

JNP Jump on not parity If the Parity Flag (PF) is cleared, control will be transferred to the

address of the instruction pointed to by the operand If PF is set, the instruction is ignored.

JO Jump on odd parity

JNO Jump on not overflow If the Overflow Flag (OF) is cleared control will be transferred to the address of the instruction pointed to by the operand If OF is

set, the instruction is ignored.

JNS Jump on not sign If the Sign Flag (SF) is cleared control will be transferred to the address of the instruction pointed to by the operand If SF is set,

the instruction is ignored.

Mnemonic

LOOP Loop while the CX register is not zero Repeatedly execute a sequence of instructions The number of times the loop is repeated is stored in the CX register. LOOPZ Loop while zero Repeatedly execute a sequence of instructions The maximum

number of times the loop is repeated is stored in the CX register The loop is terminated before the count in CX reaches zero if the Zero Flag (ZF) is set.

LOOPE Loop while equal

LOOPNZ Loop while not zero Repeatedly execute a sequence of instructions The maximum

number of times the loop is repeated is stored in the CX register The loop is terminated before the count in CX reaches zero if the Zero Flag (ZF) is cleared.

LOOPNE Loop while not equal

JCXZ Jump on CX zero If the previous instruction leaves 0 in the CX register, then control is transferred to the address of the instruction pointed to by the

operand.

INT Generate interrupt

The current instruction sequence is suspended and the sor Status Flags, the Instruction Pointer (IP) register and the CS register are pushed onto the stack Instruction continues at the memory address stored in appropriate interrupt vector location IRET Return from interrupt Restores the contents of the Flags register, the IP and the CS register

Proces-Although the list of possible conditional jumps is long and impressive, you should note that most of the mnemonics are synonyms and test the same status flag conditions Also, the set of JUMP-type instructions needs further explanation because of the segmentation method of memory addressing Jumps can be of two types, depending upon how far away the destination of the jump resides from the present location of the jump instruction If you are jumping to another location in the same region of memory pointed to by the current value of the CS register then you are executing an

intrasegment jump Conversely, if the destination of the jump is beyond the span of the CS pointer,

then you are executing an intersegment jump Intersegment jumps require that the CS register is

also modified to enable the jump to cover the entire range of physical memory

The operand of the jump may take several forms The following are operands of the jump instruction:

• Short-label: An 8-bit displacement value The address of the instruction identified by

the label is within the span of a signed 8-bit displacement from the address of the jump instruction itself

• Near label: A 16-bit displacement value The address of the instruction identified by the

label is within the span of the current code segment The value of

• Memptr16 or Regptr16: A 16-bit offset value stored in a memory location or a register

The value stored in the memory location or the register is copied into the IP register and forms the offset portion of the next instruction to be fetched from memory The value in the CS register is unchanged, so this type of an operand can only lead to a jump within the current code segment

• Far-label or Memptr32: The address of the jump operand is a 32-bit immediate value

The first 16-bits are loaded into the offset portion of the IP register The second 16-bits are loaded into the CS register The memptr32 operand may also be used to specify a double

word length indirect jump That is, the two successive 16-bit memory locations specified

by memptr32 contain the IP and CS values for the jump address Also, certain register pairs, such as DS and DX may be paired to provide the CS and IP values for the jump The type of jump instruction that you need to use is normally handled by the assembler, unless you override the default values with assembler directives Well discuss this point later on this chapter

Assembly Language Programming the 8086 Architecture

The principles of assembly language programming that we’ve covered in the previous chapters are no different then those of the 68K family However, while the principles may be the same, the implementation methods are somewhat different because:

1 the 8086 is so deeply linked to the architecture of the PC and its operating systems,

2 the segmented memory architecture requires that we declare the type of program that we

intend to write and specify a memory model for the opcodes that the assembler is going to

be able to write assembly language programs that are well-behaved Certainly these programs can run on any machine that is still running the 16-bit compatible versions of the various PC operating systems The newer, 32-bit versions are more problematic because the run older DOS programs in

an emulation mode which may or may not recognize the older BIOS calls However, most simple assembly language programs which do simple console I/O should run without difficulty in a DOS window Being a true Luddite, I still have my trusty 486 machine running good old MS-DOS, even though I’m writing this text on a system with Windows XP

Let’s first look at the issue of the segment directives and memory models In general, it is sary to explicitly identify the portions of your program that will deal with the code, the data and the stack This is similar to what you’ve already seen We use the directives:

The .data directive identifies the data space of your program For example, you might have the following variables in your program:

data

var16 dw 0AAAAh

var8 db 55h

initMsg db ‘Hello World’,0Ah,0Dh

This data space declares three variables, var16, var8 and initMsg and initializes them In order for

you to use this data space in your program you must initialize the DS segment register to address

of the data segment But since you don’t know where this is, you do it indirectly:

MOV AX,@data ;Address of data segment

MOV DS,AX

Here, @data is a reserved word that causes the assembler to calculate the correct DS segment value The .code directive identifies the beginning of your code segment The CS register will initialized

to point to the beginning of this segment whenever the program is loaded into memory

In addition to identifying where in memory the various program segments will reside you need to provide the assembler (and the operating system with some idea of the type of addressing that will

be required and the amount of memory resources that your program will need You do this with the .model directive Just as we’ve seen with the different types of pointers needed to execute

an intrasegment jump and an intersegment jump, specifying the model indicates the size of your program and data space requirements The available memory models are3:

• Tiny: Both program code and data fit within the same 64K segment Also, both code and data are defined as near, which means that they are branched to by reloading the IP register.

• Small: Program code fits entirely within a single 64K segment and the data fits entirely

within a separate 64K segment Both code and data are near

• Medium: Program code may be larger than 64K but program data must be small enough

to fit within a single 64K segment Code is defined as far, which means that both segment

and offset must be specified while data accesses are all near

• Compact: Program code fits within a single 64K segment but the size of the data may

exceed 64K, with no single data element, such as an array, being larger than 64K Code accesses are near and data accesses are far

• Large: Both code and data spaces may be larger than 64K However, no single data array

may be larger than 64K All data and code accesses are far

• Huge: Both code and data spaces may be larger than 64K and data arrays may be larger

than 64K Far addressing modes are used for all code, data and array pointers

The use of memory models is important because they are consistent with the memory models used

by compilers for the PC It guarantees that an assembly language module that will be linked in with modules written in a high level language will be compatible with each other

Let’s examine a simple program that could run on in a DOS emulation window on your PC

.MODEL small

.STACK 100h

PrnStrg db ‘Hello World$’ ;String to print

.CODE

Start:

mov ax,@data ;set data segment

mov ds,ax ;initialize data segment register

mov dx,OFFSET PrnStrg ;Load dx with offset to data

mov ah,09 ;DOS call to print string

int 21h ;call DOS to print string

mov ah,4Ch ;prepare to exit

int 21h ;quit and return to DOS

END Start

As you might guess, this program represents the first baby steps of 8086 assembly language gramming You should be all teary-eyed, recalling the very first C++ program that you actually got

pro-to compile and run

We are using the ‘small’ memory model, although the ‘tiny’ model would work just as well We’ve reserved 256 bytes for the stack space, but it is difficult to say if we’ve used any stack space at all, since we didn’t make any subroutine calls

The data space is defined with the data directive and we define a byte string, “Hello World$” The

‘$’ is used to tell DOS to terminate the string printing Borland7 suggests that instruction labels

be on lines by themselves because it is easier to identify a label and if an instruction needs to be added after the label it is marginally easier to do However, the label may appear on the same line

as the instruction that it references Labels which reference instructions must be terminated with

a colon and labels which reference data objects do not have colons Colons are not used when the label is the target in a program, such as a for a loop or jump instruction

The reserved word, offset, is used to instruct the assembler to calculate the offset from the

instruc-tion to the label, ‘PrnStrg’ and place the value in the DX register This completes the code that is necessary to completely specify the segment and offset of the data string to print Once we have established the pointer to the string, we can load the AH register with the DOS function call to print a string, 09 The call is made via a software interrupt, INT 21h, which has the same function

as the TRAP #15 instruction did for the 68K simulator

The program is terminated by a DOS termination call (INT 21h with AH = 4Ch) and the END reserved word tells the assembler to stop assembling The label following the END directive tells the assembler where program execution is to begin This can be different from the beginning of the code segment and is useful if you want to enter the program at some place other than the begin-ning of the code segment

System Vectors

Like the 68K, the first 1K memory addresses are reserved for the system interrupt vectors and exceptions In the 8086 architecture, the interrupt number is an 8-bit unsigned value from 0 to 255 The interrupt operand is shifted left 2 times (multiplied by 4) to obtain the address of the pointer

to the interrupt handler code Thus, the INT 21h instruction would cause the processor to vector through memory location 00084h to pick-up the 4 bytes of the segment and offset for the operating

system entry point In this case, the IP offset would be located at word address 00084h and the CS pointer would be located at word address 00086h The function code, 09 in the AH register cause DOS to print the string pointed to by DS:DX.

System Startup

An 8086-based system comes out of RESET with all the registers set equal to zero with the exception of the CS register, which is set equal to 0FFFFh Thus, the physical address of the first instruction fetch would be 0FFFFh:0000, or 0FFFF0h This is an address located 16-bytes from the top of physical memory Thus, an 8086 system usually has nonvolatile memory located in high memory so that it contains the boot code when the processor comes out of RESET Once, out of RESET, the 16 bytes is enough to execute a few instructions, including a jump to the beginning of the actual initialization code Once into the beginning of the ROM code, the system will usually initialize the interrupt vectors in low memory by writing their values to RAM, which occupies the low memory portion of the address space

Wrap-Up

You may either be overjoyed or disappointed that this chapter is coming to an end After all, we dissected the 68K instruction set and looked at numerous assembly language programming exam-ples In this chapter we looked at numerous code fragments and only one, rather trivial, program What gives?

Earlier in the text we were both learning the fundamentals of assembly language programming and learning a computer’s architecture at the same time The architecture of the 68K family itself

is fairly straight-forward and allows us to focus on basic principles of addressing and algorithms The 8086 architecture is a more challenging architecture to absorb, so we delayed its introduction until later in the text Now that you’ve been exposed to the general methods of assembly language programming, we could focus our efforts on mastering the intricacies of the 8086 architecture itself Anyway, that’s the theory

In the next chapter we’ll examine a third architecture that, once again, you may find either very refreshing or very frustrating, to work with Frustrating because you don’t have all the power-ful instructions and addressing modes to work with that you have with the 8086 architecture; and refreshing because you don’t have all of the powerful and complex instructions and addressing modes to master

Summary of Chapter 10

Chapter 10 covered:

• The basic architecture of the 8086 and 8088 microprocessors

• 8086 memory models and addressing

• The instruction set architecture of the 8086 family

• The basics of 8086 assembly language programming

Chapter 10: Endnotes

1 Daniel Tabak, Advanced Microprocessors, Second Edition, ISBN 0-07-062843-2, McGraw-Hill, NY, 1995, p 186.

2 Advanced Micro Devices, Inc, Am186™ES and Am188™ES User’s Manual, 1997, p 2-2.

3 Borland,Turbo Assembler 2.0 User’s Guide, Borland International, Inc Scotts Valley, 1988.

4 Advanced Micro Devices, Inc, Am186™ES and Am188™ES Instruction Set Manual, 1997.

5 Walter A Triebel and Avatar Singh, The 8088 and 8086 Microprocessors, Third Edition, ISBN 0-13-010560-0,

Prentice-Hall, Upper Saddle River, NJ, 2000 Chapters 5 and 6.

6 Intel Corporation, 8086 16-Bit HMOS Microprocessor, Data Sheet Number 231455-005, September 1990, pp 25–29.

7 Borland, op cit, p 83.

1 The contents of memory location 0C0020h = 0C7h and the contents of memory location 0C0021h = 15h What is the word stored at 0C0020h? Is it aligned or nonaligned?

2 Assume that you have a pointer (segment:offset) stored in memory at byte addresses 0A3004h through 0A3007h as follows:

<0A3004h> = 00

<0A3005h> = 10h

<0A3006h> = 0C3h

<0A3007h> = 50h

Express this pointer in terms of segment:offset value

3 What would the offset value be for the physical memory address 0A257Ch if the contents of the segment register is 0A300h?

4 Convert the following assembly language instructions to their object code equivalents:

MOV AX,DX

MOV BX[SI],BX

MOV DX,0A34h

5 Write a simple code snippet that:

a Loads the value 10 into the BX register and the value 4 into the CX register,

b executes a loop that increments BX by 1 and decrements CX until the <CX> = 00

6 Load register AX with the value 0AA55h and then swap the bytes in the register

7 What is are the contents of the AX register after the following two instructions are executed?MOV AX,0AFF6h

ADD AL,47h

8 Suppose you want to perform the mathematical operation X = Y*Z, where:

X is a 32-bit unsigned variable located at offset address 200h,

Y is a 16-bit unsigned variable located at address 204h,

Z is a 16-bit unsigned variable located at address 206h,

write an 8086 assembly language code snippet that performs this operation

9 Write a program snippet that moves 1000 bytes of data beginning at address 82000H to address 82200H

10 Modify the program of problem 9 so that the program moves 1000 bytes of data from 82000H

to C4000H

Exercises for Chapter 10

C H A P T E R 11

The ARM Architecture

Objectives

When you are finished with this lesson, you will be able to:

 Describe the processor architecture of the ARM family;

 Describe the basic instruction set architecture of the ARM7 processors;

 Describe the differences and similarities between the ARM architecture and the 68000

architecture;

 Write simple code snippets in ARM assembly language using all addressing modes and

instructions of the architecture.

Introduction

We’re going to turn our attention away from the 68K and 8086 architectures and head in a new direction You may find this change of direction to be quite refreshing because we’re going to look

at an architecture that may be characterized by how it removed all but the most essential

instruc-tions and addressing modes We call a computer that is built around this architecture a RISC computer, where RISC is an acronym for Reduced Instruction Set Computer The 68K and the

8086 processors are characteristic of an architecture called Complex Instruction Set Computer, or CISC. We’ll compare the two architectures in a later chapter For now, let’s just march onward and learn the ARM architecture as if we never heard of CISC and RISC

In 1999 the ARM 32-bit architecture finally overtook the Motorola 68K architecture in terms of popularity1 The 68K architecture had dominated the embedded systems world since it was first invented, but the ARM architecture has emerged as today’s most popular, 32-bit embedded proces-sor Also, ARM processors today outsell the Intel Pentium family by a 3 to 1 margin2 Thus, you’ve just seen my rationale for teaching these 3 microprocessor architectures

If you happen to be in Austin, Texas you could head to the south side of town and visit AMD’s impressive silicon foundry, FAB 25 In this modern, multibillion dollar factory, silicon wafers are converted to Athlon microprocessors A short distance away, Freescale’s (Motorola) FAB (fabrication facility) cranks out PowerPC® processors Intel builds its processors in FABs in Chandler, Arizona and San Jose, CA, as well as other sites worldwide Where’s ARM’s FAB located? Don’t fret, this is

a trick question ARM doesn’t have a FAB ARM is a FABless manufacturer of microprocessors.ARM Holdings plc was founded in 1990 as Advanced RISC Machines Ltd.3 It was based in the United Kingdom as a joint venture between Acorn Computer Group, Apple and VLSI Technology

ARM does not manufacture chips in its own right It licenses its chip designs to partners such as VLSI Technology, Texas Instruments, Sharp, GEC Plessey and Cirrus logic who incorporate the ARM processors in custom devices that they manufacture and sell It was ARM that created this

model of selling Intellectual Property, or IP, rather than a silicon chip mounted in a package In

that sense it is no different then buying software, which, in fact, it is A customer who wants to

build a system-on-silicon, such as a PDA/Cell phone/Camera/MP3 player would contract with VLSI

technology to build the physical part VLSI, as an ARM licensee, offers the customer an encrypted library in a hardware description language, such as Verilog Together with other IP that the customer may license, and IP that they design themselves, a Verilog description of the chip is created that VLSI can use to create the physical part Thus, you can see with the emergence of companies like ARM, the integrated circuit design model predicted by Mead and Conway has come true

Today, ARM offers a range of processor designs for a wide range of applications Just as we’ve done with the 68K and the 8086, we’re going to focus our efforts on the basic 32-bit ARM archi-tecture that is common to most of the products in the family

When we talk about the ARM processor, we’ll often discuss it in terms of a core The core is the

naked, most basic portion of a microprocessor When systems-on-silicon (or systems-on-chip) are designed, one or more microprocessor cores are combined with peripheral components to create an entire system design on a single silicon die Simpler forms of SOCs have been around for quite a

while Today we call these commercially available parts microcontrollers Both Intel and Motorola

pioneered the creation of microcontrollers Historically, a semiconductor company, such as ola, would develop a new microprocessor, such as the 68K family and sell the new part at a price premium to those customers who were doing the leading edge designs and were willing to pay a price premium to get the latest processor with the best performance

Motor-As the processor gained wider acceptance and the semiconductor company refined their tion processes, they (the companies) would often lift the CPU core and place it in another device that included other peripheral devices such as timers, memory controllers, serial ports and paral-lel ports These parts became extremely popular in more cost- conscious applications because of their higher level of integration However, a potential customer was limited to buying the particular parts from the vendor’s inventory If the customer wanted a variant part, they either bought the closest part they could find and then placed the additional circuitry on a printed circuit board, or worked with the vendor to design a custom microcontroller for their products

fabrica-Thus, we can talk about Motorola Microcontrollers that use the original 68K core, called

CPU16, such as the 68302, or more advanced microcontrollers that use the full 32-bit 68K core

(CPU32) in devices such as the 68360 The 80186 processor from Intel uses the 8086 core and the

SC520 (Elan) from AMD uses the 486 core to build an entire PC on a single chip The original PalmPilot® used a Motorola 68328 microcontroller (code name Dragonball) as its engine Thus, since all of the ARM processors are themselves cores, to be designed into systems-on-chip, we’ll continue to use that terminology

ARM Architecture

Figure 11.1 is a simplified schematic diagram of the ARM core architecture Data and instructions come in and are routed to either the instruction decoder or to one of general purpose registers,