Hardware and Computer Organization- P10 potx

The op-code word contains an opcode, which tells the computer what to do, and it also contains zero, one or two effective address ﬁelds EA.. The effective address ﬁelds contain the enco

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Chapter 9

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=1

->MOVE.L 8(A6),D0

PC=000474 SR=2000 SS=00000FE0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0

D0=00000001 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->ADD.L (A0),D0

PC=000476 SR=2000 SS=00000FE0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0

D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->BRA.L $0000047A

PC=00047A SR=2000 SS=00000FE0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->NOP

PC=00047C SR=2000 SS=00000FE0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->UNLK A6

PC=00047E SR=2000 SS=00000FE4 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FE4 Z=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->RTS

PC=000430 SR=2000 SS=00000FE8 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FE8 Z=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->ADDQ.L #8,SP

PC=000432 SR=2000 SS=00000FF0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0

OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC

1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8

OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC

OFE8 00 00 00 01 OFE4 00 00 04 30

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A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0

D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B4 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->ADDQ.L #1,D3

PC=000436 SR=2000 SS=00000FF0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0

D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B5 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->NOP

PC=000438 SR=2000 SS=00000FF0 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0

D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B5 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->MOVE.L (SP)+,D2

PC=00043A SR=2004 SS=00000FF4 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF4 Z=1

D0=000015B4 D1=00000FF8 D2=00000000 D3=000015B5 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->MOVE.L (SP)+,D3

PC=00043C SR=2004 SS=00000FF8 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000FFC A7=00000FF8 Z=1

D0=000015B4 D1=00000FF8 D2=00000000 D3=00000000 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->UNLK A6

PC=00043E SR=2004 SS=00001000 US=00000000 X=0

A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0

A4=00000000 A5=00000000 A6=00000000 A7=00001000 Z=1

D0=000015B4 D1=00000FF8 D2=00000000 D3=00000000 V=0

D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0

->RTS

You may be curious why the last instruction is an RTS If this

pro-gram were running under an operating system, and the C compiler

expects that you are, this instruction would return the control to the

operating system

There’s one last matter to discuss before we leave 68000 assembly

language and move on to other architectures This is the subject of

instruction set decomposition We’ve already looked at the

archi-tecture from the point of view of the instruction set, the addressing

OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC

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Chapter 9

modes and the internal register resources Now, we’ll try to relate that back to our discussion of state machines to see how the actual encoding of the instructions takes place

The process of converting machine language back to assembly language is called disassembly A

disassembler is a program that examines the machine code in memory and attempts to convert it back to machine language This is an extremely useful tool for debugging and, in fact, most debug-gers have a built-in disassembly feature

You may recall from our introduction to assembly language that the ﬁrst word of an instruction is

called the opcode word The op-code word contains an opcode, which tells the computer (what to do), and it also contains zero, one or two effective address ﬁelds (EA) The effective address ﬁelds

contain the encoded information that tell the processor how to retrieve the operands from memory

In other words, what is the effective address of the operand(s)

As you already know, an operand might be an address register or a data register The operand might be located in memory, but pointed to by the address register Consider the form of the instructions shown below:

DB15 DB12 DB11 DB6 DB5 DB0

The op code ﬁeld consists of 4 bits, DB12 through DB15 This tells the computer that the tion is a MOVE instruction That is, move the contents of the memory location speciﬁed by the

instruc-source EA to the memory location speciﬁed by the destination EA Furthermore, the effective

address field is further decomposed into a 3-bit Mode field and a 3-bit Subclass (register) field This information is sufficient to tell the computer everything it needs to know in order to com-

plete the instruction, but the op-code word itself may or may not contain all of the information

necessary to complete the instruction. The computer may have to go out to memory one or more additional times to fetch additional information about the source EA or the destination EA in order

to complete the instruction This begins to make sense if we recall that the op-code word is the part

of the instruction that must be decoded by the microcode-driven state machine Once the proper state machine sequence has been established by the decoding of the op-code word, the additional fetching of operands from memory, if necessary, can proceed

For example, suppose that the source EA and destination EA are both data registers In other words, the instruction is:

MOVE.W D0,D1

Since both the source and the destination are internal registers, there is no additional information needed by the processor to execute the instruction For this example, the instruction is the same length as the op code, 16-bits long, or one word in length

However, suppose that the instruction is:

MOVE.W #$00D0,D1

Now the # sign tells us that the source EA is an immediate operand (the hexadecimal number

$00D0 ) and the destination EA is still register D1 In this case, the op code word would tell us that the source is an immediate operand, but it can’t tell us what is the actual value of the immediate operand The computer must go out to memory again and retrieve (fetch) the next word in memory

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ory location $1000, the op code word would take up word address $1000 and the operand would

be at memory location $1002

The effective address field is a 6-bit wide field that is further subdivided into two, 3-bit fields called

mode and register The 3-bit wide mode field can specify one of 8 possible addressing modes and the register filed can specify one of 8 possible registers, or a subclass for the mode field.

The MOVE instruction is unique in that it has two possible effective address fields All of the other instructions that may contain an effective address field have only one possible effective address This might seem strange to you at first, but as you’ll see, almost all of the other instructions that use two operands must involve a register and a single effective address

Let’s return our attention to the MOVE instruction If we completely break it down to its ent parts it would look like this:

constitu-0 constitu-0 Size Destination Register Destination Mode Source Mode Source Register

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

The subclasses are only used with mode 7 addressing modes These modes are:

You may have noticed the Move to Address

Register (MOVEA) instruction and wondered

why we needed to create a special mnemonic for

an ordinary MOVE instruction Well ﬁrst of all,

address registers are extremely useful and

impor-tant internal resources Having an address register

means that we can do register arithmetic and manipulate pointers We can also compare the values

in registers and make decisions based upon the address of data

The MOVEA instruction is a more standard type of instruction because there is only one effective address for the source operand The destination operand is one of the 7 address registers Thus, the destination mode is hard coded to be an address register However, we needed to create a special instruction for the MOVEA operation because a word fetch on an odd byte boundary is an illegal access and the MOVEA instruction prevents this from occuring

The majority of the instructions take the form shown below

Single operand instructions, such as CLR (set the contents of the destination EA to zero) have a slightly different form

PC relative with displacement 010

PC relative with index 011

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Chapter 9

The JMP (Jump) and JSR (Jump to Subroutine) are also single operand instructions Both place the destination EA into the program counter so that the next instruction is fetched from the new location, rather than the next instruction in the sequence The JSR instruction will also automati-cally place the current value of the program counter onto the stack before the contents of the PC are replaced with the destination EA Thus, the return location is saved on the stack

The branch instructions, Bcc (branch on condition code), is similar to the jump instruction in that

it modiﬁes the contents of the PC so that the next instruction may be fetched out of sequence However, the branch instructions differ in two fundamental ways:

1 There is no effective address A displacement value is added to the current contents of

the PC so that the new value is determined as a positive or negative shift from the current value Thus, a displacement is a relative jump, rather than an absolute jump

2 The branch is taken only if the condition code being tested evaluates to true

DB15 DB12 DB11 DB8 DB7 DB0

The displacement ﬁeld is an 8-bit value This means that the branch can move to another locations either +127 bytes or –128 bytes away from the present location If a greater branch is desired, then the displacement ﬁeld is set to all zeroes and the next memory word is used as an immediate value for the displacement This gives a range of +16,383 to –16,384 bytes

Thus, if the computer is executing a tight loop, then it will operate more efﬁciently if an 8-bit displacement is used The 16-bit displacement allows it go further on a branch, but at a cost of an additional memory fetch operation

Earlier, I said that the branch is executed if the condition code evaluates to true This means that

we can test more than just the state of one of the ﬂags in the CCR The table below shows us the possible ways that a branch condition may be evaluated

CC carry clear 0100 C LS low or same 0011 C + Z

CS carry set 0101 C LT less than 1101 N*V + N*V

GE greater or equal 1100 N*V + N*V NE not equal 0110 Z

GT greater than 1110 N*V*Z + N*V*Z PL plus 1010 N

LE less or equal 1111 Z + N*V + N*V VS overflow set 1001 V

The reason for so many branch test conditions is that the branch instructions BGT, BGE, BLT and

BLE are designed to be used with signed arithmetic operations and the branch instructions BHI,

BCC, BLS and BCS are designed to be used with unsigned arithmetic operations

Some instructions, such as NOP and RTS (Return from Subroutine) take no operands and are pletely speciﬁed by their op code word

com-Earlier we discussed the role of the op mode field on how a general instruction operation may be further modified A good example to illustrate how the op mode field works is to examine the ADD instruction and all of its variations in more detail Consider Figure 9.3

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Notice how the op mode ﬁeld,

contained in bits 6, 7 and 8,

de-ﬁne the format of the instruction

The ADD instruction is

represen-tative of most of the “normal”

instructions Other

classes of instructions require

special consideration For

exam-ple, the MOVE instruction contains

two effective addresses Also,

all immediate addressing mode

instructions have the source

oper-and addressing mode hard-coded

into the instruction and thus, it

is not really an effective address

This would include instructions such as add immediate (ADDI) and subtract immediate (SUBI)

Example of a Real Machine

Before we move on to consider other architectures let’s do something a bit different, but still relevant to our discussion of assembly code and computer architecture Up to now, we’ve really ignored the fact that ultimately the code we write will have to run on a real machine Granted, memory test programs aren’t that exciting, but at least we can imagine how they might be used with actual hardware

In order to conclude our

discussion of assembly

language coding, let’s

look at the design of

an actual 68000-based

system

Figures 9.4 and 9.5 are

simpliﬁed schematic

diagrams of the processor

and memory portions of

a 68K computer system

Not all the signals are

shown, but that won’t

take anything away from

the discussion Also, we

don’t want the EE’s

get-ting too upset with us

Figure 9.3 Op mode decomposition for the ADD instruction

ADD.W Dn,<ea>

ADD.L Dn,<ea>

ADDA.W <ea>,An ADDA.L <ea>,An

CS ROM H CS ROM L CS RAM H CS RAM L

WRITE

READ RESET

GENERATOR

16 MHz Clock

TO I/O

ADDRESS DECODER

INT7 INT5 INT3 INT1

A1 A23

D0 D15

D0 A17 A18 A20 A22

AS

UDS LDS DTACK BERR CLK IN RESET IPL2 IPL1 IPL0 WR

RAM SELECT ROM SELECT

Note: Not all 68000 signals are shown

Figure 9.4 Simpliﬁed schematic diagram of a 68000-based computer system Only the 68000 CPU is shown in this ﬁgure

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The Valid Address signal in the 68K environment is called Address Strobe and is labeled AS in the

diagram This signal is routed to two places It is used as a qualifying signal for the READ and WRITE operations and is gated through the two lower OR gates in the ﬁgure (keep thinking, “ negative logic AND gates” ) and to the ADDRESS DECODER block You should have no trouble identifying this functional block and how it works In a pinch, you could probably design it your-self! Thus, we will not decode an address range until the AS signal is asserted LOW, guaranteeing

a valid address The I/O decoder also decodes our I/O devices, although they aren’t shown in this ﬁgure

Since the 68K does not have separate READ and WRITE signals, we synthesize the READ signal with the NOT gate and the OR gate We also use the OR gate and the AS signal to qualify the READ and WRITE signals, with the OR gate functioning as a negative logic AND gate Strictly speaking this isn’t necessary because we are already qualifying the ADDRESS DECODER in the same way

Figure 9.5 Simpliﬁed schematic diagram of the memory system for the 68K computer of Figure 9.4.

READ

A1 A17

D0 D16

A0 A2 A3 A5 A7 A9 A10 A12 A14 A15

CS OE

A0 A2 A3 A5 A7 A9 A10 A12 A14 A15

D0 D2 D4 D6

~CS ~OE

A0 A2 A3 A5 A7 A9 A10 A12 A14 A15

D0 D2 D4 D6

CS OE

A0 A2 A3 A5 A7 A9 A10 A12 A14 A15

D0 D2 D4 D6

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The last block of note is the Interrupt Controller block at the bottom left hand side of the diagram The 68K uses 3 active LOW interrupt inputs labeled IP0, IP1 and IP2 All three lines going low would signal a level 7 interrupt We’ll study interrupts in the next chapter The inputs to the Inter-rupt Controller are 7 active low inputs labels INT1 – INT7 If the INT7 line was brought LOW, all

of the output lines would also go LOW, indicating that INT7 is a level 7 interrupt Now, if INT6 is low ( IP0 = 1, IP1 = 0, IP2 = 0 ) and INT5 also went LOW, the outputs wouldn’t change because the Interrupt controller both decodes the interrupt inputs and prioritizes them

Figure 9.5 is the memory side of the computer It is made up of two 128K × 8 RAM chips and two 128K x 8 ROM chips Notice how the pairing of the devices and the two chip-select signals from the processor gives us byte writing control The rest of this circuit should look very familiar to you.The memory system in this computer design consists of 256K bytes of ROM, located at address

$000000 through $3FFFF The RAM is located at address $100000 through address $13FFFF This address mapping is not obvious from the simpliﬁed schematic diagrams because you do not know the details of the circuit block labeled ‘Address Decoder” in Figure 9.4

Summary of Chapter 9

Chapter 9 covered:

• The advanced addressing modes of the 68K architecture and their relationship to level languages

high-• An overview of the classes of instructions of the 68K architecture

• Using the TRAP #15 instruction to simulated I/O

• How a program, written in C executes in assembly language and how the C compiler makes use of the advanced addressing modes of the 68K architecture

• How program disassembly is implemented and its relation to the architecture

• The functional blocks of a 68K-based computer system

Chapter 9: Endnotes

1 Alan Clements, 68000 Family Assembly Language, ISBN 0-534-93275-4, PWS Publishing Company, Boston, 1994,

p 704

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1 Examine the block of assembly language code shown below

a What is the address of the memory location where the byte, FF, is stored in the indicated instruction?

b Is this code segment relocatable? Why?

per-00001000 41F9 00001018 10 START: LEA DATA+2,A0

00001006 2C50 11 MOVEA.L (A0),A6

00001008 203C 00001B00 12 MOVE.L #$00001B00,D00000100E 2C00 13 MOVE.L D0,D6

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00000422 60FE STOP_HERE: BRA STOP_HERE

4 Answer the following questions in a sentence or two

a Why do local variables go out of scope when a C++ function is exited?

b Give two reasons why variables in high level languages, such as C, must be declared fore they can be used?

be-c The 68000 assembly language instructions, LINK and UNLK would be representative of instructions that are created in order to support a high-level language Why?

5 The following is a display of 32 bytes of memory that you might see from a “display memory” command in a debugger What are the 3 instructions shown in this display?

00000400 06 79 55 55 00 00 AA AA 06 B9 AA AA 55 55 00 00

00000410 FF FE 06 40 AA AA 00 00 FF 00 00 00 00 00 00 00

6 Assume that you are trying to write a disassembler program for 68K instructions in memory Register A6 points to the opcode word of the next instruction that you are trying to disassem-ble Examine the following algorithm Describe in words how it works For this example, you may assume that <A6> = $00001A00 and <$00001A00> = %1101111001100001

MOVE.B #shift,D1 *Shift 12 bits to the right

{ Other instructions }

JMP code0001 JMP code0010 JMP code0011 JMP code0100 JMP code0101 JMP code0110 JMP code0111 JMP code1000 JMP code1001 JMP code1010

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Chapter 9

JMP code1011 JMP code1100 JMP code1101 JMP code1110 JMP code1111

7 Convert the memory test program from Chapter 9, exercise #9, to be relocatable In order to see if you’ve succeeded write the program as follows:

a ORG the program at $400

b Add some code at the beginning so when it begins to execute, it relocates itself to the memory region beginning at $000A0000

c Test the memory region from $00000400 to $0009FFF0

d Make sure that you locate your stack so that it is not overwritten

8 This exercise will extend your mastery of the 68K with the introduction of several new cepts to the memory test exercise from chapter 8 It will also be a good exercise for structuring your assembly code with appropriate subroutines The exercise introduces the concept of user I/O through the use of the TRAP #15 instruction You should read up on the TRAP #15 instructions by studying the HELP facility that comes with the E68K program Alternatively, you can read up on the details of the TRAP #15 instruction on page 704 of the Clements1 text.The TRAP #15 instruction is an artifact of the simulator It was designed to allow I/O to take place between the simulator and the user If you were really writing I/O routines, you probably would do some things differently, but lots of the things are the same

con-Associated with the TRAP #15 instruction are various tasks Each task is numbered and ciated with each task is an API that explains how it does its work For example, task #0 prints a string to the display and adds a newline character so that the cursor advances to the beginning

asso-of the next line In order to use task #0 you must set up the following registers (this is the API):

• D0 holds the task number as a byte

• The address of the beginning of the string is held in A1

• The length of the string to print is stored as a word in D1

Once you’ve set-up the three registers you then call TRAP #15 as an instruction and you’re message is printed to the display Here’s a sample program that illustrates how it works To output the string, “Hello world!”, you might use the following code snippet:

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MOVE.W str_len,D1 *Get the length of the string TRAP #15 *Do it

STOP #$2700 * Back to simulator

* Data area

string DC.B ‘Hello world’ * Store the message here

str_len DC.W str_len-string *Get the length of the string END $400

Task #1 is almost identical to task #0 except that it does not print the newline character This is handy when you want to prompt the user to enter information So, you would issue a prompt using task #1 rather than task #0

Also, you might want to get information from the user Such as, “Where do they want to run the memory test and what test pattern do they want to use?” Also, you might ask them if they want to run the test again with a different pattern

Problem Statement

1 Extend the memory test program (Chapter 9, exercise #9) to enable a user to enter the starting address of the memory test, the ending address of the memory test, and the word pattern to use for the test Only the input test pattern will be used There is no need to complement the bits or

do any other tests

2 The region of memory that may be tested will be between $00001000 and $000A0000

3 The program ﬁrst prints out a test summary heading with the following information:

ADDRESS DATA WRITTEN DATA READ

4 Every time an error occurs you will print the address of the failed location, the data pattern that you wrote and the data pattern that you read back

5 Locate your stack above $A0000

6 When the program start running it prompts the user to enter the starting address (above

$00001000) of the test The user enters the starting address for the test The program then prompts the user for the ending address of the test (below $FFFF) The user enters the address Finally, the program prompts the user for the word pattern to use for the test

You must check to see that the ending address is at least 1 word lengths away from the ing address and is greater than the starting address You do not have to test for valid numeric entries You may assume for this problem that only valid addresses and data values will be entered Valid entries are the numbers 0 through 9 the lower case letters a through f and the upper case letters A through F

start-Once this information is entered, the test summary heading line is printed to the display and the testing beings Any errors that are encountered are printed to the display as described above

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C H A P T E R 10

The Intel x86 Architecture

Objectives

When you are ﬁnished with this lesson, you will be able to:

 Describe the processor architecture of the 8086 and 8088 microprocessors;

 Describe the basic instruction set architecture of the 8086 and 8088 processors;

 Address memory using segment:offset addressing techniques;

 Describe the differences and similarities between the 8086 architecture and the 68000

of Intel’s Zilog was formed by Intel employees who worked on the original Intel 8080 processor Zilog produced a code-compatible enhancement of the 8080, the Z80 The Z80 executed all of the

8080 instructions plus some additional instructions It was also somewhat easier to interface to then the 8080

Hobbyists embraced the Z80 and it became the processor of choice for almost all of the early PCs built upon the CP/M operating system developed by Gary Kidall at Digital Research Corporation Zilog was rumored to be working on a 16-bit version of the Z80, the Z800, which promised dramatic performance improvement over the 8-bit Z80 IBM initially approached Zilog as the possible CPU supplier for the PC-XT Today, it could be agued that Intel rose to that position of prominence because Zilog could not deliver on its promised delivery date to IBM

In 1978 Intel had a 16-bit successor to the 8080, the 8086/8088 The 8088 was internally identical

to the 8086 with the exception of an 8-bit eternal data bus, rather than 16-bit Certainly this would limit the performance of the device, but to IBM it had the attractive feature of signiﬁcantly lower-ing the system cost Intel was able to meet IBM’s schedule and a 4.077 MHz 8088 CPU deputed in the original IBM PC-XT computer For an operating system, IBM chose a 16-bit CP/M look-alike from a small Seattle software company called, Microsoft Although Zilog survived to this day, they never recovered from their inability to deliver the Z800 This should be a lesson that all software

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Chapter 10

developers who miss their delivery targets should take this classic example of a missed schedule delivery to heart As a post-script, the original Z80 also survives to this date and continues to be used as an embedded controller It is hard to estimate its impact, but there must be billions of lines

of Z80 code still being used in the world

The growth of the PC industry essentially tracked Intel’s continued development and ongoing reﬁnement of the x86 architecture Intel introduced the 80286 as a follow-on CPU and IBM intro-

duced the PC-AT computer which used it The 80286 introduced the concept of protected mode,

which enabled the operating system to begin to employ task management, so that MS-DOS, which was a single tasking operating system, could now be extended to allow crude forms of multitask-ing to take place The 80286 was still a 16-bit machine During this period Intel also introduced the 80186/80188 integrated microcontroller family These were CPUs with 8086/8088 cores and additional on-chip peripheral devices which made the device extremely attractive as a one-chip solution for many embedded computer products Among the on-chip peripherals are:

• 2 direct memory access controllers (DMA)

• Three 16-bit programmable timers

• Clock generator

• Chip select unit

• Programmable Control Registers

The 80186/188 family is still extremely popular to this day, with other semiconductor companies building even more highly integrated variants, such as the E86™ family from Advanced Micro Devices (AMD) and the V-series from NEC In particular, the combination of peripheral devices made the 186 families very attractive to disk drive manufacturers for controllers

With the introduction of the 80386 the x86 architecture was ﬁnally extended to 32 bits The PC world responded with hardware and software ( Windows 3.0 ) which rallied around this architec-ture The follow on processors to the 80386, the 80486 and Pentium families, continued to evolve the basic architecture deﬁned in the i386

Our interest in this family leads us to step back from the i386 architecture and to focus on the original 8086 family architecture This architecture will provide us with a good point of reference for trying to gain a comparative understanding of the 68000 versus the 8086 While the 68000 is usually speciﬁed as a 16/32-bit architecture, the 8086 is also capable of doing many 32-bit opera-tions as well Also, the default operand size for the 68K is 16-bits, so the relative comparison of the two architectures is reasonably valid

Therefore, we will approach our look at the x86 family from the perspective of the 8086 There are many other references available on the follow-on architectures to the 8086 and the interested reader is encouraged to seek them out

As we begin to study the 8086 architecture and instruction set architecture it will become obvious that so much of focus is on the DOS operating system and the PC run time environment From that perspective, we have an interesting counter example to the 68K architecture When we studied the 68K, we were running in an “emulation” environment because the native instruction set of your

PC and that of the 68K are incompatible So, a virtual 68K is created programmatically and that

Tiêu đề	Chapter 9
Trường học	Vietnam National University, Hanoi
Chuyên ngành	Hardware and Computer Organization
Thể loại	Lecture Notes
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